]> git.proxmox.com Git - qemu.git/blame - target-unicore32/cpu-qom.h
Open 2.0 development tree
[qemu.git] / target-unicore32 / cpu-qom.h
CommitLineData
ae0f5e9e
AF
1/*
2 * QEMU UniCore32 CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or (at your option) any
9 * later version. See the COPYING file in the top-level directory.
10 */
11#ifndef QEMU_UC32_CPU_QOM_H
12#define QEMU_UC32_CPU_QOM_H
13
14cccb61 14#include "qom/cpu.h"
ae0f5e9e
AF
15#include "cpu.h"
16
17#define TYPE_UNICORE32_CPU "unicore32-cpu"
18
19#define UNICORE32_CPU_CLASS(klass) \
20 OBJECT_CLASS_CHECK(UniCore32CPUClass, (klass), TYPE_UNICORE32_CPU)
21#define UNICORE32_CPU(obj) \
22 OBJECT_CHECK(UniCore32CPU, (obj), TYPE_UNICORE32_CPU)
23#define UNICORE32_CPU_GET_CLASS(obj) \
24 OBJECT_GET_CLASS(UniCore32CPUClass, (obj), TYPE_UNICORE32_CPU)
25
26/**
27 * UniCore32CPUClass:
088383e3 28 * @parent_realize: The parent class' realize handler.
ae0f5e9e
AF
29 *
30 * A UniCore32 CPU model.
31 */
32typedef struct UniCore32CPUClass {
33 /*< private >*/
34 CPUClass parent_class;
35 /*< public >*/
088383e3
AF
36
37 DeviceRealize parent_realize;
ae0f5e9e
AF
38} UniCore32CPUClass;
39
40/**
41 * UniCore32CPU:
42 * @env: #CPUUniCore32State
43 *
44 * A UniCore32 CPU.
45 */
46typedef struct UniCore32CPU {
47 /*< private >*/
48 CPUState parent_obj;
49 /*< public >*/
50
51 CPUUniCore32State env;
52} UniCore32CPU;
53
54static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env)
55{
6e42be7c 56 return container_of(env, UniCore32CPU, env);
ae0f5e9e
AF
57}
58
59#define ENV_GET_CPU(e) CPU(uc32_env_get_cpu(e))
60
fadf9825 61#define ENV_OFFSET offsetof(UniCore32CPU, env)
ae0f5e9e 62
97a8ea5a 63void uc32_cpu_do_interrupt(CPUState *cpu);
878096ee
AF
64void uc32_cpu_dump_state(CPUState *cpu, FILE *f,
65 fprintf_function cpu_fprintf, int flags);
00b941e5 66hwaddr uc32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
97a8ea5a 67
ae0f5e9e 68#endif