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1/*
2 * Copyright (c) 2012, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include "cpu.h"
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29#include "exec/exec-all.h"
30#include "exec/gdbstub.h"
176ac95e 31#include "qemu-common.h"
1de7afc9 32#include "qemu/host-utils.h"
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33
34#include "core-dc233c/core-isa.h"
35#include "overlay_tool.h"
36
37static const XtensaConfig dc233c = {
38 .name = "dc233c",
39 .options = XTENSA_OPTIONS,
40 .gdb_regmap = {
41 .num_regs = 121,
42 .num_core_regs = 52,
43 .reg = {
44#include "core-dc233c/gdb-config.c"
45 }
46 },
47 .nareg = XCHAL_NUM_AREGS,
48 .ndepc = 1,
49 EXCEPTIONS_SECTION,
50 INTERRUPTS_SECTION,
51 TLB_SECTION,
ebbfd5a0 52 DEBUG_SECTION,
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53 .clock_freq_khz = 10000,
54};
55
56REGISTER_CORE(dc233c)