[qemu.git] / target-xtensa / overlay_tool.h

/*
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
        a1, a2, a3, a4, a5, a6) \
    { .targno = (no), .type = (typ), .group = (grp) },

#ifndef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 0
#endif

#ifndef XCHAL_UNALIGNED_LOAD_HW
#define XCHAL_UNALIGNED_LOAD_HW 0
#endif

#ifndef XCHAL_HAVE_VECBASE
#define XCHAL_HAVE_VECBASE 0
#define XCHAL_VECBASE_RESET_VADDR 0
#endif

#ifndef XCHAL_HW_MIN_VERSION
#define XCHAL_HW_MIN_VERSION 0
#endif

#define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)

#define XTENSA_OPTIONS ( \
    XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
    XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
    XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
    XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
    XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
    XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
    XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
    XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
    XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
    XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
    XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
    XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
    XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
    XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
    XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
    XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
    XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
    XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
        XTENSA_OPTION_ATOMCTL) | \
    /* Interrupts and exceptions */ \
    XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
    XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
    XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
        XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
    XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
    XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
        XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
    XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
    /* Local memory, TODO */ \
    XCHAL_OPTION(XCHAL_ICACHE_WAYS, XTENSA_OPTION_ICACHE) | \
    XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
            XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
    XCHAL_OPTION(XCHAL_DCACHE_WAYS, XTENSA_OPTION_DCACHE) | \
    XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
            XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
    XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
    /* Memory protection and translation */ \
    XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
            XTENSA_OPTION_REGION_PROTECTION) | \
    XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
            XTENSA_OPTION_REGION_TRANSLATION) | \
    XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
    XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
    /* Other, TODO */ \
    XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
    XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\
    XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \
    XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \
    XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID))

#ifndef XCHAL_WINDOW_OF4_VECOFS
#define XCHAL_WINDOW_OF4_VECOFS         0x00000000
#define XCHAL_WINDOW_UF4_VECOFS         0x00000040
#define XCHAL_WINDOW_OF8_VECOFS         0x00000080
#define XCHAL_WINDOW_UF8_VECOFS         0x000000C0
#define XCHAL_WINDOW_OF12_VECOFS        0x00000100
#define XCHAL_WINDOW_UF12_VECOFS        0x00000140
#endif

#define EXCEPTION_VECTORS { \
        [EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \
        [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
            XCHAL_WINDOW_VECTORS_VADDR, \
        [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
            XCHAL_WINDOW_VECTORS_VADDR, \
        [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
            XCHAL_WINDOW_VECTORS_VADDR, \
        [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
            XCHAL_WINDOW_VECTORS_VADDR, \
        [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
            XCHAL_WINDOW_VECTORS_VADDR, \
        [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
            XCHAL_WINDOW_VECTORS_VADDR, \
        [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
        [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
        [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
        [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
    }

#define INTERRUPT_VECTORS { \
        0, \
        0, \
        XCHAL_INTLEVEL2_VECTOR_VADDR, \
        XCHAL_INTLEVEL3_VECTOR_VADDR, \
        XCHAL_INTLEVEL4_VECTOR_VADDR, \
        XCHAL_INTLEVEL5_VECTOR_VADDR, \
        XCHAL_INTLEVEL6_VECTOR_VADDR, \
        XCHAL_INTLEVEL7_VECTOR_VADDR, \
    }

#define LEVEL_MASKS { \
        [1] = XCHAL_INTLEVEL1_MASK, \
        [2] = XCHAL_INTLEVEL2_MASK, \
        [3] = XCHAL_INTLEVEL3_MASK, \
        [4] = XCHAL_INTLEVEL4_MASK, \
        [5] = XCHAL_INTLEVEL5_MASK, \
        [6] = XCHAL_INTLEVEL6_MASK, \
        [7] = XCHAL_INTLEVEL7_MASK, \
    }

#define INTTYPE_MASKS { \
        [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
        [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
        [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
    }

#define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
#define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
#define XTHAL_INTTYPE_NMI INTTYPE_NMI
#define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
#define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
#define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
#define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
#define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR


#define INTERRUPT(i) { \
        .level = XCHAL_INT ## i ## _LEVEL, \
        .inttype = XCHAL_INT ## i ## _TYPE, \
    }

#define INTERRUPTS { \
        [0] = INTERRUPT(0), \
        [1] = INTERRUPT(1), \
        [2] = INTERRUPT(2), \
        [3] = INTERRUPT(3), \
        [4] = INTERRUPT(4), \
        [5] = INTERRUPT(5), \
        [6] = INTERRUPT(6), \
        [7] = INTERRUPT(7), \
        [8] = INTERRUPT(8), \
        [9] = INTERRUPT(9), \
        [10] = INTERRUPT(10), \
        [11] = INTERRUPT(11), \
        [12] = INTERRUPT(12), \
        [13] = INTERRUPT(13), \
        [14] = INTERRUPT(14), \
        [15] = INTERRUPT(15), \
        [16] = INTERRUPT(16), \
        [17] = INTERRUPT(17), \
        [18] = INTERRUPT(18), \
        [19] = INTERRUPT(19), \
        [20] = INTERRUPT(20), \
        [21] = INTERRUPT(21), \
        [22] = INTERRUPT(22), \
        [23] = INTERRUPT(23), \
        [24] = INTERRUPT(24), \
        [25] = INTERRUPT(25), \
        [26] = INTERRUPT(26), \
        [27] = INTERRUPT(27), \
        [28] = INTERRUPT(28), \
        [29] = INTERRUPT(29), \
        [30] = INTERRUPT(30), \
        [31] = INTERRUPT(31), \
    }

#define TIMERINTS { \
        [0] = XCHAL_TIMER0_INTERRUPT, \
        [1] = XCHAL_TIMER1_INTERRUPT, \
        [2] = XCHAL_TIMER2_INTERRUPT, \
    }

#define EXTINTS { \
        [0] = XCHAL_EXTINT0_NUM, \
        [1] = XCHAL_EXTINT1_NUM, \
        [2] = XCHAL_EXTINT2_NUM, \
        [3] = XCHAL_EXTINT3_NUM, \
        [4] = XCHAL_EXTINT4_NUM, \
        [5] = XCHAL_EXTINT5_NUM, \
        [6] = XCHAL_EXTINT6_NUM, \
        [7] = XCHAL_EXTINT7_NUM, \
        [8] = XCHAL_EXTINT8_NUM, \
        [9] = XCHAL_EXTINT9_NUM, \
        [10] = XCHAL_EXTINT10_NUM, \
        [11] = XCHAL_EXTINT11_NUM, \
        [12] = XCHAL_EXTINT12_NUM, \
        [13] = XCHAL_EXTINT13_NUM, \
        [14] = XCHAL_EXTINT14_NUM, \
        [15] = XCHAL_EXTINT15_NUM, \
        [16] = XCHAL_EXTINT16_NUM, \
        [17] = XCHAL_EXTINT17_NUM, \
        [18] = XCHAL_EXTINT18_NUM, \
        [19] = XCHAL_EXTINT19_NUM, \
        [20] = XCHAL_EXTINT20_NUM, \
        [21] = XCHAL_EXTINT21_NUM, \
        [22] = XCHAL_EXTINT22_NUM, \
        [23] = XCHAL_EXTINT23_NUM, \
        [24] = XCHAL_EXTINT24_NUM, \
        [25] = XCHAL_EXTINT25_NUM, \
        [26] = XCHAL_EXTINT26_NUM, \
        [27] = XCHAL_EXTINT27_NUM, \
        [28] = XCHAL_EXTINT28_NUM, \
        [29] = XCHAL_EXTINT29_NUM, \
        [30] = XCHAL_EXTINT30_NUM, \
        [31] = XCHAL_EXTINT31_NUM, \
    }

#define EXCEPTIONS_SECTION \
    .excm_level = XCHAL_EXCM_LEVEL, \
    .vecbase = XCHAL_VECBASE_RESET_VADDR, \
    .exception_vector = EXCEPTION_VECTORS

#define INTERRUPTS_SECTION \
    .ninterrupt = XCHAL_NUM_INTERRUPTS, \
    .nlevel = XCHAL_NUM_INTLEVELS, \
    .interrupt_vector = INTERRUPT_VECTORS, \
    .level_mask = LEVEL_MASKS, \
    .inttype_mask = INTTYPE_MASKS, \
    .interrupt = INTERRUPTS, \
    .nccompare = XCHAL_NUM_TIMERS, \
    .timerint = TIMERINTS, \
    .nextint = XCHAL_NUM_EXTINTERRUPTS, \
    .extint = EXTINTS

#if XCHAL_HAVE_PTP_MMU

#define TLB_TEMPLATE(ways, refill_way_size, way56) { \
        .nways = ways, \
        .way_size = { \
            (refill_way_size), (refill_way_size), \
            (refill_way_size), (refill_way_size), \
            4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
        }, \
        .varway56 = (way56), \
        .nrefillentries = (refill_way_size) * 4, \
    }

#define ITLB(varway56) \
    TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)

#define DTLB(varway56) \
    TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)

#define TLB_SECTION \
    .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
    .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)

#elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR

#define TLB_TEMPLATE { \
        .nways = 1, \
        .way_size = { \
            8, \
        } \
    }

#define TLB_SECTION \
    .itlb = TLB_TEMPLATE, \
    .dtlb = TLB_TEMPLATE

#endif

#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
#define REGISTER_CORE(core) \
    static void __attribute__((constructor)) register_core(void) \
    { \
        static XtensaConfigList node = { \
            .config = &core, \
        }; \
        xtensa_register_core(&node); \
    }
#else
#define REGISTER_CORE(core)
#endif

#define DEBUG_SECTION \
    .debug_level = XCHAL_DEBUGLEVEL, \
    .nibreak = XCHAL_NUM_IBREAK, \
    .ndbreak = XCHAL_NUM_DBREAK

#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
#define XCHAL_INTLEVEL7_VECTOR_VADDR 0
#endif


#if XCHAL_NUM_INTERRUPTS <= 0
#define XCHAL_INT0_LEVEL 0
#define XCHAL_INT0_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 1
#define XCHAL_INT1_LEVEL 0
#define XCHAL_INT1_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 2
#define XCHAL_INT2_LEVEL 0
#define XCHAL_INT2_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 3
#define XCHAL_INT3_LEVEL 0
#define XCHAL_INT3_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 4
#define XCHAL_INT4_LEVEL 0
#define XCHAL_INT4_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 5
#define XCHAL_INT5_LEVEL 0
#define XCHAL_INT5_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 6
#define XCHAL_INT6_LEVEL 0
#define XCHAL_INT6_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 7
#define XCHAL_INT7_LEVEL 0
#define XCHAL_INT7_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 8
#define XCHAL_INT8_LEVEL 0
#define XCHAL_INT8_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 9
#define XCHAL_INT9_LEVEL 0
#define XCHAL_INT9_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 10
#define XCHAL_INT10_LEVEL 0
#define XCHAL_INT10_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 11
#define XCHAL_INT11_LEVEL 0
#define XCHAL_INT11_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 12
#define XCHAL_INT12_LEVEL 0
#define XCHAL_INT12_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 13
#define XCHAL_INT13_LEVEL 0
#define XCHAL_INT13_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 14
#define XCHAL_INT14_LEVEL 0
#define XCHAL_INT14_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 15
#define XCHAL_INT15_LEVEL 0
#define XCHAL_INT15_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 16
#define XCHAL_INT16_LEVEL 0
#define XCHAL_INT16_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 17
#define XCHAL_INT17_LEVEL 0
#define XCHAL_INT17_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 18
#define XCHAL_INT18_LEVEL 0
#define XCHAL_INT18_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 19
#define XCHAL_INT19_LEVEL 0
#define XCHAL_INT19_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 20
#define XCHAL_INT20_LEVEL 0
#define XCHAL_INT20_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 21
#define XCHAL_INT21_LEVEL 0
#define XCHAL_INT21_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 22
#define XCHAL_INT22_LEVEL 0
#define XCHAL_INT22_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 23
#define XCHAL_INT23_LEVEL 0
#define XCHAL_INT23_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 24
#define XCHAL_INT24_LEVEL 0
#define XCHAL_INT24_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 25
#define XCHAL_INT25_LEVEL 0
#define XCHAL_INT25_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 26
#define XCHAL_INT26_LEVEL 0
#define XCHAL_INT26_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 27
#define XCHAL_INT27_LEVEL 0
#define XCHAL_INT27_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 28
#define XCHAL_INT28_LEVEL 0
#define XCHAL_INT28_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 29
#define XCHAL_INT29_LEVEL 0
#define XCHAL_INT29_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 30
#define XCHAL_INT30_LEVEL 0
#define XCHAL_INT30_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 31
#define XCHAL_INT31_LEVEL 0
#define XCHAL_INT31_TYPE 0
#endif


#if XCHAL_NUM_EXTINTERRUPTS <= 0
#define XCHAL_EXTINT0_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 1
#define XCHAL_EXTINT1_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 2
#define XCHAL_EXTINT2_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 3
#define XCHAL_EXTINT3_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 4
#define XCHAL_EXTINT4_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 5
#define XCHAL_EXTINT5_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 6
#define XCHAL_EXTINT6_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 7
#define XCHAL_EXTINT7_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 8
#define XCHAL_EXTINT8_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 9
#define XCHAL_EXTINT9_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 10
#define XCHAL_EXTINT10_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 11
#define XCHAL_EXTINT11_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 12
#define XCHAL_EXTINT12_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 13
#define XCHAL_EXTINT13_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 14
#define XCHAL_EXTINT14_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 15
#define XCHAL_EXTINT15_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 16
#define XCHAL_EXTINT16_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 17
#define XCHAL_EXTINT17_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 18
#define XCHAL_EXTINT18_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 19
#define XCHAL_EXTINT19_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 20
#define XCHAL_EXTINT20_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 21
#define XCHAL_EXTINT21_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 22
#define XCHAL_EXTINT22_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 23
#define XCHAL_EXTINT23_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 24
#define XCHAL_EXTINT24_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 25
#define XCHAL_EXTINT25_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 26
#define XCHAL_EXTINT26_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 27
#define XCHAL_EXTINT27_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 28
#define XCHAL_EXTINT28_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 29
#define XCHAL_EXTINT29_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 30
#define XCHAL_EXTINT30_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 31
#define XCHAL_EXTINT31_NUM 0
#endif


#define XTHAL_TIMER_UNCONFIGURED 0
Commit	Line	Data
ac8b7db4 MF	1	/*
	2	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	* * Redistributions of source code must retain the above copyright
	8	* notice, this list of conditions and the following disclaimer.
	9	* * Redistributions in binary form must reproduce the above copyright
	10	* notice, this list of conditions and the following disclaimer in the
	11	* documentation and/or other materials provided with the distribution.
	12	* * Neither the name of the Open Source and Linux Lab nor the
	13	* names of its contributors may be used to endorse or promote products
	14	* derived from this software without specific prior written permission.
	15	*
	16	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	20	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	21	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	22	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	23	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	24	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	25	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	*/
	27
	28	#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
	29	a1, a2, a3, a4, a5, a6) \
	30	{ .targno = (no), .type = (typ), .group = (grp) },
	31
	32	#ifndef XCHAL_HAVE_DIV32
	33	#define XCHAL_HAVE_DIV32 0
	34	#endif
	35
	36	#ifndef XCHAL_UNALIGNED_LOAD_HW
	37	#define XCHAL_UNALIGNED_LOAD_HW 0
	38	#endif
	39
	40	#ifndef XCHAL_HAVE_VECBASE
	41	#define XCHAL_HAVE_VECBASE 0
	42	#define XCHAL_VECBASE_RESET_VADDR 0
	43	#endif
	44
fcc803d1 MF	45	#ifndef XCHAL_HW_MIN_VERSION
	46	#define XCHAL_HW_MIN_VERSION 0
	47	#endif
	48
ac8b7db4 MF	49	#define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
	50
	51	#define XTENSA_OPTIONS ( \
	52	XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) \| \
	53	XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) \| \
	54	XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) \| \
	55	XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) \| \
	56	XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) \| \
	57	XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) \| \
	58	XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) \| \
	59	XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) \| \
	60	XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) \| \
	61	XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) \| \
	62	XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) \| \
	63	XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) \| \
	64	XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) \| \
10f6ca03	65	XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) \| \
ac8b7db4 MF	66	XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) \| \
	67	XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) \| \
	68	XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) \| \
fcc803d1 MF	69	XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
fcc803d1 MF	70	XTENSA_OPTION_ATOMCTL) \| \
ac8b7db4 MF	71	/* Interrupts and exceptions */ \
	72	XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) \| \
	73	XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) \| \
	74	XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
	75	XTENSA_OPTION_UNALIGNED_EXCEPTION) \| \
	76	XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) \| \
	77	XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
	78	XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) \| \
	79	XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) \| \
	80	/* Local memory, TODO */ \
0c852e17 MF	81	XCHAL_OPTION(XCHAL_ICACHE_WAYS, XTENSA_OPTION_ICACHE) \| \
	82	XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
	83	XTENSA_OPTION_ICACHE_INDEX_LOCK) \| \
	84	XCHAL_OPTION(XCHAL_DCACHE_WAYS, XTENSA_OPTION_DCACHE) \| \
	85	XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
	86	XTENSA_OPTION_DCACHE_INDEX_LOCK) \| \
ac8b7db4 MF	87	XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) \| \
	88	/* Memory protection and translation */ \
	89	XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
	90	XTENSA_OPTION_REGION_PROTECTION) \| \
	91	XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
	92	XTENSA_OPTION_REGION_TRANSLATION) \| \
	93	XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) \| \
4e41d2f5	94	XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) \| \
ac8b7db4 MF	95	/* Other, TODO */ \
ac8b7db4 MF	96	XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) \| \
fe0bd475	97	XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) \|\
b7909d81	98	XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) \| \
fe0bd475 MF	99	XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) \| \
fe0bd475 MF	100	XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID))
ac8b7db4 MF	101
	102	#ifndef XCHAL_WINDOW_OF4_VECOFS
	103	#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
	104	#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
	105	#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
	106	#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
	107	#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
	108	#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
	109	#endif
	110
	111	#define EXCEPTION_VECTORS { \
	112	[EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \
	113	[EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
	114	XCHAL_WINDOW_VECTORS_VADDR, \
	115	[EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
	116	XCHAL_WINDOW_VECTORS_VADDR, \
	117	[EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
	118	XCHAL_WINDOW_VECTORS_VADDR, \
	119	[EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
	120	XCHAL_WINDOW_VECTORS_VADDR, \
	121	[EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
	122	XCHAL_WINDOW_VECTORS_VADDR, \
	123	[EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
	124	XCHAL_WINDOW_VECTORS_VADDR, \
	125	[EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
	126	[EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
	127	[EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
18da9326	128	[EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
ac8b7db4 MF	129	}
	130
	131	#define INTERRUPT_VECTORS { \
	132	0, \
	133	0, \
	134	XCHAL_INTLEVEL2_VECTOR_VADDR, \
	135	XCHAL_INTLEVEL3_VECTOR_VADDR, \
	136	XCHAL_INTLEVEL4_VECTOR_VADDR, \
	137	XCHAL_INTLEVEL5_VECTOR_VADDR, \
	138	XCHAL_INTLEVEL6_VECTOR_VADDR, \
	139	XCHAL_INTLEVEL7_VECTOR_VADDR, \
	140	}
	141
	142	#define LEVEL_MASKS { \
	143	[1] = XCHAL_INTLEVEL1_MASK, \
	144	[2] = XCHAL_INTLEVEL2_MASK, \
	145	[3] = XCHAL_INTLEVEL3_MASK, \
	146	[4] = XCHAL_INTLEVEL4_MASK, \
	147	[5] = XCHAL_INTLEVEL5_MASK, \
	148	[6] = XCHAL_INTLEVEL6_MASK, \
	149	[7] = XCHAL_INTLEVEL7_MASK, \
	150	}
	151
	152	#define INTTYPE_MASKS { \
	153	[INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
	154	[INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
	155	[INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
	156	}
	157
	158	#define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
	159	#define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
	160	#define XTHAL_INTTYPE_NMI INTTYPE_NMI
	161	#define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
	162	#define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
	163	#define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
	164	#define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
	165	#define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
	166
	167
	168	#define INTERRUPT(i) { \
	169	.level = XCHAL_INT ## i ## _LEVEL, \
	170	.inttype = XCHAL_INT ## i ## _TYPE, \
	171	}
	172
	173	#define INTERRUPTS { \
	174	[0] = INTERRUPT(0), \
	175	[1] = INTERRUPT(1), \
	176	[2] = INTERRUPT(2), \
	177	[3] = INTERRUPT(3), \
	178	[4] = INTERRUPT(4), \
	179	[5] = INTERRUPT(5), \
	180	[6] = INTERRUPT(6), \
	181	[7] = INTERRUPT(7), \
	182	[8] = INTERRUPT(8), \
	183	[9] = INTERRUPT(9), \
	184	[10] = INTERRUPT(10), \
	185	[11] = INTERRUPT(11), \
	186	[12] = INTERRUPT(12), \
	187	[13] = INTERRUPT(13), \
	188	[14] = INTERRUPT(14), \
	189	[15] = INTERRUPT(15), \
	190	[16] = INTERRUPT(16), \
	191	[17] = INTERRUPT(17), \
	192	[18] = INTERRUPT(18), \
193	[19] = INTERRUPT(19), \
194	[20] = INTERRUPT(20), \
195	[21] = INTERRUPT(21), \
196	[22] = INTERRUPT(22), \
197	[23] = INTERRUPT(23), \
198	[24] = INTERRUPT(24), \
199	[25] = INTERRUPT(25), \
200	[26] = INTERRUPT(26), \
201	[27] = INTERRUPT(27), \
202	[28] = INTERRUPT(28), \
203	[29] = INTERRUPT(29), \
204	[30] = INTERRUPT(30), \
205	[31] = INTERRUPT(31), \
206	}
207
208	#define TIMERINTS { \
209	[0] = XCHAL_TIMER0_INTERRUPT, \
210	[1] = XCHAL_TIMER1_INTERRUPT, \
211	[2] = XCHAL_TIMER2_INTERRUPT, \
212	}
213
214	#define EXTINTS { \
215	[0] = XCHAL_EXTINT0_NUM, \
216	[1] = XCHAL_EXTINT1_NUM, \
217	[2] = XCHAL_EXTINT2_NUM, \
218	[3] = XCHAL_EXTINT3_NUM, \
219	[4] = XCHAL_EXTINT4_NUM, \
220	[5] = XCHAL_EXTINT5_NUM, \
221	[6] = XCHAL_EXTINT6_NUM, \
222	[7] = XCHAL_EXTINT7_NUM, \
223	[8] = XCHAL_EXTINT8_NUM, \
224	[9] = XCHAL_EXTINT9_NUM, \
225	[10] = XCHAL_EXTINT10_NUM, \
226	[11] = XCHAL_EXTINT11_NUM, \
227	[12] = XCHAL_EXTINT12_NUM, \
228	[13] = XCHAL_EXTINT13_NUM, \
229	[14] = XCHAL_EXTINT14_NUM, \
230	[15] = XCHAL_EXTINT15_NUM, \
231	[16] = XCHAL_EXTINT16_NUM, \
232	[17] = XCHAL_EXTINT17_NUM, \
233	[18] = XCHAL_EXTINT18_NUM, \
234	[19] = XCHAL_EXTINT19_NUM, \
235	[20] = XCHAL_EXTINT20_NUM, \
236	[21] = XCHAL_EXTINT21_NUM, \
237	[22] = XCHAL_EXTINT22_NUM, \
238	[23] = XCHAL_EXTINT23_NUM, \
239	[24] = XCHAL_EXTINT24_NUM, \
240	[25] = XCHAL_EXTINT25_NUM, \
241	[26] = XCHAL_EXTINT26_NUM, \
242	[27] = XCHAL_EXTINT27_NUM, \
243	[28] = XCHAL_EXTINT28_NUM, \
244	[29] = XCHAL_EXTINT29_NUM, \
245	[30] = XCHAL_EXTINT30_NUM, \
246	[31] = XCHAL_EXTINT31_NUM, \
247	}
248
249	#define EXCEPTIONS_SECTION \
250	.excm_level = XCHAL_EXCM_LEVEL, \
251	.vecbase = XCHAL_VECBASE_RESET_VADDR, \
252	.exception_vector = EXCEPTION_VECTORS
253
254	#define INTERRUPTS_SECTION \
255	.ninterrupt = XCHAL_NUM_INTERRUPTS, \
256	.nlevel = XCHAL_NUM_INTLEVELS, \
257	.interrupt_vector = INTERRUPT_VECTORS, \
258	.level_mask = LEVEL_MASKS, \
259	.inttype_mask = INTTYPE_MASKS, \
260	.interrupt = INTERRUPTS, \
261	.nccompare = XCHAL_NUM_TIMERS, \
262	.timerint = TIMERINTS, \
263	.nextint = XCHAL_NUM_EXTINTERRUPTS, \
264	.extint = EXTINTS
265
b96ac3e4 MF	266	#if XCHAL_HAVE_PTP_MMU
b96ac3e4 MF	267
ac8b7db4 MF	268	#define TLB_TEMPLATE(ways, refill_way_size, way56) { \
	269	.nways = ways, \
	270	.way_size = { \
	271	(refill_way_size), (refill_way_size), \
	272	(refill_way_size), (refill_way_size), \
0fdd2e1d	273	4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
ac8b7db4 MF	274	}, \
	275	.varway56 = (way56), \
	276	.nrefillentries = (refill_way_size) * 4, \
	277	}
	278
	279	#define ITLB(varway56) \
	280	TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
	281
	282	#define DTLB(varway56) \
	283	TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
	284
ac8b7db4 MF	285	#define TLB_SECTION \
	286	.itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
	287	.dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
b96ac3e4 MF	288
	289	#elif XCHAL_HAVE_XLT_CACHEATTR \|\| XCHAL_HAVE_MIMIC_CACHEATTR
	290
	291	#define TLB_TEMPLATE { \
	292	.nways = 1, \
	293	.way_size = { \
	294	8, \
	295	} \
	296	}
	297
	298	#define TLB_SECTION \
	299	.itlb = TLB_TEMPLATE, \
	300	.dtlb = TLB_TEMPLATE
	301
ac8b7db4 MF	302	#endif
	303
	304	#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
	305	#define REGISTER_CORE(core) \
	306	static void __attribute__((constructor)) register_core(void) \
	307	{ \
	308	static XtensaConfigList node = { \
	309	.config = &core, \
	310	}; \
	311	xtensa_register_core(&node); \
	312	}
	313	#else
	314	#define REGISTER_CORE(core)
	315	#endif
	316
18da9326 MF	317	#define DEBUG_SECTION \
	318	.debug_level = XCHAL_DEBUGLEVEL, \
	319	.nibreak = XCHAL_NUM_IBREAK, \
	320	.ndbreak = XCHAL_NUM_DBREAK
ac8b7db4 MF	321
	322	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
	323	#define XCHAL_INTLEVEL2_VECTOR_VADDR 0
	324	#endif
	325	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
	326	#define XCHAL_INTLEVEL3_VECTOR_VADDR 0
	327	#endif
	328	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
	329	#define XCHAL_INTLEVEL4_VECTOR_VADDR 0
	330	#endif
	331	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
	332	#define XCHAL_INTLEVEL5_VECTOR_VADDR 0
	333	#endif
	334	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
	335	#define XCHAL_INTLEVEL6_VECTOR_VADDR 0
	336	#endif
	337	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
	338	#define XCHAL_INTLEVEL7_VECTOR_VADDR 0
	339	#endif
	340
	341
	342	#if XCHAL_NUM_INTERRUPTS <= 0
	343	#define XCHAL_INT0_LEVEL 0
	344	#define XCHAL_INT0_TYPE 0
	345	#endif
	346	#if XCHAL_NUM_INTERRUPTS <= 1
	347	#define XCHAL_INT1_LEVEL 0
	348	#define XCHAL_INT1_TYPE 0
	349	#endif
	350	#if XCHAL_NUM_INTERRUPTS <= 2
	351	#define XCHAL_INT2_LEVEL 0
	352	#define XCHAL_INT2_TYPE 0
	353	#endif
	354	#if XCHAL_NUM_INTERRUPTS <= 3
	355	#define XCHAL_INT3_LEVEL 0
	356	#define XCHAL_INT3_TYPE 0
	357	#endif
	358	#if XCHAL_NUM_INTERRUPTS <= 4
	359	#define XCHAL_INT4_LEVEL 0
	360	#define XCHAL_INT4_TYPE 0
	361	#endif
	362	#if XCHAL_NUM_INTERRUPTS <= 5
	363	#define XCHAL_INT5_LEVEL 0
	364	#define XCHAL_INT5_TYPE 0
	365	#endif
	366	#if XCHAL_NUM_INTERRUPTS <= 6
	367	#define XCHAL_INT6_LEVEL 0
	368	#define XCHAL_INT6_TYPE 0
	369	#endif
	370	#if XCHAL_NUM_INTERRUPTS <= 7
	371	#define XCHAL_INT7_LEVEL 0
	372	#define XCHAL_INT7_TYPE 0
	373	#endif
	374	#if XCHAL_NUM_INTERRUPTS <= 8
	375	#define XCHAL_INT8_LEVEL 0
	376	#define XCHAL_INT8_TYPE 0
	377	#endif
	378	#if XCHAL_NUM_INTERRUPTS <= 9
	379	#define XCHAL_INT9_LEVEL 0
	380	#define XCHAL_INT9_TYPE 0
	381	#endif
	382	#if XCHAL_NUM_INTERRUPTS <= 10
	383	#define XCHAL_INT10_LEVEL 0
	384	#define XCHAL_INT10_TYPE 0
385	#endif
386	#if XCHAL_NUM_INTERRUPTS <= 11
387	#define XCHAL_INT11_LEVEL 0
388	#define XCHAL_INT11_TYPE 0
389	#endif
390	#if XCHAL_NUM_INTERRUPTS <= 12
391	#define XCHAL_INT12_LEVEL 0
392	#define XCHAL_INT12_TYPE 0
393	#endif
394	#if XCHAL_NUM_INTERRUPTS <= 13
395	#define XCHAL_INT13_LEVEL 0
396	#define XCHAL_INT13_TYPE 0
397	#endif
398	#if XCHAL_NUM_INTERRUPTS <= 14
399	#define XCHAL_INT14_LEVEL 0
400	#define XCHAL_INT14_TYPE 0
401	#endif
402	#if XCHAL_NUM_INTERRUPTS <= 15
403	#define XCHAL_INT15_LEVEL 0
404	#define XCHAL_INT15_TYPE 0
405	#endif
406	#if XCHAL_NUM_INTERRUPTS <= 16
407	#define XCHAL_INT16_LEVEL 0
408	#define XCHAL_INT16_TYPE 0
409	#endif
410	#if XCHAL_NUM_INTERRUPTS <= 17
411	#define XCHAL_INT17_LEVEL 0
412	#define XCHAL_INT17_TYPE 0
413	#endif
414	#if XCHAL_NUM_INTERRUPTS <= 18
415	#define XCHAL_INT18_LEVEL 0
416	#define XCHAL_INT18_TYPE 0
417	#endif
418	#if XCHAL_NUM_INTERRUPTS <= 19
419	#define XCHAL_INT19_LEVEL 0
420	#define XCHAL_INT19_TYPE 0
421	#endif
422	#if XCHAL_NUM_INTERRUPTS <= 20
423	#define XCHAL_INT20_LEVEL 0
424	#define XCHAL_INT20_TYPE 0
425	#endif
426	#if XCHAL_NUM_INTERRUPTS <= 21
427	#define XCHAL_INT21_LEVEL 0
428	#define XCHAL_INT21_TYPE 0
429	#endif
430	#if XCHAL_NUM_INTERRUPTS <= 22
431	#define XCHAL_INT22_LEVEL 0
432	#define XCHAL_INT22_TYPE 0
433	#endif
434	#if XCHAL_NUM_INTERRUPTS <= 23
435	#define XCHAL_INT23_LEVEL 0
436	#define XCHAL_INT23_TYPE 0
437	#endif
438	#if XCHAL_NUM_INTERRUPTS <= 24
439	#define XCHAL_INT24_LEVEL 0
440	#define XCHAL_INT24_TYPE 0
441	#endif
442	#if XCHAL_NUM_INTERRUPTS <= 25
443	#define XCHAL_INT25_LEVEL 0
444	#define XCHAL_INT25_TYPE 0
445	#endif
446	#if XCHAL_NUM_INTERRUPTS <= 26
447	#define XCHAL_INT26_LEVEL 0
448	#define XCHAL_INT26_TYPE 0
449	#endif
450	#if XCHAL_NUM_INTERRUPTS <= 27
451	#define XCHAL_INT27_LEVEL 0
452	#define XCHAL_INT27_TYPE 0
453	#endif
454	#if XCHAL_NUM_INTERRUPTS <= 28
455	#define XCHAL_INT28_LEVEL 0
456	#define XCHAL_INT28_TYPE 0
457	#endif
458	#if XCHAL_NUM_INTERRUPTS <= 29
459	#define XCHAL_INT29_LEVEL 0
460	#define XCHAL_INT29_TYPE 0
461	#endif
462	#if XCHAL_NUM_INTERRUPTS <= 30
463	#define XCHAL_INT30_LEVEL 0
464	#define XCHAL_INT30_TYPE 0
465	#endif
466	#if XCHAL_NUM_INTERRUPTS <= 31
467	#define XCHAL_INT31_LEVEL 0
468	#define XCHAL_INT31_TYPE 0
469	#endif
470
471
472	#if XCHAL_NUM_EXTINTERRUPTS <= 0
473	#define XCHAL_EXTINT0_NUM 0
474	#endif
475	#if XCHAL_NUM_EXTINTERRUPTS <= 1
476	#define XCHAL_EXTINT1_NUM 0
477	#endif
478	#if XCHAL_NUM_EXTINTERRUPTS <= 2
479	#define XCHAL_EXTINT2_NUM 0
480	#endif
481	#if XCHAL_NUM_EXTINTERRUPTS <= 3
482	#define XCHAL_EXTINT3_NUM 0
483	#endif
484	#if XCHAL_NUM_EXTINTERRUPTS <= 4
485	#define XCHAL_EXTINT4_NUM 0
486	#endif
487	#if XCHAL_NUM_EXTINTERRUPTS <= 5
488	#define XCHAL_EXTINT5_NUM 0
489	#endif
490	#if XCHAL_NUM_EXTINTERRUPTS <= 6
491	#define XCHAL_EXTINT6_NUM 0
492	#endif
493	#if XCHAL_NUM_EXTINTERRUPTS <= 7
494	#define XCHAL_EXTINT7_NUM 0
495	#endif
496	#if XCHAL_NUM_EXTINTERRUPTS <= 8
497	#define XCHAL_EXTINT8_NUM 0
498	#endif
499	#if XCHAL_NUM_EXTINTERRUPTS <= 9
500	#define XCHAL_EXTINT9_NUM 0
501	#endif
502	#if XCHAL_NUM_EXTINTERRUPTS <= 10
503	#define XCHAL_EXTINT10_NUM 0
504	#endif
505	#if XCHAL_NUM_EXTINTERRUPTS <= 11
506	#define XCHAL_EXTINT11_NUM 0
507	#endif
508	#if XCHAL_NUM_EXTINTERRUPTS <= 12
509	#define XCHAL_EXTINT12_NUM 0
510	#endif
511	#if XCHAL_NUM_EXTINTERRUPTS <= 13
512	#define XCHAL_EXTINT13_NUM 0
513	#endif
514	#if XCHAL_NUM_EXTINTERRUPTS <= 14
515	#define XCHAL_EXTINT14_NUM 0
516	#endif
517	#if XCHAL_NUM_EXTINTERRUPTS <= 15
518	#define XCHAL_EXTINT15_NUM 0
519	#endif
520	#if XCHAL_NUM_EXTINTERRUPTS <= 16
521	#define XCHAL_EXTINT16_NUM 0
522	#endif
523	#if XCHAL_NUM_EXTINTERRUPTS <= 17
524	#define XCHAL_EXTINT17_NUM 0
525	#endif
526	#if XCHAL_NUM_EXTINTERRUPTS <= 18
527	#define XCHAL_EXTINT18_NUM 0
528	#endif
529	#if XCHAL_NUM_EXTINTERRUPTS <= 19
530	#define XCHAL_EXTINT19_NUM 0
531	#endif
532	#if XCHAL_NUM_EXTINTERRUPTS <= 20
533	#define XCHAL_EXTINT20_NUM 0
534	#endif
535	#if XCHAL_NUM_EXTINTERRUPTS <= 21
536	#define XCHAL_EXTINT21_NUM 0
537	#endif
538	#if XCHAL_NUM_EXTINTERRUPTS <= 22
539	#define XCHAL_EXTINT22_NUM 0
540	#endif
541	#if XCHAL_NUM_EXTINTERRUPTS <= 23
542	#define XCHAL_EXTINT23_NUM 0
543	#endif
544	#if XCHAL_NUM_EXTINTERRUPTS <= 24
545	#define XCHAL_EXTINT24_NUM 0
546	#endif
547	#if XCHAL_NUM_EXTINTERRUPTS <= 25
548	#define XCHAL_EXTINT25_NUM 0
549	#endif
550	#if XCHAL_NUM_EXTINTERRUPTS <= 26
551	#define XCHAL_EXTINT26_NUM 0
552	#endif
553	#if XCHAL_NUM_EXTINTERRUPTS <= 27
554	#define XCHAL_EXTINT27_NUM 0
555	#endif
556	#if XCHAL_NUM_EXTINTERRUPTS <= 28
557	#define XCHAL_EXTINT28_NUM 0
558	#endif
559	#if XCHAL_NUM_EXTINTERRUPTS <= 29
560	#define XCHAL_EXTINT29_NUM 0
561	#endif
562	#if XCHAL_NUM_EXTINTERRUPTS <= 30
563	#define XCHAL_EXTINT30_NUM 0
564	#endif
565	#if XCHAL_NUM_EXTINTERRUPTS <= 31
566	#define XCHAL_EXTINT31_NUM 0
567	#endif
568
569
570	#define XTHAL_TIMER_UNCONFIGURED 0