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477ba620 AJ |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net> | |
5 | * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
3cf246f0 RH |
26 | #include "tcg-be-null.h" |
27 | ||
477ba620 AJ |
28 | /* |
29 | * Register definitions | |
30 | */ | |
31 | ||
32 | #ifndef NDEBUG | |
33 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { | |
34 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
35 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
36 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
37 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
38 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
39 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
40 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
41 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
42 | }; | |
43 | #endif | |
44 | ||
6781d08d RH |
45 | #ifdef CONFIG_USE_GUEST_BASE |
46 | #define TCG_GUEST_BASE_REG TCG_REG_R55 | |
47 | #else | |
48 | #define TCG_GUEST_BASE_REG TCG_REG_R0 | |
49 | #endif | |
255108c0 RH |
50 | #ifndef GUEST_BASE |
51 | #define GUEST_BASE 0 | |
52 | #endif | |
6781d08d | 53 | |
477ba620 AJ |
54 | /* Branch registers */ |
55 | enum { | |
56 | TCG_REG_B0 = 0, | |
57 | TCG_REG_B1, | |
58 | TCG_REG_B2, | |
59 | TCG_REG_B3, | |
60 | TCG_REG_B4, | |
61 | TCG_REG_B5, | |
62 | TCG_REG_B6, | |
63 | TCG_REG_B7, | |
64 | }; | |
65 | ||
66 | /* Floating point registers */ | |
67 | enum { | |
68 | TCG_REG_F0 = 0, | |
69 | TCG_REG_F1, | |
70 | TCG_REG_F2, | |
71 | TCG_REG_F3, | |
72 | TCG_REG_F4, | |
73 | TCG_REG_F5, | |
74 | TCG_REG_F6, | |
75 | TCG_REG_F7, | |
76 | TCG_REG_F8, | |
77 | TCG_REG_F9, | |
78 | TCG_REG_F10, | |
79 | TCG_REG_F11, | |
80 | TCG_REG_F12, | |
81 | TCG_REG_F13, | |
82 | TCG_REG_F14, | |
83 | TCG_REG_F15, | |
84 | }; | |
85 | ||
86 | /* Predicate registers */ | |
87 | enum { | |
88 | TCG_REG_P0 = 0, | |
89 | TCG_REG_P1, | |
90 | TCG_REG_P2, | |
91 | TCG_REG_P3, | |
92 | TCG_REG_P4, | |
93 | TCG_REG_P5, | |
94 | TCG_REG_P6, | |
95 | TCG_REG_P7, | |
96 | TCG_REG_P8, | |
97 | TCG_REG_P9, | |
98 | TCG_REG_P10, | |
99 | TCG_REG_P11, | |
100 | TCG_REG_P12, | |
101 | TCG_REG_P13, | |
102 | TCG_REG_P14, | |
103 | TCG_REG_P15, | |
104 | }; | |
105 | ||
106 | /* Application registers */ | |
107 | enum { | |
108 | TCG_REG_PFS = 64, | |
109 | }; | |
110 | ||
111 | static const int tcg_target_reg_alloc_order[] = { | |
477ba620 AJ |
112 | TCG_REG_R35, |
113 | TCG_REG_R36, | |
114 | TCG_REG_R37, | |
115 | TCG_REG_R38, | |
116 | TCG_REG_R39, | |
117 | TCG_REG_R40, | |
118 | TCG_REG_R41, | |
119 | TCG_REG_R42, | |
120 | TCG_REG_R43, | |
121 | TCG_REG_R44, | |
122 | TCG_REG_R45, | |
123 | TCG_REG_R46, | |
124 | TCG_REG_R47, | |
125 | TCG_REG_R48, | |
126 | TCG_REG_R49, | |
127 | TCG_REG_R50, | |
128 | TCG_REG_R51, | |
129 | TCG_REG_R52, | |
130 | TCG_REG_R53, | |
131 | TCG_REG_R54, | |
132 | TCG_REG_R55, | |
133 | TCG_REG_R14, | |
134 | TCG_REG_R15, | |
135 | TCG_REG_R16, | |
136 | TCG_REG_R17, | |
137 | TCG_REG_R18, | |
138 | TCG_REG_R19, | |
139 | TCG_REG_R20, | |
140 | TCG_REG_R21, | |
141 | TCG_REG_R22, | |
142 | TCG_REG_R23, | |
143 | TCG_REG_R24, | |
144 | TCG_REG_R25, | |
145 | TCG_REG_R26, | |
146 | TCG_REG_R27, | |
147 | TCG_REG_R28, | |
148 | TCG_REG_R29, | |
149 | TCG_REG_R30, | |
150 | TCG_REG_R31, | |
151 | TCG_REG_R56, | |
152 | TCG_REG_R57, | |
153 | TCG_REG_R58, | |
154 | TCG_REG_R59, | |
155 | TCG_REG_R60, | |
156 | TCG_REG_R61, | |
157 | TCG_REG_R62, | |
158 | TCG_REG_R63, | |
159 | TCG_REG_R8, | |
160 | TCG_REG_R9, | |
161 | TCG_REG_R10, | |
162 | TCG_REG_R11 | |
163 | }; | |
164 | ||
165 | static const int tcg_target_call_iarg_regs[8] = { | |
166 | TCG_REG_R56, | |
167 | TCG_REG_R57, | |
168 | TCG_REG_R58, | |
169 | TCG_REG_R59, | |
170 | TCG_REG_R60, | |
171 | TCG_REG_R61, | |
172 | TCG_REG_R62, | |
173 | TCG_REG_R63, | |
174 | }; | |
175 | ||
af15a623 SW |
176 | static const int tcg_target_call_oarg_regs[] = { |
177 | TCG_REG_R8 | |
477ba620 AJ |
178 | }; |
179 | ||
477ba620 AJ |
180 | /* |
181 | * opcode formation | |
182 | */ | |
183 | ||
184 | /* bundle templates: stops (double bar in the IA64 manual) are marked with | |
185 | an uppercase letter. */ | |
186 | enum { | |
187 | mii = 0x00, | |
188 | miI = 0x01, | |
189 | mIi = 0x02, | |
190 | mII = 0x03, | |
191 | mlx = 0x04, | |
192 | mLX = 0x05, | |
193 | mmi = 0x08, | |
194 | mmI = 0x09, | |
195 | Mmi = 0x0a, | |
196 | MmI = 0x0b, | |
197 | mfi = 0x0c, | |
198 | mfI = 0x0d, | |
199 | mmf = 0x0e, | |
200 | mmF = 0x0f, | |
201 | mib = 0x10, | |
202 | miB = 0x11, | |
203 | mbb = 0x12, | |
204 | mbB = 0x13, | |
205 | bbb = 0x16, | |
206 | bbB = 0x17, | |
207 | mmb = 0x18, | |
208 | mmB = 0x19, | |
209 | mfb = 0x1c, | |
210 | mfB = 0x1d, | |
211 | }; | |
212 | ||
213 | enum { | |
214 | OPC_ADD_A1 = 0x10000000000ull, | |
215 | OPC_AND_A1 = 0x10060000000ull, | |
216 | OPC_AND_A3 = 0x10160000000ull, | |
217 | OPC_ANDCM_A1 = 0x10068000000ull, | |
218 | OPC_ANDCM_A3 = 0x10168000000ull, | |
219 | OPC_ADDS_A4 = 0x10800000000ull, | |
220 | OPC_ADDL_A5 = 0x12000000000ull, | |
221 | OPC_ALLOC_M34 = 0x02c00000000ull, | |
222 | OPC_BR_DPTK_FEW_B1 = 0x08400000000ull, | |
223 | OPC_BR_SPTK_MANY_B1 = 0x08000001000ull, | |
224 | OPC_BR_SPTK_MANY_B4 = 0x00100001000ull, | |
225 | OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull, | |
226 | OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull, | |
227 | OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull, | |
6f65c780 | 228 | OPC_BRL_CALL_SPTK_MANY_X4 = 0x1a000001000ull, |
477ba620 AJ |
229 | OPC_CMP_LT_A6 = 0x18000000000ull, |
230 | OPC_CMP_LTU_A6 = 0x1a000000000ull, | |
231 | OPC_CMP_EQ_A6 = 0x1c000000000ull, | |
232 | OPC_CMP4_LT_A6 = 0x18400000000ull, | |
233 | OPC_CMP4_LTU_A6 = 0x1a400000000ull, | |
234 | OPC_CMP4_EQ_A6 = 0x1c400000000ull, | |
63975ea7 | 235 | OPC_DEP_I14 = 0x0ae00000000ull, |
c7d4475a | 236 | OPC_DEP_I15 = 0x08000000000ull, |
477ba620 AJ |
237 | OPC_DEP_Z_I12 = 0x0a600000000ull, |
238 | OPC_EXTR_I11 = 0x0a400002000ull, | |
239 | OPC_EXTR_U_I11 = 0x0a400000000ull, | |
240 | OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull, | |
241 | OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull, | |
242 | OPC_FCVT_XF_F11 = 0x000e0000000ull, | |
243 | OPC_FMA_S1_F1 = 0x10400000000ull, | |
244 | OPC_FNMA_S1_F1 = 0x18400000000ull, | |
245 | OPC_FRCPA_S1_F6 = 0x00600000000ull, | |
246 | OPC_GETF_SIG_M19 = 0x08708000000ull, | |
247 | OPC_LD1_M1 = 0x08000000000ull, | |
248 | OPC_LD1_M3 = 0x0a000000000ull, | |
249 | OPC_LD2_M1 = 0x08040000000ull, | |
250 | OPC_LD2_M3 = 0x0a040000000ull, | |
251 | OPC_LD4_M1 = 0x08080000000ull, | |
252 | OPC_LD4_M3 = 0x0a080000000ull, | |
253 | OPC_LD8_M1 = 0x080c0000000ull, | |
254 | OPC_LD8_M3 = 0x0a0c0000000ull, | |
255 | OPC_MUX1_I3 = 0x0eca0000000ull, | |
256 | OPC_NOP_B9 = 0x04008000000ull, | |
257 | OPC_NOP_F16 = 0x00008000000ull, | |
258 | OPC_NOP_I18 = 0x00008000000ull, | |
259 | OPC_NOP_M48 = 0x00008000000ull, | |
260 | OPC_MOV_I21 = 0x00e00100000ull, | |
261 | OPC_MOV_RET_I21 = 0x00e00500000ull, | |
262 | OPC_MOV_I22 = 0x00188000000ull, | |
263 | OPC_MOV_I_I26 = 0x00150000000ull, | |
264 | OPC_MOVL_X2 = 0x0c000000000ull, | |
265 | OPC_OR_A1 = 0x10070000000ull, | |
266 | OPC_SETF_EXP_M18 = 0x0c748000000ull, | |
267 | OPC_SETF_SIG_M18 = 0x0c708000000ull, | |
268 | OPC_SHL_I7 = 0x0f240000000ull, | |
269 | OPC_SHR_I5 = 0x0f220000000ull, | |
270 | OPC_SHR_U_I5 = 0x0f200000000ull, | |
271 | OPC_SHRP_I10 = 0x0ac00000000ull, | |
272 | OPC_SXT1_I29 = 0x000a0000000ull, | |
273 | OPC_SXT2_I29 = 0x000a8000000ull, | |
274 | OPC_SXT4_I29 = 0x000b0000000ull, | |
275 | OPC_ST1_M4 = 0x08c00000000ull, | |
276 | OPC_ST2_M4 = 0x08c40000000ull, | |
277 | OPC_ST4_M4 = 0x08c80000000ull, | |
278 | OPC_ST8_M4 = 0x08cc0000000ull, | |
279 | OPC_SUB_A1 = 0x10028000000ull, | |
280 | OPC_SUB_A3 = 0x10128000000ull, | |
281 | OPC_UNPACK4_L_I2 = 0x0f860000000ull, | |
282 | OPC_XMA_L_F2 = 0x1d000000000ull, | |
283 | OPC_XOR_A1 = 0x10078000000ull, | |
284 | OPC_ZXT1_I29 = 0x00080000000ull, | |
285 | OPC_ZXT2_I29 = 0x00088000000ull, | |
286 | OPC_ZXT4_I29 = 0x00090000000ull, | |
5f7b1687 RH |
287 | |
288 | INSN_NOP_M = OPC_NOP_M48, /* nop.m 0 */ | |
289 | INSN_NOP_I = OPC_NOP_I18, /* nop.i 0 */ | |
477ba620 AJ |
290 | }; |
291 | ||
292 | static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1, | |
293 | int r2, int r3) | |
294 | { | |
295 | return opc | |
296 | | ((r3 & 0x7f) << 20) | |
297 | | ((r2 & 0x7f) << 13) | |
298 | | ((r1 & 0x7f) << 6) | |
299 | | (qp & 0x3f); | |
300 | } | |
301 | ||
302 | static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1, | |
303 | uint64_t imm, int r3) | |
304 | { | |
305 | return opc | |
306 | | ((imm & 0x80) << 29) /* s */ | |
307 | | ((imm & 0x7f) << 13) /* imm7b */ | |
308 | | ((r3 & 0x7f) << 20) | |
309 | | ((r1 & 0x7f) << 6) | |
310 | | (qp & 0x3f); | |
311 | } | |
312 | ||
313 | static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1, | |
314 | uint64_t imm, int r3) | |
315 | { | |
316 | return opc | |
317 | | ((imm & 0x2000) << 23) /* s */ | |
318 | | ((imm & 0x1f80) << 20) /* imm6d */ | |
319 | | ((imm & 0x007f) << 13) /* imm7b */ | |
320 | | ((r3 & 0x7f) << 20) | |
321 | | ((r1 & 0x7f) << 6) | |
322 | | (qp & 0x3f); | |
323 | } | |
324 | ||
325 | static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1, | |
326 | uint64_t imm, int r3) | |
327 | { | |
328 | return opc | |
329 | | ((imm & 0x200000) << 15) /* s */ | |
330 | | ((imm & 0x1f0000) << 6) /* imm5c */ | |
331 | | ((imm & 0x00ff80) << 20) /* imm9d */ | |
332 | | ((imm & 0x00007f) << 13) /* imm7b */ | |
333 | | ((r3 & 0x03) << 20) | |
334 | | ((r1 & 0x7f) << 6) | |
335 | | (qp & 0x3f); | |
336 | } | |
337 | ||
338 | static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1, | |
339 | int p2, int r2, int r3) | |
340 | { | |
341 | return opc | |
342 | | ((p2 & 0x3f) << 27) | |
343 | | ((r3 & 0x7f) << 20) | |
344 | | ((r2 & 0x7f) << 13) | |
345 | | ((p1 & 0x3f) << 6) | |
346 | | (qp & 0x3f); | |
347 | } | |
348 | ||
349 | static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm) | |
350 | { | |
351 | return opc | |
352 | | ((imm & 0x100000) << 16) /* s */ | |
353 | | ((imm & 0x0fffff) << 13) /* imm20b */ | |
354 | | (qp & 0x3f); | |
355 | } | |
356 | ||
357 | static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2) | |
358 | { | |
359 | return opc | |
360 | | ((b2 & 0x7) << 13) | |
361 | | (qp & 0x3f); | |
362 | } | |
363 | ||
364 | static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2) | |
365 | { | |
366 | return opc | |
367 | | ((b2 & 0x7) << 13) | |
368 | | ((b1 & 0x7) << 6) | |
369 | | (qp & 0x3f); | |
370 | } | |
371 | ||
372 | ||
373 | static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm) | |
374 | { | |
375 | return opc | |
376 | | ((imm & 0x100000) << 16) /* i */ | |
377 | | ((imm & 0x0fffff) << 6) /* imm20a */ | |
378 | | (qp & 0x3f); | |
379 | } | |
380 | ||
381 | static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1, | |
382 | int f3, int f4, int f2) | |
383 | { | |
384 | return opc | |
385 | | ((f4 & 0x7f) << 27) | |
386 | | ((f3 & 0x7f) << 20) | |
387 | | ((f2 & 0x7f) << 13) | |
388 | | ((f1 & 0x7f) << 6) | |
389 | | (qp & 0x3f); | |
390 | } | |
391 | ||
392 | static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1, | |
393 | int f3, int f4, int f2) | |
394 | { | |
395 | return opc | |
396 | | ((f4 & 0x7f) << 27) | |
397 | | ((f3 & 0x7f) << 20) | |
398 | | ((f2 & 0x7f) << 13) | |
399 | | ((f1 & 0x7f) << 6) | |
400 | | (qp & 0x3f); | |
401 | } | |
402 | ||
403 | static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1, | |
404 | int p2, int f2, int f3) | |
405 | { | |
406 | return opc | |
407 | | ((p2 & 0x3f) << 27) | |
408 | | ((f3 & 0x7f) << 20) | |
409 | | ((f2 & 0x7f) << 13) | |
410 | | ((f1 & 0x7f) << 6) | |
411 | | (qp & 0x3f); | |
412 | } | |
413 | ||
414 | static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2) | |
415 | { | |
416 | return opc | |
417 | | ((f2 & 0x7f) << 13) | |
418 | | ((f1 & 0x7f) << 6) | |
419 | | (qp & 0x3f); | |
420 | } | |
421 | ||
422 | static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2) | |
423 | { | |
424 | return opc | |
425 | | ((f2 & 0x7f) << 13) | |
426 | | ((f1 & 0x7f) << 6) | |
427 | | (qp & 0x3f); | |
428 | } | |
429 | ||
430 | static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm) | |
431 | { | |
432 | return opc | |
433 | | ((imm & 0x100000) << 16) /* i */ | |
434 | | ((imm & 0x0fffff) << 6) /* imm20a */ | |
435 | | (qp & 0x3f); | |
436 | } | |
437 | ||
438 | static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1, | |
439 | int r2, int r3) | |
440 | { | |
441 | return opc | |
442 | | ((r3 & 0x7f) << 20) | |
443 | | ((r2 & 0x7f) << 13) | |
444 | | ((r1 & 0x7f) << 6) | |
445 | | (qp & 0x3f); | |
446 | } | |
447 | ||
448 | static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1, | |
449 | int r2, int mbtype) | |
450 | { | |
451 | return opc | |
452 | | ((mbtype & 0x0f) << 20) | |
453 | | ((r2 & 0x7f) << 13) | |
454 | | ((r1 & 0x7f) << 6) | |
455 | | (qp & 0x3f); | |
456 | } | |
457 | ||
458 | static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1, | |
459 | int r3, int r2) | |
460 | { | |
461 | return opc | |
462 | | ((r3 & 0x7f) << 20) | |
463 | | ((r2 & 0x7f) << 13) | |
464 | | ((r1 & 0x7f) << 6) | |
465 | | (qp & 0x3f); | |
466 | } | |
467 | ||
468 | static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1, | |
469 | int r2, int r3) | |
470 | { | |
471 | return opc | |
472 | | ((r3 & 0x7f) << 20) | |
473 | | ((r2 & 0x7f) << 13) | |
474 | | ((r1 & 0x7f) << 6) | |
475 | | (qp & 0x3f); | |
476 | } | |
477 | ||
478 | static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1, | |
479 | int r2, int r3, uint64_t count) | |
480 | { | |
481 | return opc | |
482 | | ((count & 0x3f) << 27) | |
483 | | ((r3 & 0x7f) << 20) | |
484 | | ((r2 & 0x7f) << 13) | |
485 | | ((r1 & 0x7f) << 6) | |
486 | | (qp & 0x3f); | |
487 | } | |
488 | ||
489 | static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1, | |
490 | int r3, uint64_t pos, uint64_t len) | |
491 | { | |
492 | return opc | |
493 | | ((len & 0x3f) << 27) | |
494 | | ((r3 & 0x7f) << 20) | |
495 | | ((pos & 0x3f) << 14) | |
496 | | ((r1 & 0x7f) << 6) | |
497 | | (qp & 0x3f); | |
498 | } | |
499 | ||
500 | static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1, | |
501 | int r2, uint64_t pos, uint64_t len) | |
502 | { | |
503 | return opc | |
504 | | ((len & 0x3f) << 27) | |
505 | | ((pos & 0x3f) << 20) | |
506 | | ((r2 & 0x7f) << 13) | |
507 | | ((r1 & 0x7f) << 6) | |
508 | | (qp & 0x3f); | |
509 | } | |
510 | ||
63975ea7 AJ |
511 | static inline uint64_t tcg_opc_i14(int qp, uint64_t opc, int r1, uint64_t imm, |
512 | int r3, uint64_t pos, uint64_t len) | |
513 | { | |
514 | return opc | |
515 | | ((imm & 0x01) << 36) | |
516 | | ((len & 0x3f) << 27) | |
517 | | ((r3 & 0x7f) << 20) | |
518 | | ((pos & 0x3f) << 14) | |
519 | | ((r1 & 0x7f) << 6) | |
520 | | (qp & 0x3f); | |
521 | } | |
522 | ||
c7d4475a RH |
523 | static inline uint64_t tcg_opc_i15(int qp, uint64_t opc, int r1, int r2, |
524 | int r3, uint64_t pos, uint64_t len) | |
525 | { | |
526 | return opc | |
527 | | ((pos & 0x3f) << 31) | |
528 | | ((len & 0x0f) << 27) | |
529 | | ((r3 & 0x7f) << 20) | |
530 | | ((r2 & 0x7f) << 13) | |
531 | | ((r1 & 0x7f) << 6) | |
532 | | (qp & 0x3f); | |
533 | } | |
534 | ||
477ba620 AJ |
535 | static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm) |
536 | { | |
537 | return opc | |
538 | | ((imm & 0x100000) << 16) /* i */ | |
539 | | ((imm & 0x0fffff) << 6) /* imm20a */ | |
540 | | (qp & 0x3f); | |
541 | } | |
542 | ||
543 | static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1, | |
544 | int r2, uint64_t imm) | |
545 | { | |
546 | return opc | |
547 | | ((imm & 0x1ff) << 24) | |
548 | | ((r2 & 0x7f) << 13) | |
549 | | ((b1 & 0x7) << 6) | |
550 | | (qp & 0x3f); | |
551 | } | |
552 | ||
553 | static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2) | |
554 | { | |
555 | return opc | |
556 | | ((b2 & 0x7) << 13) | |
557 | | ((r1 & 0x7f) << 6) | |
558 | | (qp & 0x3f); | |
559 | } | |
560 | ||
561 | static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2) | |
562 | { | |
563 | return opc | |
564 | | ((ar3 & 0x7f) << 20) | |
565 | | ((r2 & 0x7f) << 13) | |
566 | | (qp & 0x3f); | |
567 | } | |
568 | ||
569 | static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3) | |
570 | { | |
571 | return opc | |
572 | | ((r3 & 0x7f) << 20) | |
573 | | ((r1 & 0x7f) << 6) | |
574 | | (qp & 0x3f); | |
575 | } | |
576 | ||
577 | static inline uint64_t tcg_opc_l2(uint64_t imm) | |
578 | { | |
579 | return (imm & 0x7fffffffffc00000ull) >> 22; | |
580 | } | |
581 | ||
582 | static inline uint64_t tcg_opc_l3(uint64_t imm) | |
583 | { | |
584 | return (imm & 0x07fffffffff00000ull) >> 18; | |
585 | } | |
586 | ||
6f65c780 RH |
587 | #define tcg_opc_l4 tcg_opc_l3 |
588 | ||
477ba620 AJ |
589 | static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3) |
590 | { | |
591 | return opc | |
592 | | ((r3 & 0x7f) << 20) | |
593 | | ((r1 & 0x7f) << 6) | |
594 | | (qp & 0x3f); | |
595 | } | |
596 | ||
597 | static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1, | |
598 | int r3, uint64_t imm) | |
599 | { | |
600 | return opc | |
601 | | ((imm & 0x100) << 28) /* s */ | |
602 | | ((imm & 0x080) << 20) /* i */ | |
603 | | ((imm & 0x07f) << 13) /* imm7b */ | |
604 | | ((r3 & 0x7f) << 20) | |
605 | | ((r1 & 0x7f) << 6) | |
606 | | (qp & 0x3f); | |
607 | } | |
608 | ||
609 | static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3) | |
610 | { | |
611 | return opc | |
612 | | ((r3 & 0x7f) << 20) | |
613 | | ((r2 & 0x7f) << 13) | |
614 | | (qp & 0x3f); | |
615 | } | |
616 | ||
617 | static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2) | |
618 | { | |
619 | return opc | |
620 | | ((r2 & 0x7f) << 13) | |
621 | | ((f1 & 0x7f) << 6) | |
622 | | (qp & 0x3f); | |
623 | } | |
624 | ||
625 | static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2) | |
626 | { | |
627 | return opc | |
628 | | ((f2 & 0x7f) << 13) | |
629 | | ((r1 & 0x7f) << 6) | |
630 | | (qp & 0x3f); | |
631 | } | |
632 | ||
633 | static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1, | |
634 | int sof, int sol, int sor) | |
635 | { | |
636 | return opc | |
637 | | ((sor & 0x0f) << 27) | |
638 | | ((sol & 0x7f) << 20) | |
639 | | ((sof & 0x7f) << 13) | |
640 | | ((r1 & 0x7f) << 6) | |
641 | | (qp & 0x3f); | |
642 | } | |
643 | ||
644 | static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm) | |
645 | { | |
646 | return opc | |
647 | | ((imm & 0x100000) << 16) /* i */ | |
648 | | ((imm & 0x0fffff) << 6) /* imm20a */ | |
649 | | (qp & 0x3f); | |
650 | } | |
651 | ||
652 | static inline uint64_t tcg_opc_x2(int qp, uint64_t opc, | |
653 | int r1, uint64_t imm) | |
654 | { | |
655 | return opc | |
656 | | ((imm & 0x8000000000000000ull) >> 27) /* i */ | |
657 | | (imm & 0x0000000000200000ull) /* ic */ | |
658 | | ((imm & 0x00000000001f0000ull) << 6) /* imm5c */ | |
659 | | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */ | |
660 | | ((imm & 0x000000000000007full) << 13) /* imm7b */ | |
661 | | ((r1 & 0x7f) << 6) | |
662 | | (qp & 0x3f); | |
663 | } | |
664 | ||
665 | static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm) | |
666 | { | |
667 | return opc | |
668 | | ((imm & 0x0800000000000000ull) >> 23) /* i */ | |
669 | | ((imm & 0x00000000000fffffull) << 13) /* imm20b */ | |
670 | | (qp & 0x3f); | |
671 | } | |
672 | ||
6f65c780 RH |
673 | static inline uint64_t tcg_opc_x4(int qp, uint64_t opc, int b1, uint64_t imm) |
674 | { | |
675 | return opc | |
676 | | ((imm & 0x0800000000000000ull) >> 23) /* i */ | |
677 | | ((imm & 0x00000000000fffffull) << 13) /* imm20b */ | |
678 | | ((b1 & 0x7) << 6) | |
679 | | (qp & 0x3f); | |
680 | } | |
681 | ||
477ba620 AJ |
682 | |
683 | /* | |
684 | * Relocations | |
685 | */ | |
686 | ||
2ba7fae2 | 687 | static inline void reloc_pcrel21b(void *pc, intptr_t target) |
477ba620 AJ |
688 | { |
689 | uint64_t imm; | |
690 | int64_t disp; | |
691 | int slot; | |
692 | ||
2ba7fae2 RH |
693 | slot = (intptr_t)pc & 3; |
694 | pc = (void *)((intptr_t)pc & ~3); | |
477ba620 | 695 | |
2ba7fae2 | 696 | disp = target - (intptr_t)pc; |
477ba620 AJ |
697 | imm = (uint64_t) disp >> 4; |
698 | ||
699 | switch(slot) { | |
700 | case 0: | |
701 | *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull) | |
702 | | ((imm & 0x100000) << 21) /* s */ | |
703 | | ((imm & 0x0fffff) << 18); /* imm20b */ | |
704 | break; | |
705 | case 1: | |
706 | *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull) | |
707 | | ((imm & 0x100000) >> 2) /* s */ | |
708 | | ((imm & 0x0fffe0) >> 5); /* imm20b */ | |
709 | *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull) | |
710 | | ((imm & 0x00001f) << 59); /* imm20b */ | |
711 | break; | |
712 | case 2: | |
713 | *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull) | |
714 | | ((imm & 0x100000) << 39) /* s */ | |
715 | | ((imm & 0x0fffff) << 36); /* imm20b */ | |
716 | break; | |
717 | } | |
718 | } | |
719 | ||
720 | static inline uint64_t get_reloc_pcrel21b (void *pc) | |
721 | { | |
722 | int64_t low, high; | |
723 | int slot; | |
724 | ||
725 | slot = (tcg_target_long) pc & 3; | |
726 | pc = (void *)((tcg_target_long) pc & ~3); | |
727 | ||
728 | low = (*(uint64_t *)(pc + 0)); | |
729 | high = (*(uint64_t *)(pc + 8)); | |
730 | ||
731 | switch(slot) { | |
732 | case 0: | |
733 | return ((low >> 21) & 0x100000) + /* s */ | |
734 | ((low >> 18) & 0x0fffff); /* imm20b */ | |
735 | case 1: | |
736 | return ((high << 2) & 0x100000) + /* s */ | |
737 | ((high << 5) & 0x0fffe0) + /* imm20b */ | |
738 | ((low >> 59) & 0x00001f); /* imm20b */ | |
739 | case 2: | |
740 | return ((high >> 39) & 0x100000) + /* s */ | |
741 | ((high >> 36) & 0x0fffff); /* imm20b */ | |
742 | default: | |
743 | tcg_abort(); | |
744 | } | |
745 | } | |
746 | ||
2ba7fae2 | 747 | static inline void reloc_pcrel60b(void *pc, intptr_t target) |
477ba620 AJ |
748 | { |
749 | int64_t disp; | |
750 | uint64_t imm; | |
751 | ||
2ba7fae2 | 752 | disp = target - (intptr_t)pc; |
477ba620 AJ |
753 | imm = (uint64_t) disp >> 4; |
754 | ||
755 | *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull) | |
756 | | (imm & 0x0800000000000000ull) /* s */ | |
757 | | ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */ | |
758 | | ((imm & 0x00000000000fffffull) << 36); /* imm20b */ | |
759 | *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull) | |
760 | | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */ | |
761 | } | |
762 | ||
763 | static inline uint64_t get_reloc_pcrel60b (void *pc) | |
764 | { | |
765 | int64_t low, high; | |
766 | ||
767 | low = (*(uint64_t *)(pc + 0)); | |
768 | high = (*(uint64_t *)(pc + 8)); | |
769 | ||
770 | return ((high) & 0x0800000000000000ull) + /* s */ | |
771 | ((high >> 36) & 0x00000000000fffffull) + /* imm20b */ | |
772 | ((high << 36) & 0x07fffff000000000ull) + /* imm39 */ | |
773 | ((low >> 28) & 0x0000000ffff00000ull); /* imm39 */ | |
774 | } | |
775 | ||
776 | ||
777 | static void patch_reloc(uint8_t *code_ptr, int type, | |
2ba7fae2 | 778 | intptr_t value, intptr_t addend) |
477ba620 AJ |
779 | { |
780 | value += addend; | |
781 | switch (type) { | |
782 | case R_IA64_PCREL21B: | |
783 | reloc_pcrel21b(code_ptr, value); | |
784 | break; | |
785 | case R_IA64_PCREL60B: | |
786 | reloc_pcrel60b(code_ptr, value); | |
787 | default: | |
788 | tcg_abort(); | |
789 | } | |
790 | } | |
791 | ||
792 | /* | |
793 | * Constraints | |
794 | */ | |
795 | ||
796 | /* parse target specific constraints */ | |
797 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) | |
798 | { | |
799 | const char *ct_str; | |
800 | ||
801 | ct_str = *pct_str; | |
802 | switch(ct_str[0]) { | |
803 | case 'r': | |
804 | ct->ct |= TCG_CT_REG; | |
805 | tcg_regset_set(ct->u.regs, 0xffffffffffffffffull); | |
806 | break; | |
807 | case 'I': | |
808 | ct->ct |= TCG_CT_CONST_S22; | |
809 | break; | |
810 | case 'S': | |
811 | ct->ct |= TCG_CT_REG; | |
812 | tcg_regset_set(ct->u.regs, 0xffffffffffffffffull); | |
813 | #if defined(CONFIG_SOFTMMU) | |
814 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56); | |
815 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57); | |
816 | #endif | |
817 | break; | |
818 | case 'Z': | |
819 | /* We are cheating a bit here, using the fact that the register | |
820 | r0 is also the register number 0. Hence there is no need | |
821 | to check for const_args in each instruction. */ | |
822 | ct->ct |= TCG_CT_CONST_ZERO; | |
823 | break; | |
824 | default: | |
825 | return -1; | |
826 | } | |
827 | ct_str++; | |
828 | *pct_str = ct_str; | |
829 | return 0; | |
830 | } | |
831 | ||
832 | /* test if a constant matches the constraint */ | |
833 | static inline int tcg_target_const_match(tcg_target_long val, | |
834 | const TCGArgConstraint *arg_ct) | |
835 | { | |
836 | int ct; | |
837 | ct = arg_ct->ct; | |
838 | if (ct & TCG_CT_CONST) | |
839 | return 1; | |
840 | else if ((ct & TCG_CT_CONST_ZERO) && val == 0) | |
841 | return 1; | |
842 | else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10) | |
843 | return 1; | |
844 | else | |
845 | return 0; | |
846 | } | |
847 | ||
848 | /* | |
849 | * Code generation | |
850 | */ | |
851 | ||
852 | static uint8_t *tb_ret_addr; | |
853 | ||
854 | static inline void tcg_out_bundle(TCGContext *s, int template, | |
855 | uint64_t slot0, uint64_t slot1, | |
856 | uint64_t slot2) | |
857 | { | |
858 | template &= 0x1f; /* 5 bits */ | |
859 | slot0 &= 0x1ffffffffffull; /* 41 bits */ | |
860 | slot1 &= 0x1ffffffffffull; /* 41 bits */ | |
861 | slot2 &= 0x1ffffffffffull; /* 41 bits */ | |
862 | ||
863 | *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template; | |
864 | *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18); | |
865 | s->code_ptr += 16; | |
866 | } | |
867 | ||
3b6dac34 | 868 | static inline void tcg_out_mov(TCGContext *s, TCGType type, |
2a534aff | 869 | TCGReg ret, TCGReg arg) |
477ba620 AJ |
870 | { |
871 | tcg_out_bundle(s, mmI, | |
5f7b1687 RH |
872 | INSN_NOP_M, |
873 | INSN_NOP_M, | |
477ba620 AJ |
874 | tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg)); |
875 | } | |
876 | ||
877 | static inline void tcg_out_movi(TCGContext *s, TCGType type, | |
2a534aff | 878 | TCGReg reg, tcg_target_long arg) |
477ba620 AJ |
879 | { |
880 | tcg_out_bundle(s, mLX, | |
5f7b1687 | 881 | INSN_NOP_M, |
477ba620 AJ |
882 | tcg_opc_l2 (arg), |
883 | tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg)); | |
884 | } | |
885 | ||
477ba620 AJ |
886 | static void tcg_out_br(TCGContext *s, int label_index) |
887 | { | |
888 | TCGLabel *l = &s->labels[label_index]; | |
889 | ||
56779034 AJ |
890 | /* We pay attention here to not modify the branch target by reading |
891 | the existing value and using it again. This ensure that caches and | |
892 | memory are kept coherent during retranslation. */ | |
477ba620 | 893 | tcg_out_bundle(s, mmB, |
5f7b1687 RH |
894 | INSN_NOP_M, |
895 | INSN_NOP_M, | |
477ba620 AJ |
896 | tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1, |
897 | get_reloc_pcrel21b(s->code_ptr + 2))); | |
898 | ||
899 | if (l->has_value) { | |
900 | reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value); | |
901 | } else { | |
902 | tcg_out_reloc(s, (s->code_ptr - 16) + 2, | |
903 | R_IA64_PCREL21B, label_index, 0); | |
904 | } | |
905 | } | |
906 | ||
6f65c780 RH |
907 | static inline void tcg_out_calli(TCGContext *s, uintptr_t addr) |
908 | { | |
909 | /* Look through the function descriptor. */ | |
910 | uintptr_t disp, *desc = (uintptr_t *)addr; | |
911 | tcg_out_bundle(s, mlx, | |
912 | INSN_NOP_M, | |
913 | tcg_opc_l2 (desc[1]), | |
914 | tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, TCG_REG_R1, desc[1])); | |
915 | disp = (desc[0] - (uintptr_t)s->code_ptr) >> 4; | |
916 | tcg_out_bundle(s, mLX, | |
917 | INSN_NOP_M, | |
918 | tcg_opc_l4 (disp), | |
919 | tcg_opc_x4 (TCG_REG_P0, OPC_BRL_CALL_SPTK_MANY_X4, | |
920 | TCG_REG_B0, disp)); | |
921 | } | |
922 | ||
923 | static inline void tcg_out_callr(TCGContext *s, TCGReg addr) | |
477ba620 AJ |
924 | { |
925 | tcg_out_bundle(s, MmI, | |
926 | tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr), | |
927 | tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr), | |
928 | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, | |
929 | TCG_REG_B6, TCG_REG_R2, 0)); | |
930 | tcg_out_bundle(s, mmB, | |
931 | tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3), | |
5f7b1687 | 932 | INSN_NOP_M, |
477ba620 AJ |
933 | tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5, |
934 | TCG_REG_B0, TCG_REG_B6)); | |
935 | } | |
936 | ||
937 | static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg) | |
938 | { | |
939 | int64_t disp; | |
940 | uint64_t imm; | |
941 | ||
942 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg); | |
943 | ||
944 | disp = tb_ret_addr - s->code_ptr; | |
945 | imm = (uint64_t)disp >> 4; | |
946 | ||
947 | tcg_out_bundle(s, mLX, | |
5f7b1687 | 948 | INSN_NOP_M, |
477ba620 AJ |
949 | tcg_opc_l3 (imm), |
950 | tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm)); | |
951 | } | |
952 | ||
953 | static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg) | |
954 | { | |
955 | if (s->tb_jmp_offset) { | |
956 | /* direct jump method */ | |
957 | tcg_abort(); | |
958 | } else { | |
959 | /* indirect jump method */ | |
960 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, | |
961 | (tcg_target_long)(s->tb_next + arg)); | |
962 | tcg_out_bundle(s, MmI, | |
963 | tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, | |
964 | TCG_REG_R2, TCG_REG_R2), | |
5f7b1687 | 965 | INSN_NOP_M, |
477ba620 AJ |
966 | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, |
967 | TCG_REG_R2, 0)); | |
968 | tcg_out_bundle(s, mmB, | |
5f7b1687 RH |
969 | INSN_NOP_M, |
970 | INSN_NOP_M, | |
477ba620 AJ |
971 | tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, |
972 | TCG_REG_B6)); | |
973 | } | |
974 | s->tb_next_offset[arg] = s->code_ptr - s->code_buf; | |
975 | } | |
976 | ||
977 | static inline void tcg_out_jmp(TCGContext *s, TCGArg addr) | |
978 | { | |
979 | tcg_out_bundle(s, mmI, | |
5f7b1687 RH |
980 | INSN_NOP_M, |
981 | INSN_NOP_M, | |
477ba620 AJ |
982 | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0)); |
983 | tcg_out_bundle(s, mmB, | |
5f7b1687 RH |
984 | INSN_NOP_M, |
985 | INSN_NOP_M, | |
477ba620 AJ |
986 | tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6)); |
987 | } | |
988 | ||
989 | static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg, | |
990 | TCGArg arg1, tcg_target_long arg2) | |
991 | { | |
992 | if (arg2 == ((int16_t)arg2 >> 2) << 2) { | |
993 | tcg_out_bundle(s, MmI, | |
994 | tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, | |
995 | TCG_REG_R2, arg2, arg1), | |
996 | tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), | |
5f7b1687 | 997 | INSN_NOP_I); |
477ba620 AJ |
998 | } else { |
999 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2); | |
1000 | tcg_out_bundle(s, MmI, | |
1001 | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, | |
1002 | TCG_REG_R2, TCG_REG_R2, arg1), | |
1003 | tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), | |
5f7b1687 | 1004 | INSN_NOP_I); |
477ba620 AJ |
1005 | } |
1006 | } | |
1007 | ||
1008 | static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg, | |
1009 | TCGArg arg1, tcg_target_long arg2) | |
1010 | { | |
1011 | if (arg2 == ((int16_t)arg2 >> 2) << 2) { | |
1012 | tcg_out_bundle(s, MmI, | |
1013 | tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, | |
1014 | TCG_REG_R2, arg2, arg1), | |
1015 | tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), | |
5f7b1687 | 1016 | INSN_NOP_I); |
477ba620 AJ |
1017 | } else { |
1018 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2); | |
1019 | tcg_out_bundle(s, MmI, | |
1020 | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, | |
1021 | TCG_REG_R2, TCG_REG_R2, arg1), | |
1022 | tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), | |
5f7b1687 | 1023 | INSN_NOP_I); |
477ba620 AJ |
1024 | } |
1025 | } | |
1026 | ||
2a534aff | 1027 | static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, |
a05b5b9b | 1028 | TCGReg arg1, intptr_t arg2) |
477ba620 AJ |
1029 | { |
1030 | if (type == TCG_TYPE_I32) { | |
1031 | tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2); | |
1032 | } else { | |
1033 | tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2); | |
1034 | } | |
1035 | } | |
1036 | ||
2a534aff | 1037 | static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, |
a05b5b9b | 1038 | TCGReg arg1, intptr_t arg2) |
477ba620 AJ |
1039 | { |
1040 | if (type == TCG_TYPE_I32) { | |
1041 | tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2); | |
1042 | } else { | |
1043 | tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2); | |
1044 | } | |
1045 | } | |
1046 | ||
3c289cba RH |
1047 | static void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGReg ret, TCGArg arg1, |
1048 | int const_arg1, TCGArg arg2, int const_arg2) | |
477ba620 | 1049 | { |
3c289cba | 1050 | uint64_t opc1 = 0, opc2 = 0; |
477ba620 AJ |
1051 | |
1052 | if (const_arg1 && arg1 != 0) { | |
1053 | opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, | |
1054 | TCG_REG_R2, arg1, TCG_REG_R0); | |
1055 | arg1 = TCG_REG_R2; | |
477ba620 AJ |
1056 | } |
1057 | ||
1058 | if (const_arg2 && arg2 != 0) { | |
1059 | opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, | |
1060 | TCG_REG_R3, arg2, TCG_REG_R0); | |
1061 | arg2 = TCG_REG_R3; | |
477ba620 AJ |
1062 | } |
1063 | ||
3c289cba RH |
1064 | tcg_out_bundle(s, (opc1 || opc2 ? mII : miI), |
1065 | opc1 ? opc1 : INSN_NOP_M, | |
1066 | opc2 ? opc2 : INSN_NOP_I, | |
477ba620 AJ |
1067 | tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2)); |
1068 | } | |
1069 | ||
8642088a RH |
1070 | static inline void tcg_out_add(TCGContext *s, TCGReg ret, TCGReg arg1, |
1071 | TCGArg arg2, int const_arg2) | |
1072 | { | |
1073 | if (const_arg2 && arg2 == sextract64(arg2, 0, 14)) { | |
1074 | tcg_out_bundle(s, mmI, | |
1075 | INSN_NOP_M, | |
1076 | INSN_NOP_M, | |
1077 | tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, arg2, arg1)); | |
1078 | } else { | |
1079 | tcg_out_alu(s, OPC_ADD_A1, ret, arg1, 0, arg2, const_arg2); | |
1080 | } | |
1081 | } | |
1082 | ||
477ba620 AJ |
1083 | static inline void tcg_out_eqv(TCGContext *s, TCGArg ret, |
1084 | TCGArg arg1, int const_arg1, | |
1085 | TCGArg arg2, int const_arg2) | |
1086 | { | |
1087 | tcg_out_bundle(s, mII, | |
5f7b1687 | 1088 | INSN_NOP_M, |
477ba620 AJ |
1089 | tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2), |
1090 | tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret)); | |
1091 | } | |
1092 | ||
1093 | static inline void tcg_out_nand(TCGContext *s, TCGArg ret, | |
1094 | TCGArg arg1, int const_arg1, | |
1095 | TCGArg arg2, int const_arg2) | |
1096 | { | |
1097 | tcg_out_bundle(s, mII, | |
5f7b1687 | 1098 | INSN_NOP_M, |
477ba620 AJ |
1099 | tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2), |
1100 | tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret)); | |
1101 | } | |
1102 | ||
1103 | static inline void tcg_out_nor(TCGContext *s, TCGArg ret, | |
1104 | TCGArg arg1, int const_arg1, | |
1105 | TCGArg arg2, int const_arg2) | |
1106 | { | |
1107 | tcg_out_bundle(s, mII, | |
5f7b1687 | 1108 | INSN_NOP_M, |
477ba620 AJ |
1109 | tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2), |
1110 | tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret)); | |
1111 | } | |
1112 | ||
1113 | static inline void tcg_out_orc(TCGContext *s, TCGArg ret, | |
1114 | TCGArg arg1, int const_arg1, | |
1115 | TCGArg arg2, int const_arg2) | |
1116 | { | |
1117 | tcg_out_bundle(s, mII, | |
5f7b1687 | 1118 | INSN_NOP_M, |
477ba620 AJ |
1119 | tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2), |
1120 | tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2)); | |
1121 | } | |
1122 | ||
1123 | static inline void tcg_out_mul(TCGContext *s, TCGArg ret, | |
1124 | TCGArg arg1, TCGArg arg2) | |
1125 | { | |
1126 | tcg_out_bundle(s, mmI, | |
1127 | tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1), | |
1128 | tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2), | |
5f7b1687 | 1129 | INSN_NOP_I); |
477ba620 | 1130 | tcg_out_bundle(s, mmF, |
5f7b1687 RH |
1131 | INSN_NOP_M, |
1132 | INSN_NOP_M, | |
477ba620 AJ |
1133 | tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6, |
1134 | TCG_REG_F7, TCG_REG_F0)); | |
1135 | tcg_out_bundle(s, miI, | |
1136 | tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6), | |
5f7b1687 RH |
1137 | INSN_NOP_I, |
1138 | INSN_NOP_I); | |
477ba620 AJ |
1139 | } |
1140 | ||
1141 | static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1142 | TCGArg arg2, int const_arg2) | |
1143 | { | |
1144 | if (const_arg2) { | |
1145 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1146 | INSN_NOP_M, |
1147 | INSN_NOP_I, | |
477ba620 AJ |
1148 | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11, |
1149 | ret, arg1, arg2, 31 - arg2)); | |
1150 | } else { | |
1151 | tcg_out_bundle(s, mII, | |
1152 | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, | |
1153 | TCG_REG_R3, 0x1f, arg2), | |
1154 | tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1), | |
1155 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, | |
1156 | TCG_REG_R2, TCG_REG_R3)); | |
1157 | } | |
1158 | } | |
1159 | ||
1160 | static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1161 | TCGArg arg2, int const_arg2) | |
1162 | { | |
1163 | if (const_arg2) { | |
1164 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1165 | INSN_NOP_M, |
1166 | INSN_NOP_I, | |
477ba620 AJ |
1167 | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11, |
1168 | ret, arg1, arg2, 63 - arg2)); | |
1169 | } else { | |
1170 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1171 | INSN_NOP_M, |
1172 | INSN_NOP_I, | |
477ba620 AJ |
1173 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2)); |
1174 | } | |
1175 | } | |
1176 | ||
1177 | static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1178 | TCGArg arg2, int const_arg2) | |
1179 | { | |
1180 | if (const_arg2) { | |
1181 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1182 | INSN_NOP_M, |
1183 | INSN_NOP_I, | |
477ba620 AJ |
1184 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, |
1185 | arg1, 63 - arg2, 31 - arg2)); | |
1186 | } else { | |
1187 | tcg_out_bundle(s, mII, | |
5f7b1687 | 1188 | INSN_NOP_M, |
477ba620 AJ |
1189 | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2, |
1190 | 0x1f, arg2), | |
1191 | tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret, | |
1192 | arg1, TCG_REG_R2)); | |
1193 | } | |
1194 | } | |
1195 | ||
1196 | static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1197 | TCGArg arg2, int const_arg2) | |
1198 | { | |
1199 | if (const_arg2) { | |
1200 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1201 | INSN_NOP_M, |
1202 | INSN_NOP_I, | |
477ba620 AJ |
1203 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, |
1204 | arg1, 63 - arg2, 63 - arg2)); | |
1205 | } else { | |
1206 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1207 | INSN_NOP_M, |
1208 | INSN_NOP_I, | |
477ba620 AJ |
1209 | tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret, |
1210 | arg1, arg2)); | |
1211 | } | |
1212 | } | |
1213 | ||
1214 | static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1215 | TCGArg arg2, int const_arg2) | |
1216 | { | |
1217 | if (const_arg2) { | |
1218 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1219 | INSN_NOP_M, |
1220 | INSN_NOP_I, | |
477ba620 AJ |
1221 | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, |
1222 | arg1, arg2, 31 - arg2)); | |
1223 | } else { | |
1224 | tcg_out_bundle(s, mII, | |
1225 | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, | |
1226 | 0x1f, arg2), | |
1227 | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1), | |
1228 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, | |
1229 | TCG_REG_R2, TCG_REG_R3)); | |
1230 | } | |
1231 | } | |
1232 | ||
1233 | static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1234 | TCGArg arg2, int const_arg2) | |
1235 | { | |
1236 | if (const_arg2) { | |
1237 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1238 | INSN_NOP_M, |
1239 | INSN_NOP_I, | |
477ba620 AJ |
1240 | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, |
1241 | arg1, arg2, 63 - arg2)); | |
1242 | } else { | |
1243 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1244 | INSN_NOP_M, |
1245 | INSN_NOP_I, | |
477ba620 AJ |
1246 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, |
1247 | arg1, arg2)); | |
1248 | } | |
1249 | } | |
1250 | ||
1251 | static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1252 | TCGArg arg2, int const_arg2) | |
1253 | { | |
1254 | if (const_arg2) { | |
1255 | tcg_out_bundle(s, mII, | |
5f7b1687 | 1256 | INSN_NOP_M, |
477ba620 AJ |
1257 | tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
1258 | TCG_REG_R2, arg1, arg1), | |
1259 | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, | |
1260 | TCG_REG_R2, 32 - arg2, 31)); | |
1261 | } else { | |
1262 | tcg_out_bundle(s, miI, | |
5f7b1687 | 1263 | INSN_NOP_M, |
477ba620 AJ |
1264 | tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
1265 | TCG_REG_R2, arg1, arg1), | |
1266 | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, | |
1267 | 0x1f, arg2)); | |
1268 | tcg_out_bundle(s, mII, | |
5f7b1687 | 1269 | INSN_NOP_M, |
477ba620 AJ |
1270 | tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3, |
1271 | 0x20, TCG_REG_R3), | |
1272 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, | |
1273 | TCG_REG_R2, TCG_REG_R3)); | |
1274 | } | |
1275 | } | |
1276 | ||
1277 | static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1278 | TCGArg arg2, int const_arg2) | |
1279 | { | |
1280 | if (const_arg2) { | |
1281 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1282 | INSN_NOP_M, |
1283 | INSN_NOP_I, | |
477ba620 AJ |
1284 | tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1, |
1285 | arg1, 0x40 - arg2)); | |
1286 | } else { | |
1287 | tcg_out_bundle(s, mII, | |
1288 | tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2, | |
1289 | 0x40, arg2), | |
1290 | tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3, | |
1291 | arg1, arg2), | |
1292 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2, | |
1293 | arg1, TCG_REG_R2)); | |
1294 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1295 | INSN_NOP_M, |
1296 | INSN_NOP_I, | |
477ba620 AJ |
1297 | tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, |
1298 | TCG_REG_R2, TCG_REG_R3)); | |
1299 | } | |
1300 | } | |
1301 | ||
1302 | static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1303 | TCGArg arg2, int const_arg2) | |
1304 | { | |
1305 | if (const_arg2) { | |
1306 | tcg_out_bundle(s, mII, | |
5f7b1687 | 1307 | INSN_NOP_M, |
477ba620 AJ |
1308 | tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
1309 | TCG_REG_R2, arg1, arg1), | |
1310 | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, | |
1311 | TCG_REG_R2, arg2, 31)); | |
1312 | } else { | |
1313 | tcg_out_bundle(s, mII, | |
1314 | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, | |
1315 | 0x1f, arg2), | |
1316 | tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, | |
1317 | TCG_REG_R2, arg1, arg1), | |
1318 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, | |
1319 | TCG_REG_R2, TCG_REG_R3)); | |
1320 | } | |
1321 | } | |
1322 | ||
1323 | static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1324 | TCGArg arg2, int const_arg2) | |
1325 | { | |
1326 | if (const_arg2) { | |
1327 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1328 | INSN_NOP_M, |
1329 | INSN_NOP_I, | |
477ba620 AJ |
1330 | tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1, |
1331 | arg1, arg2)); | |
1332 | } else { | |
1333 | tcg_out_bundle(s, mII, | |
1334 | tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2, | |
1335 | 0x40, arg2), | |
1336 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3, | |
1337 | arg1, arg2), | |
1338 | tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2, | |
1339 | arg1, TCG_REG_R2)); | |
1340 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1341 | INSN_NOP_M, |
1342 | INSN_NOP_I, | |
477ba620 AJ |
1343 | tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, |
1344 | TCG_REG_R2, TCG_REG_R3)); | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29, | |
1349 | TCGArg ret, TCGArg arg) | |
1350 | { | |
1351 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1352 | INSN_NOP_M, |
1353 | INSN_NOP_I, | |
477ba620 AJ |
1354 | tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg)); |
1355 | } | |
1356 | ||
1357 | static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg) | |
1358 | { | |
1359 | tcg_out_bundle(s, mII, | |
5f7b1687 | 1360 | INSN_NOP_M, |
477ba620 AJ |
1361 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15), |
1362 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb)); | |
1363 | } | |
1364 | ||
1365 | static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg) | |
1366 | { | |
1367 | tcg_out_bundle(s, mII, | |
5f7b1687 | 1368 | INSN_NOP_M, |
477ba620 AJ |
1369 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31), |
1370 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb)); | |
1371 | } | |
1372 | ||
1373 | static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg) | |
1374 | { | |
a3e28aa5 | 1375 | tcg_out_bundle(s, miI, |
5f7b1687 RH |
1376 | INSN_NOP_M, |
1377 | INSN_NOP_I, | |
477ba620 AJ |
1378 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb)); |
1379 | } | |
1380 | ||
c7d4475a RH |
1381 | static inline void tcg_out_deposit(TCGContext *s, TCGArg ret, TCGArg a1, |
1382 | TCGArg a2, int const_a2, int pos, int len) | |
1383 | { | |
1384 | uint64_t i1 = 0, i2 = 0; | |
1385 | int cpos = 63 - pos, lm1 = len - 1; | |
1386 | ||
1387 | if (const_a2) { | |
1388 | /* Truncate the value of a constant a2 to the width of the field. */ | |
1389 | int mask = (1u << len) - 1; | |
1390 | a2 &= mask; | |
1391 | ||
1392 | if (a2 == 0 || a2 == mask) { | |
1393 | /* 1-bit signed constant inserted into register. */ | |
1394 | i2 = tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, ret, a2, a1, cpos, lm1); | |
1395 | } else { | |
1396 | /* Otherwise, load any constant into a temporary. Do this into | |
1397 | the first I slot to help out with cross-unit delays. */ | |
1398 | i1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, | |
1399 | TCG_REG_R2, a2, TCG_REG_R0); | |
1400 | a2 = TCG_REG_R2; | |
1401 | } | |
1402 | } | |
1403 | if (i2 == 0) { | |
1404 | i2 = tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, ret, a2, a1, cpos, lm1); | |
1405 | } | |
1406 | tcg_out_bundle(s, (i1 ? mII : miI), | |
5f7b1687 RH |
1407 | INSN_NOP_M, |
1408 | i1 ? i1 : INSN_NOP_I, | |
c7d4475a RH |
1409 | i2); |
1410 | } | |
1411 | ||
477ba620 AJ |
1412 | static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1, |
1413 | TCGArg arg2, int cmp4) | |
1414 | { | |
1415 | uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6; | |
1416 | ||
1417 | if (cmp4) { | |
1418 | opc_eq_a6 = OPC_CMP4_EQ_A6; | |
1419 | opc_lt_a6 = OPC_CMP4_LT_A6; | |
1420 | opc_ltu_a6 = OPC_CMP4_LTU_A6; | |
1421 | } else { | |
1422 | opc_eq_a6 = OPC_CMP_EQ_A6; | |
1423 | opc_lt_a6 = OPC_CMP_LT_A6; | |
1424 | opc_ltu_a6 = OPC_CMP_LTU_A6; | |
1425 | } | |
1426 | ||
1427 | switch (cond) { | |
1428 | case TCG_COND_EQ: | |
1429 | return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2); | |
1430 | case TCG_COND_NE: | |
1431 | return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2); | |
1432 | case TCG_COND_LT: | |
1433 | return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2); | |
1434 | case TCG_COND_LTU: | |
1435 | return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2); | |
1436 | case TCG_COND_GE: | |
1437 | return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2); | |
1438 | case TCG_COND_GEU: | |
1439 | return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2); | |
1440 | case TCG_COND_LE: | |
1441 | return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1); | |
1442 | case TCG_COND_LEU: | |
1443 | return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1); | |
1444 | case TCG_COND_GT: | |
1445 | return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1); | |
1446 | case TCG_COND_GTU: | |
1447 | return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1); | |
1448 | default: | |
1449 | tcg_abort(); | |
1450 | break; | |
1451 | } | |
1452 | } | |
1453 | ||
6d264b38 RH |
1454 | static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, |
1455 | TCGReg arg2, int label_index, int cmp4) | |
477ba620 AJ |
1456 | { |
1457 | TCGLabel *l = &s->labels[label_index]; | |
477ba620 | 1458 | |
6d264b38 | 1459 | tcg_out_bundle(s, miB, |
5f7b1687 | 1460 | INSN_NOP_M, |
6d264b38 RH |
1461 | tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4), |
1462 | tcg_opc_b1(TCG_REG_P6, OPC_BR_DPTK_FEW_B1, | |
1463 | get_reloc_pcrel21b(s->code_ptr + 2))); | |
477ba620 AJ |
1464 | |
1465 | if (l->has_value) { | |
1466 | reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value); | |
1467 | } else { | |
1468 | tcg_out_reloc(s, (s->code_ptr - 16) + 2, | |
1469 | R_IA64_PCREL21B, label_index, 0); | |
1470 | } | |
1471 | } | |
1472 | ||
1473 | static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret, | |
1474 | TCGArg arg1, TCGArg arg2, int cmp4) | |
1475 | { | |
1476 | tcg_out_bundle(s, MmI, | |
1477 | tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4), | |
1478 | tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0), | |
1479 | tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0)); | |
1480 | } | |
1481 | ||
b90cf716 AJ |
1482 | static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret, |
1483 | TCGArg c1, TCGArg c2, | |
1484 | TCGArg v1, int const_v1, | |
1485 | TCGArg v2, int const_v2, int cmp4) | |
1486 | { | |
1487 | uint64_t opc1, opc2; | |
1488 | ||
1489 | if (const_v1) { | |
1490 | opc1 = tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, v1, TCG_REG_R0); | |
1491 | } else if (ret == v1) { | |
5f7b1687 | 1492 | opc1 = INSN_NOP_M; |
b90cf716 AJ |
1493 | } else { |
1494 | opc1 = tcg_opc_a4(TCG_REG_P6, OPC_ADDS_A4, ret, 0, v1); | |
1495 | } | |
1496 | if (const_v2) { | |
1497 | opc2 = tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, v2, TCG_REG_R0); | |
1498 | } else if (ret == v2) { | |
5f7b1687 | 1499 | opc2 = INSN_NOP_I; |
b90cf716 AJ |
1500 | } else { |
1501 | opc2 = tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, ret, 0, v2); | |
1502 | } | |
1503 | ||
1504 | tcg_out_bundle(s, MmI, | |
1505 | tcg_opc_cmp_a(TCG_REG_P0, cond, c1, c2, cmp4), | |
1506 | opc1, | |
1507 | opc2); | |
1508 | } | |
1509 | ||
477ba620 | 1510 | #if defined(CONFIG_SOFTMMU) |
477ba620 AJ |
1511 | /* Load and compare a TLB entry, and return the result in (p6, p7). |
1512 | R2 is loaded with the address of the addend TLB entry. | |
2174d1e1 | 1513 | R57 is loaded with the address, zero extented on 32-bit targets. */ |
477ba620 | 1514 | static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg, |
e3afa1c4 | 1515 | TCGMemOp s_bits, uint64_t offset_rw, |
477ba620 AJ |
1516 | uint64_t offset_addend) |
1517 | { | |
1518 | tcg_out_bundle(s, mII, | |
5f7b1687 | 1519 | INSN_NOP_M, |
477ba620 AJ |
1520 | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2, |
1521 | addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1), | |
1522 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2, | |
1523 | TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS, | |
1524 | 63 - CPU_TLB_ENTRY_BITS)); | |
1525 | tcg_out_bundle(s, mII, | |
1526 | tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2, | |
1527 | offset_rw, TCG_REG_R2), | |
1528 | #if TARGET_LONG_BITS == 32 | |
2174d1e1 | 1529 | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R57, addr_reg), |
477ba620 | 1530 | #else |
2174d1e1 | 1531 | tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R57, |
477ba620 AJ |
1532 | 0, addr_reg), |
1533 | #endif | |
1534 | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, | |
1535 | TCG_REG_R2, TCG_AREG0)); | |
1536 | tcg_out_bundle(s, mII, | |
650a217a RH |
1537 | tcg_opc_m3 (TCG_REG_P0, |
1538 | (TARGET_LONG_BITS == 32 | |
2174d1e1 | 1539 | ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R56, |
477ba620 | 1540 | TCG_REG_R2, offset_addend - offset_rw), |
63975ea7 AJ |
1541 | tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, TCG_REG_R3, 0, |
1542 | TCG_REG_R57, 63 - s_bits, | |
1543 | TARGET_PAGE_BITS - s_bits - 1), | |
477ba620 | 1544 | tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6, |
2174d1e1 | 1545 | TCG_REG_P7, TCG_REG_R3, TCG_REG_R56)); |
477ba620 AJ |
1546 | } |
1547 | ||
e141ab52 BS |
1548 | /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, |
1549 | int mmu_idx) */ | |
1550 | static const void * const qemu_ld_helpers[4] = { | |
1551 | helper_ldb_mmu, | |
1552 | helper_ldw_mmu, | |
1553 | helper_ldl_mmu, | |
1554 | helper_ldq_mmu, | |
1555 | }; | |
477ba620 | 1556 | |
e3afa1c4 RH |
1557 | static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
1558 | TCGMemOp opc) | |
477ba620 | 1559 | { |
e3afa1c4 RH |
1560 | static const uint64_t opc_ld_m1[4] = { |
1561 | OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 | |
1562 | }; | |
1563 | static const uint64_t opc_ext_i29[8] = { | |
1564 | OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0, | |
1565 | OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 | |
1566 | }; | |
1567 | int addr_reg, data_reg, mem_index; | |
1568 | TCGMemOp s_bits, bswap; | |
477ba620 AJ |
1569 | |
1570 | data_reg = *args++; | |
1571 | addr_reg = *args++; | |
1572 | mem_index = *args; | |
e3afa1c4 RH |
1573 | s_bits = opc & MO_SIZE; |
1574 | bswap = opc & MO_BSWAP; | |
477ba620 AJ |
1575 | |
1576 | /* Read the TLB entry */ | |
1577 | tcg_out_qemu_tlb(s, addr_reg, s_bits, | |
9349b4f9 AF |
1578 | offsetof(CPUArchState, tlb_table[mem_index][0].addr_read), |
1579 | offsetof(CPUArchState, tlb_table[mem_index][0].addend)); | |
477ba620 AJ |
1580 | |
1581 | /* P6 is the fast path, and P7 the slow path */ | |
1582 | tcg_out_bundle(s, mLX, | |
2174d1e1 AJ |
1583 | tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, |
1584 | TCG_REG_R56, 0, TCG_AREG0), | |
477ba620 AJ |
1585 | tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]), |
1586 | tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2, | |
1587 | (tcg_target_long) qemu_ld_helpers[s_bits])); | |
1588 | tcg_out_bundle(s, MmI, | |
1589 | tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3, | |
1590 | TCG_REG_R2, 8), | |
1591 | tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3, | |
2174d1e1 | 1592 | TCG_REG_R3, TCG_REG_R57), |
477ba620 AJ |
1593 | tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, |
1594 | TCG_REG_R3, 0)); | |
e3afa1c4 | 1595 | if (bswap && s_bits == MO_16) { |
477ba620 AJ |
1596 | tcg_out_bundle(s, MmI, |
1597 | tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], | |
1598 | TCG_REG_R8, TCG_REG_R3), | |
1599 | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), | |
1600 | tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, | |
1601 | TCG_REG_R8, TCG_REG_R8, 15, 15)); | |
e3afa1c4 | 1602 | } else if (bswap && s_bits == MO_32) { |
477ba620 AJ |
1603 | tcg_out_bundle(s, MmI, |
1604 | tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], | |
1605 | TCG_REG_R8, TCG_REG_R3), | |
1606 | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), | |
1607 | tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, | |
1608 | TCG_REG_R8, TCG_REG_R8, 31, 31)); | |
1609 | } else { | |
1610 | tcg_out_bundle(s, mmI, | |
1611 | tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], | |
1612 | TCG_REG_R8, TCG_REG_R3), | |
1613 | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), | |
5f7b1687 | 1614 | INSN_NOP_I); |
477ba620 | 1615 | } |
e3afa1c4 | 1616 | if (!bswap) { |
477ba620 | 1617 | tcg_out_bundle(s, miB, |
2174d1e1 AJ |
1618 | tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58, |
1619 | mem_index, TCG_REG_R0), | |
5f7b1687 | 1620 | INSN_NOP_I, |
477ba620 AJ |
1621 | tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, |
1622 | TCG_REG_B0, TCG_REG_B6)); | |
1623 | } else { | |
1624 | tcg_out_bundle(s, miB, | |
2174d1e1 AJ |
1625 | tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58, |
1626 | mem_index, TCG_REG_R0), | |
477ba620 AJ |
1627 | tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
1628 | TCG_REG_R8, TCG_REG_R8, 0xb), | |
1629 | tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, | |
1630 | TCG_REG_B0, TCG_REG_B6)); | |
1631 | } | |
1632 | ||
e3afa1c4 | 1633 | if (s_bits == MO_64) { |
477ba620 | 1634 | tcg_out_bundle(s, miI, |
5f7b1687 RH |
1635 | INSN_NOP_M, |
1636 | INSN_NOP_I, | |
477ba620 AJ |
1637 | tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, |
1638 | data_reg, 0, TCG_REG_R8)); | |
1639 | } else { | |
1640 | tcg_out_bundle(s, miI, | |
5f7b1687 RH |
1641 | INSN_NOP_M, |
1642 | INSN_NOP_I, | |
e3afa1c4 | 1643 | tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc & MO_SSIZE], |
477ba620 AJ |
1644 | data_reg, TCG_REG_R8)); |
1645 | } | |
1646 | } | |
1647 | ||
e141ab52 BS |
1648 | /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, |
1649 | uintxx_t val, int mmu_idx) */ | |
1650 | static const void * const qemu_st_helpers[4] = { | |
1651 | helper_stb_mmu, | |
1652 | helper_stw_mmu, | |
1653 | helper_stl_mmu, | |
1654 | helper_stq_mmu, | |
1655 | }; | |
477ba620 | 1656 | |
e3afa1c4 RH |
1657 | static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
1658 | TCGMemOp opc) | |
477ba620 | 1659 | { |
e3afa1c4 RH |
1660 | static const uint64_t opc_st_m4[4] = { |
1661 | OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 | |
1662 | }; | |
1663 | int addr_reg, data_reg, mem_index; | |
1664 | TCGMemOp s_bits; | |
477ba620 AJ |
1665 | |
1666 | data_reg = *args++; | |
1667 | addr_reg = *args++; | |
1668 | mem_index = *args; | |
e3afa1c4 | 1669 | s_bits = opc & MO_SIZE; |
477ba620 | 1670 | |
e3afa1c4 | 1671 | tcg_out_qemu_tlb(s, addr_reg, s_bits, |
9349b4f9 AF |
1672 | offsetof(CPUArchState, tlb_table[mem_index][0].addr_write), |
1673 | offsetof(CPUArchState, tlb_table[mem_index][0].addend)); | |
477ba620 AJ |
1674 | |
1675 | /* P6 is the fast path, and P7 the slow path */ | |
1676 | tcg_out_bundle(s, mLX, | |
2174d1e1 AJ |
1677 | tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, |
1678 | TCG_REG_R56, 0, TCG_AREG0), | |
e3afa1c4 | 1679 | tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[s_bits]), |
477ba620 | 1680 | tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2, |
e3afa1c4 | 1681 | (tcg_target_long) qemu_st_helpers[s_bits])); |
477ba620 AJ |
1682 | tcg_out_bundle(s, MmI, |
1683 | tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3, | |
1684 | TCG_REG_R2, 8), | |
1685 | tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3, | |
2174d1e1 | 1686 | TCG_REG_R3, TCG_REG_R57), |
477ba620 AJ |
1687 | tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, |
1688 | TCG_REG_R3, 0)); | |
1689 | ||
e3afa1c4 RH |
1690 | switch (opc) { |
1691 | case MO_8: | |
1692 | case MO_16: | |
1693 | case MO_32: | |
1694 | case MO_64: | |
2174d1e1 | 1695 | tcg_out_bundle(s, mii, |
477ba620 AJ |
1696 | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
1697 | TCG_REG_R1, TCG_REG_R2), | |
2174d1e1 AJ |
1698 | tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58, |
1699 | 0, data_reg), | |
5f7b1687 | 1700 | INSN_NOP_I); |
e3afa1c4 RH |
1701 | break; |
1702 | ||
1703 | case MO_16 | MO_BSWAP: | |
2174d1e1 | 1704 | tcg_out_bundle(s, miI, |
477ba620 AJ |
1705 | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
1706 | TCG_REG_R1, TCG_REG_R2), | |
5f7b1687 | 1707 | INSN_NOP_I, |
477ba620 | 1708 | tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, |
2174d1e1 AJ |
1709 | TCG_REG_R2, data_reg, 15, 15)); |
1710 | tcg_out_bundle(s, miI, | |
1711 | tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58, | |
1712 | 0, data_reg), | |
5f7b1687 | 1713 | INSN_NOP_I, |
477ba620 AJ |
1714 | tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
1715 | TCG_REG_R2, TCG_REG_R2, 0xb)); | |
1716 | data_reg = TCG_REG_R2; | |
e3afa1c4 RH |
1717 | break; |
1718 | ||
1719 | case MO_32 | MO_BSWAP: | |
2174d1e1 | 1720 | tcg_out_bundle(s, miI, |
477ba620 AJ |
1721 | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
1722 | TCG_REG_R1, TCG_REG_R2), | |
5f7b1687 | 1723 | INSN_NOP_I, |
477ba620 | 1724 | tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, |
2174d1e1 AJ |
1725 | TCG_REG_R2, data_reg, 31, 31)); |
1726 | tcg_out_bundle(s, miI, | |
1727 | tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58, | |
1728 | 0, data_reg), | |
5f7b1687 | 1729 | INSN_NOP_I, |
477ba620 AJ |
1730 | tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
1731 | TCG_REG_R2, TCG_REG_R2, 0xb)); | |
1732 | data_reg = TCG_REG_R2; | |
e3afa1c4 RH |
1733 | break; |
1734 | ||
1735 | case MO_64 | MO_BSWAP: | |
477ba620 AJ |
1736 | tcg_out_bundle(s, miI, |
1737 | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, | |
1738 | TCG_REG_R1, TCG_REG_R2), | |
2174d1e1 AJ |
1739 | tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58, |
1740 | 0, data_reg), | |
477ba620 AJ |
1741 | tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
1742 | TCG_REG_R2, data_reg, 0xb)); | |
1743 | data_reg = TCG_REG_R2; | |
e3afa1c4 RH |
1744 | break; |
1745 | ||
1746 | default: | |
1747 | tcg_abort(); | |
477ba620 AJ |
1748 | } |
1749 | ||
d03c98d8 | 1750 | tcg_out_bundle(s, miB, |
e3afa1c4 | 1751 | tcg_opc_m4 (TCG_REG_P6, opc_st_m4[s_bits], |
d03c98d8 | 1752 | data_reg, TCG_REG_R3), |
2174d1e1 AJ |
1753 | tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59, |
1754 | mem_index, TCG_REG_R0), | |
d03c98d8 AJ |
1755 | tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, |
1756 | TCG_REG_B0, TCG_REG_B6)); | |
477ba620 AJ |
1757 | } |
1758 | ||
1759 | #else /* !CONFIG_SOFTMMU */ | |
1760 | ||
e3afa1c4 RH |
1761 | static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
1762 | TCGMemOp opc) | |
477ba620 | 1763 | { |
6781d08d RH |
1764 | static uint64_t const opc_ld_m1[4] = { |
1765 | OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 | |
1766 | }; | |
1767 | static uint64_t const opc_sxt_i29[4] = { | |
1768 | OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 | |
1769 | }; | |
e3afa1c4 RH |
1770 | int addr_reg, data_reg; |
1771 | TCGMemOp s_bits, bswap; | |
477ba620 AJ |
1772 | |
1773 | data_reg = *args++; | |
1774 | addr_reg = *args++; | |
e3afa1c4 RH |
1775 | s_bits = opc & MO_SIZE; |
1776 | bswap = opc & MO_BSWAP; | |
477ba620 | 1777 | |
477ba620 | 1778 | #if TARGET_LONG_BITS == 32 |
6781d08d RH |
1779 | if (GUEST_BASE != 0) { |
1780 | tcg_out_bundle(s, mII, | |
5f7b1687 | 1781 | INSN_NOP_M, |
6781d08d RH |
1782 | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, |
1783 | TCG_REG_R3, addr_reg), | |
1784 | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, | |
1785 | TCG_GUEST_BASE_REG, TCG_REG_R3)); | |
1786 | } else { | |
1787 | tcg_out_bundle(s, miI, | |
5f7b1687 | 1788 | INSN_NOP_M, |
6781d08d RH |
1789 | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, |
1790 | TCG_REG_R2, addr_reg), | |
5f7b1687 | 1791 | INSN_NOP_I); |
6781d08d | 1792 | } |
477ba620 | 1793 | |
e3afa1c4 RH |
1794 | if (!bswap) { |
1795 | if (!(opc & MO_SIGN)) { | |
477ba620 AJ |
1796 | tcg_out_bundle(s, miI, |
1797 | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], | |
1798 | data_reg, TCG_REG_R2), | |
5f7b1687 RH |
1799 | INSN_NOP_I, |
1800 | INSN_NOP_I); | |
477ba620 AJ |
1801 | } else { |
1802 | tcg_out_bundle(s, mII, | |
1803 | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], | |
1804 | data_reg, TCG_REG_R2), | |
5f7b1687 | 1805 | INSN_NOP_I, |
477ba620 AJ |
1806 | tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], |
1807 | data_reg, data_reg)); | |
1808 | } | |
e3afa1c4 | 1809 | } else if (s_bits == MO_64) { |
477ba620 AJ |
1810 | tcg_out_bundle(s, mII, |
1811 | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], | |
1812 | data_reg, TCG_REG_R2), | |
5f7b1687 | 1813 | INSN_NOP_I, |
477ba620 AJ |
1814 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1815 | data_reg, data_reg, 0xb)); | |
1816 | } else { | |
e3afa1c4 | 1817 | if (s_bits == MO_16) { |
477ba620 AJ |
1818 | tcg_out_bundle(s, mII, |
1819 | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], | |
1820 | data_reg, TCG_REG_R2), | |
5f7b1687 | 1821 | INSN_NOP_I, |
477ba620 AJ |
1822 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1823 | data_reg, data_reg, 15, 15)); | |
1824 | } else { | |
1825 | tcg_out_bundle(s, mII, | |
1826 | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], | |
1827 | data_reg, TCG_REG_R2), | |
5f7b1687 | 1828 | INSN_NOP_I, |
477ba620 AJ |
1829 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1830 | data_reg, data_reg, 31, 31)); | |
1831 | } | |
e3afa1c4 | 1832 | if (!(opc & MO_SIGN)) { |
477ba620 | 1833 | tcg_out_bundle(s, miI, |
5f7b1687 RH |
1834 | INSN_NOP_M, |
1835 | INSN_NOP_I, | |
477ba620 AJ |
1836 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1837 | data_reg, data_reg, 0xb)); | |
1838 | } else { | |
1839 | tcg_out_bundle(s, mII, | |
5f7b1687 | 1840 | INSN_NOP_M, |
477ba620 AJ |
1841 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1842 | data_reg, data_reg, 0xb), | |
1843 | tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], | |
1844 | data_reg, data_reg)); | |
1845 | } | |
1846 | } | |
1847 | #else | |
6781d08d RH |
1848 | if (GUEST_BASE != 0) { |
1849 | tcg_out_bundle(s, MmI, | |
1850 | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, | |
1851 | TCG_GUEST_BASE_REG, addr_reg), | |
1852 | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], | |
1853 | data_reg, TCG_REG_R2), | |
5f7b1687 | 1854 | INSN_NOP_I); |
6781d08d RH |
1855 | } else { |
1856 | tcg_out_bundle(s, mmI, | |
5f7b1687 | 1857 | INSN_NOP_M, |
6781d08d RH |
1858 | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
1859 | data_reg, addr_reg), | |
5f7b1687 | 1860 | INSN_NOP_I); |
6781d08d | 1861 | } |
477ba620 | 1862 | |
e3afa1c4 | 1863 | if (bswap && s_bits == MO_16) { |
477ba620 | 1864 | tcg_out_bundle(s, mII, |
5f7b1687 | 1865 | INSN_NOP_M, |
477ba620 AJ |
1866 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1867 | data_reg, data_reg, 15, 15), | |
1868 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1869 | data_reg, data_reg, 0xb)); | |
e3afa1c4 | 1870 | } else if (bswap && s_bits == MO_32) { |
477ba620 | 1871 | tcg_out_bundle(s, mII, |
5f7b1687 | 1872 | INSN_NOP_M, |
477ba620 AJ |
1873 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1874 | data_reg, data_reg, 31, 31), | |
1875 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1876 | data_reg, data_reg, 0xb)); | |
e3afa1c4 | 1877 | } else if (bswap && s_bits == MO_64) { |
477ba620 | 1878 | tcg_out_bundle(s, miI, |
5f7b1687 RH |
1879 | INSN_NOP_M, |
1880 | INSN_NOP_I, | |
477ba620 AJ |
1881 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1882 | data_reg, data_reg, 0xb)); | |
1883 | } | |
e3afa1c4 | 1884 | if (opc & MO_SIGN) { |
477ba620 | 1885 | tcg_out_bundle(s, miI, |
5f7b1687 RH |
1886 | INSN_NOP_M, |
1887 | INSN_NOP_I, | |
477ba620 AJ |
1888 | tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], |
1889 | data_reg, data_reg)); | |
1890 | } | |
1891 | #endif | |
1892 | } | |
1893 | ||
e3afa1c4 RH |
1894 | static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
1895 | TCGMemOp opc) | |
477ba620 | 1896 | { |
6781d08d RH |
1897 | static uint64_t const opc_st_m4[4] = { |
1898 | OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 | |
1899 | }; | |
e3afa1c4 | 1900 | int addr_reg, data_reg; |
6781d08d RH |
1901 | #if TARGET_LONG_BITS == 64 |
1902 | uint64_t add_guest_base; | |
1903 | #endif | |
e3afa1c4 | 1904 | TCGMemOp s_bits, bswap; |
477ba620 AJ |
1905 | |
1906 | data_reg = *args++; | |
1907 | addr_reg = *args++; | |
e3afa1c4 RH |
1908 | s_bits = opc & MO_SIZE; |
1909 | bswap = opc & MO_BSWAP; | |
477ba620 | 1910 | |
477ba620 | 1911 | #if TARGET_LONG_BITS == 32 |
6781d08d RH |
1912 | if (GUEST_BASE != 0) { |
1913 | tcg_out_bundle(s, mII, | |
5f7b1687 | 1914 | INSN_NOP_M, |
6781d08d RH |
1915 | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, |
1916 | TCG_REG_R3, addr_reg), | |
1917 | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, | |
1918 | TCG_GUEST_BASE_REG, TCG_REG_R3)); | |
1919 | } else { | |
1920 | tcg_out_bundle(s, miI, | |
5f7b1687 | 1921 | INSN_NOP_M, |
6781d08d | 1922 | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, |
07f59737 | 1923 | TCG_REG_R2, addr_reg), |
5f7b1687 | 1924 | INSN_NOP_I); |
6781d08d RH |
1925 | } |
1926 | ||
477ba620 | 1927 | if (bswap) { |
e3afa1c4 | 1928 | if (s_bits == MO_16) { |
477ba620 | 1929 | tcg_out_bundle(s, mII, |
5f7b1687 | 1930 | INSN_NOP_M, |
477ba620 AJ |
1931 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1932 | TCG_REG_R3, data_reg, 15, 15), | |
1933 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1934 | TCG_REG_R3, TCG_REG_R3, 0xb)); | |
1935 | data_reg = TCG_REG_R3; | |
e3afa1c4 | 1936 | } else if (s_bits == MO_32) { |
477ba620 | 1937 | tcg_out_bundle(s, mII, |
5f7b1687 | 1938 | INSN_NOP_M, |
477ba620 AJ |
1939 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1940 | TCG_REG_R3, data_reg, 31, 31), | |
1941 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1942 | TCG_REG_R3, TCG_REG_R3, 0xb)); | |
1943 | data_reg = TCG_REG_R3; | |
e3afa1c4 | 1944 | } else if (s_bits == MO_64) { |
477ba620 | 1945 | tcg_out_bundle(s, miI, |
5f7b1687 RH |
1946 | INSN_NOP_M, |
1947 | INSN_NOP_I, | |
477ba620 AJ |
1948 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1949 | TCG_REG_R3, data_reg, 0xb)); | |
1950 | data_reg = TCG_REG_R3; | |
1951 | } | |
1952 | } | |
1953 | tcg_out_bundle(s, mmI, | |
e3afa1c4 | 1954 | tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits], |
477ba620 | 1955 | data_reg, TCG_REG_R2), |
5f7b1687 RH |
1956 | INSN_NOP_M, |
1957 | INSN_NOP_I); | |
477ba620 | 1958 | #else |
6781d08d RH |
1959 | if (GUEST_BASE != 0) { |
1960 | add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, | |
1961 | TCG_GUEST_BASE_REG, addr_reg); | |
1962 | addr_reg = TCG_REG_R2; | |
1963 | } else { | |
5f7b1687 | 1964 | add_guest_base = INSN_NOP_M; |
6781d08d RH |
1965 | } |
1966 | ||
e3afa1c4 | 1967 | if (!bswap) { |
6781d08d RH |
1968 | tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI), |
1969 | add_guest_base, | |
e3afa1c4 | 1970 | tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits], |
6781d08d | 1971 | data_reg, addr_reg), |
5f7b1687 | 1972 | INSN_NOP_I); |
477ba620 | 1973 | } else { |
e3afa1c4 | 1974 | if (s_bits == MO_16) { |
477ba620 | 1975 | tcg_out_bundle(s, mII, |
6781d08d | 1976 | add_guest_base, |
477ba620 AJ |
1977 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1978 | TCG_REG_R3, data_reg, 15, 15), | |
1979 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1980 | TCG_REG_R3, TCG_REG_R3, 0xb)); | |
1981 | data_reg = TCG_REG_R3; | |
e3afa1c4 | 1982 | } else if (s_bits == MO_32) { |
477ba620 | 1983 | tcg_out_bundle(s, mII, |
6781d08d | 1984 | add_guest_base, |
477ba620 AJ |
1985 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1986 | TCG_REG_R3, data_reg, 31, 31), | |
1987 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1988 | TCG_REG_R3, TCG_REG_R3, 0xb)); | |
1989 | data_reg = TCG_REG_R3; | |
e3afa1c4 | 1990 | } else if (s_bits == MO_64) { |
477ba620 | 1991 | tcg_out_bundle(s, miI, |
6781d08d | 1992 | add_guest_base, |
5f7b1687 | 1993 | INSN_NOP_I, |
477ba620 AJ |
1994 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1995 | TCG_REG_R3, data_reg, 0xb)); | |
1996 | data_reg = TCG_REG_R3; | |
1997 | } | |
1998 | tcg_out_bundle(s, miI, | |
e3afa1c4 | 1999 | tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits], |
6781d08d | 2000 | data_reg, addr_reg), |
5f7b1687 RH |
2001 | INSN_NOP_I, |
2002 | INSN_NOP_I); | |
477ba620 AJ |
2003 | } |
2004 | #endif | |
2005 | } | |
2006 | ||
2007 | #endif | |
2008 | ||
2009 | static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, | |
2010 | const TCGArg *args, const int *const_args) | |
2011 | { | |
2012 | switch(opc) { | |
2013 | case INDEX_op_exit_tb: | |
2014 | tcg_out_exit_tb(s, args[0]); | |
2015 | break; | |
2016 | case INDEX_op_br: | |
2017 | tcg_out_br(s, args[0]); | |
2018 | break; | |
2019 | case INDEX_op_call: | |
6f65c780 RH |
2020 | if (likely(const_args[0])) { |
2021 | tcg_out_calli(s, args[0]); | |
2022 | } else { | |
2023 | tcg_out_callr(s, args[0]); | |
2024 | } | |
477ba620 AJ |
2025 | break; |
2026 | case INDEX_op_goto_tb: | |
2027 | tcg_out_goto_tb(s, args[0]); | |
2028 | break; | |
477ba620 AJ |
2029 | |
2030 | case INDEX_op_movi_i32: | |
2031 | tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]); | |
2032 | break; | |
2033 | case INDEX_op_movi_i64: | |
2034 | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); | |
2035 | break; | |
2036 | ||
2037 | case INDEX_op_ld8u_i32: | |
2038 | case INDEX_op_ld8u_i64: | |
2039 | tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]); | |
2040 | break; | |
2041 | case INDEX_op_ld8s_i32: | |
2042 | case INDEX_op_ld8s_i64: | |
2043 | tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]); | |
2044 | tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]); | |
2045 | break; | |
2046 | case INDEX_op_ld16u_i32: | |
2047 | case INDEX_op_ld16u_i64: | |
2048 | tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]); | |
2049 | break; | |
2050 | case INDEX_op_ld16s_i32: | |
2051 | case INDEX_op_ld16s_i64: | |
2052 | tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]); | |
2053 | tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]); | |
2054 | break; | |
2055 | case INDEX_op_ld_i32: | |
2056 | case INDEX_op_ld32u_i64: | |
2057 | tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]); | |
2058 | break; | |
2059 | case INDEX_op_ld32s_i64: | |
2060 | tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]); | |
2061 | tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]); | |
2062 | break; | |
2063 | case INDEX_op_ld_i64: | |
2064 | tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]); | |
2065 | break; | |
2066 | case INDEX_op_st8_i32: | |
2067 | case INDEX_op_st8_i64: | |
2068 | tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]); | |
2069 | break; | |
2070 | case INDEX_op_st16_i32: | |
2071 | case INDEX_op_st16_i64: | |
2072 | tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]); | |
2073 | break; | |
2074 | case INDEX_op_st_i32: | |
2075 | case INDEX_op_st32_i64: | |
2076 | tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]); | |
2077 | break; | |
2078 | case INDEX_op_st_i64: | |
2079 | tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]); | |
2080 | break; | |
2081 | ||
2082 | case INDEX_op_add_i32: | |
2083 | case INDEX_op_add_i64: | |
8642088a | 2084 | tcg_out_add(s, args[0], args[1], args[2], const_args[2]); |
477ba620 AJ |
2085 | break; |
2086 | case INDEX_op_sub_i32: | |
2087 | case INDEX_op_sub_i64: | |
2088 | tcg_out_alu(s, OPC_SUB_A1, args[0], args[1], const_args[1], | |
2089 | args[2], const_args[2]); | |
2090 | break; | |
2091 | ||
2092 | case INDEX_op_and_i32: | |
2093 | case INDEX_op_and_i64: | |
2094 | tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1], | |
2095 | args[2], const_args[2]); | |
2096 | break; | |
2097 | case INDEX_op_andc_i32: | |
2098 | case INDEX_op_andc_i64: | |
2099 | tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1], | |
2100 | args[2], const_args[2]); | |
2101 | break; | |
2102 | case INDEX_op_eqv_i32: | |
2103 | case INDEX_op_eqv_i64: | |
2104 | tcg_out_eqv(s, args[0], args[1], const_args[1], | |
2105 | args[2], const_args[2]); | |
2106 | break; | |
2107 | case INDEX_op_nand_i32: | |
2108 | case INDEX_op_nand_i64: | |
2109 | tcg_out_nand(s, args[0], args[1], const_args[1], | |
2110 | args[2], const_args[2]); | |
2111 | break; | |
2112 | case INDEX_op_nor_i32: | |
2113 | case INDEX_op_nor_i64: | |
2114 | tcg_out_nor(s, args[0], args[1], const_args[1], | |
2115 | args[2], const_args[2]); | |
2116 | break; | |
2117 | case INDEX_op_or_i32: | |
2118 | case INDEX_op_or_i64: | |
2119 | tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1], | |
2120 | args[2], const_args[2]); | |
2121 | break; | |
2122 | case INDEX_op_orc_i32: | |
2123 | case INDEX_op_orc_i64: | |
2124 | tcg_out_orc(s, args[0], args[1], const_args[1], | |
2125 | args[2], const_args[2]); | |
2126 | break; | |
2127 | case INDEX_op_xor_i32: | |
2128 | case INDEX_op_xor_i64: | |
2129 | tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1], | |
2130 | args[2], const_args[2]); | |
2131 | break; | |
2132 | ||
2133 | case INDEX_op_mul_i32: | |
2134 | case INDEX_op_mul_i64: | |
2135 | tcg_out_mul(s, args[0], args[1], args[2]); | |
2136 | break; | |
2137 | ||
2138 | case INDEX_op_sar_i32: | |
2139 | tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]); | |
2140 | break; | |
2141 | case INDEX_op_sar_i64: | |
2142 | tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]); | |
2143 | break; | |
2144 | case INDEX_op_shl_i32: | |
2145 | tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]); | |
2146 | break; | |
2147 | case INDEX_op_shl_i64: | |
2148 | tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]); | |
2149 | break; | |
2150 | case INDEX_op_shr_i32: | |
2151 | tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]); | |
2152 | break; | |
2153 | case INDEX_op_shr_i64: | |
2154 | tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]); | |
2155 | break; | |
2156 | case INDEX_op_rotl_i32: | |
2157 | tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]); | |
2158 | break; | |
2159 | case INDEX_op_rotl_i64: | |
2160 | tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]); | |
2161 | break; | |
2162 | case INDEX_op_rotr_i32: | |
2163 | tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]); | |
2164 | break; | |
2165 | case INDEX_op_rotr_i64: | |
2166 | tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]); | |
2167 | break; | |
2168 | ||
2169 | case INDEX_op_ext8s_i32: | |
2170 | case INDEX_op_ext8s_i64: | |
2171 | tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]); | |
2172 | break; | |
2173 | case INDEX_op_ext8u_i32: | |
2174 | case INDEX_op_ext8u_i64: | |
2175 | tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]); | |
2176 | break; | |
2177 | case INDEX_op_ext16s_i32: | |
2178 | case INDEX_op_ext16s_i64: | |
2179 | tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]); | |
2180 | break; | |
2181 | case INDEX_op_ext16u_i32: | |
2182 | case INDEX_op_ext16u_i64: | |
2183 | tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]); | |
2184 | break; | |
2185 | case INDEX_op_ext32s_i64: | |
2186 | tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]); | |
2187 | break; | |
2188 | case INDEX_op_ext32u_i64: | |
2189 | tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]); | |
2190 | break; | |
2191 | ||
2192 | case INDEX_op_bswap16_i32: | |
2193 | case INDEX_op_bswap16_i64: | |
2194 | tcg_out_bswap16(s, args[0], args[1]); | |
2195 | break; | |
2196 | case INDEX_op_bswap32_i32: | |
2197 | case INDEX_op_bswap32_i64: | |
2198 | tcg_out_bswap32(s, args[0], args[1]); | |
2199 | break; | |
2200 | case INDEX_op_bswap64_i64: | |
2201 | tcg_out_bswap64(s, args[0], args[1]); | |
2202 | break; | |
2203 | ||
c7d4475a RH |
2204 | case INDEX_op_deposit_i32: |
2205 | case INDEX_op_deposit_i64: | |
2206 | tcg_out_deposit(s, args[0], args[1], args[2], const_args[2], | |
2207 | args[3], args[4]); | |
2208 | break; | |
2209 | ||
477ba620 | 2210 | case INDEX_op_brcond_i32: |
6d264b38 | 2211 | tcg_out_brcond(s, args[2], args[0], args[1], args[3], 1); |
477ba620 AJ |
2212 | break; |
2213 | case INDEX_op_brcond_i64: | |
6d264b38 | 2214 | tcg_out_brcond(s, args[2], args[0], args[1], args[3], 0); |
477ba620 AJ |
2215 | break; |
2216 | case INDEX_op_setcond_i32: | |
2217 | tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1); | |
2218 | break; | |
2219 | case INDEX_op_setcond_i64: | |
2220 | tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0); | |
2221 | break; | |
b90cf716 AJ |
2222 | case INDEX_op_movcond_i32: |
2223 | tcg_out_movcond(s, args[5], args[0], args[1], args[2], | |
2224 | args[3], const_args[3], args[4], const_args[4], 1); | |
2225 | break; | |
2226 | case INDEX_op_movcond_i64: | |
2227 | tcg_out_movcond(s, args[5], args[0], args[1], args[2], | |
2228 | args[3], const_args[3], args[4], const_args[4], 0); | |
2229 | break; | |
477ba620 AJ |
2230 | |
2231 | case INDEX_op_qemu_ld8u: | |
e3afa1c4 | 2232 | tcg_out_qemu_ld(s, args, MO_UB); |
477ba620 AJ |
2233 | break; |
2234 | case INDEX_op_qemu_ld8s: | |
e3afa1c4 | 2235 | tcg_out_qemu_ld(s, args, MO_SB); |
477ba620 AJ |
2236 | break; |
2237 | case INDEX_op_qemu_ld16u: | |
e3afa1c4 | 2238 | tcg_out_qemu_ld(s, args, MO_TEUW); |
477ba620 AJ |
2239 | break; |
2240 | case INDEX_op_qemu_ld16s: | |
e3afa1c4 | 2241 | tcg_out_qemu_ld(s, args, MO_TESW); |
477ba620 | 2242 | break; |
b3b0091f | 2243 | case INDEX_op_qemu_ld32: |
477ba620 | 2244 | case INDEX_op_qemu_ld32u: |
e3afa1c4 | 2245 | tcg_out_qemu_ld(s, args, MO_TEUL); |
477ba620 AJ |
2246 | break; |
2247 | case INDEX_op_qemu_ld32s: | |
e3afa1c4 | 2248 | tcg_out_qemu_ld(s, args, MO_TESL); |
477ba620 AJ |
2249 | break; |
2250 | case INDEX_op_qemu_ld64: | |
e3afa1c4 | 2251 | tcg_out_qemu_ld(s, args, MO_TEQ); |
477ba620 AJ |
2252 | break; |
2253 | ||
2254 | case INDEX_op_qemu_st8: | |
e3afa1c4 | 2255 | tcg_out_qemu_st(s, args, MO_UB); |
477ba620 AJ |
2256 | break; |
2257 | case INDEX_op_qemu_st16: | |
e3afa1c4 | 2258 | tcg_out_qemu_st(s, args, MO_TEUW); |
477ba620 AJ |
2259 | break; |
2260 | case INDEX_op_qemu_st32: | |
e3afa1c4 | 2261 | tcg_out_qemu_st(s, args, MO_TEUL); |
477ba620 AJ |
2262 | break; |
2263 | case INDEX_op_qemu_st64: | |
e3afa1c4 | 2264 | tcg_out_qemu_st(s, args, MO_TEQ); |
477ba620 AJ |
2265 | break; |
2266 | ||
2267 | default: | |
2268 | tcg_abort(); | |
2269 | } | |
2270 | } | |
2271 | ||
2272 | static const TCGTargetOpDef ia64_op_defs[] = { | |
2273 | { INDEX_op_br, { } }, | |
6f65c780 | 2274 | { INDEX_op_call, { "ri" } }, |
477ba620 AJ |
2275 | { INDEX_op_exit_tb, { } }, |
2276 | { INDEX_op_goto_tb, { } }, | |
477ba620 AJ |
2277 | |
2278 | { INDEX_op_mov_i32, { "r", "r" } }, | |
2279 | { INDEX_op_movi_i32, { "r" } }, | |
2280 | ||
2281 | { INDEX_op_ld8u_i32, { "r", "r" } }, | |
2282 | { INDEX_op_ld8s_i32, { "r", "r" } }, | |
2283 | { INDEX_op_ld16u_i32, { "r", "r" } }, | |
2284 | { INDEX_op_ld16s_i32, { "r", "r" } }, | |
2285 | { INDEX_op_ld_i32, { "r", "r" } }, | |
2286 | { INDEX_op_st8_i32, { "rZ", "r" } }, | |
2287 | { INDEX_op_st16_i32, { "rZ", "r" } }, | |
2288 | { INDEX_op_st_i32, { "rZ", "r" } }, | |
2289 | ||
8642088a | 2290 | { INDEX_op_add_i32, { "r", "rZ", "rI" } }, |
477ba620 AJ |
2291 | { INDEX_op_sub_i32, { "r", "rI", "rI" } }, |
2292 | ||
2293 | { INDEX_op_and_i32, { "r", "rI", "rI" } }, | |
2294 | { INDEX_op_andc_i32, { "r", "rI", "rI" } }, | |
2295 | { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } }, | |
2296 | { INDEX_op_nand_i32, { "r", "rZ", "rZ" } }, | |
2297 | { INDEX_op_nor_i32, { "r", "rZ", "rZ" } }, | |
2298 | { INDEX_op_or_i32, { "r", "rI", "rI" } }, | |
2299 | { INDEX_op_orc_i32, { "r", "rZ", "rZ" } }, | |
2300 | { INDEX_op_xor_i32, { "r", "rI", "rI" } }, | |
2301 | ||
2302 | { INDEX_op_mul_i32, { "r", "rZ", "rZ" } }, | |
2303 | ||
2304 | { INDEX_op_sar_i32, { "r", "rZ", "ri" } }, | |
2305 | { INDEX_op_shl_i32, { "r", "rZ", "ri" } }, | |
2306 | { INDEX_op_shr_i32, { "r", "rZ", "ri" } }, | |
2307 | { INDEX_op_rotl_i32, { "r", "rZ", "ri" } }, | |
2308 | { INDEX_op_rotr_i32, { "r", "rZ", "ri" } }, | |
2309 | ||
2310 | { INDEX_op_ext8s_i32, { "r", "rZ"} }, | |
2311 | { INDEX_op_ext8u_i32, { "r", "rZ"} }, | |
2312 | { INDEX_op_ext16s_i32, { "r", "rZ"} }, | |
2313 | { INDEX_op_ext16u_i32, { "r", "rZ"} }, | |
2314 | ||
2315 | { INDEX_op_bswap16_i32, { "r", "rZ" } }, | |
2316 | { INDEX_op_bswap32_i32, { "r", "rZ" } }, | |
2317 | ||
6d264b38 | 2318 | { INDEX_op_brcond_i32, { "rZ", "rZ" } }, |
477ba620 | 2319 | { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } }, |
b90cf716 | 2320 | { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } }, |
477ba620 AJ |
2321 | |
2322 | { INDEX_op_mov_i64, { "r", "r" } }, | |
2323 | { INDEX_op_movi_i64, { "r" } }, | |
2324 | ||
2325 | { INDEX_op_ld8u_i64, { "r", "r" } }, | |
2326 | { INDEX_op_ld8s_i64, { "r", "r" } }, | |
2327 | { INDEX_op_ld16u_i64, { "r", "r" } }, | |
2328 | { INDEX_op_ld16s_i64, { "r", "r" } }, | |
2329 | { INDEX_op_ld32u_i64, { "r", "r" } }, | |
2330 | { INDEX_op_ld32s_i64, { "r", "r" } }, | |
2331 | { INDEX_op_ld_i64, { "r", "r" } }, | |
2332 | { INDEX_op_st8_i64, { "rZ", "r" } }, | |
2333 | { INDEX_op_st16_i64, { "rZ", "r" } }, | |
2334 | { INDEX_op_st32_i64, { "rZ", "r" } }, | |
2335 | { INDEX_op_st_i64, { "rZ", "r" } }, | |
2336 | ||
8642088a | 2337 | { INDEX_op_add_i64, { "r", "rZ", "rI" } }, |
477ba620 AJ |
2338 | { INDEX_op_sub_i64, { "r", "rI", "rI" } }, |
2339 | ||
2340 | { INDEX_op_and_i64, { "r", "rI", "rI" } }, | |
2341 | { INDEX_op_andc_i64, { "r", "rI", "rI" } }, | |
2342 | { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } }, | |
2343 | { INDEX_op_nand_i64, { "r", "rZ", "rZ" } }, | |
2344 | { INDEX_op_nor_i64, { "r", "rZ", "rZ" } }, | |
2345 | { INDEX_op_or_i64, { "r", "rI", "rI" } }, | |
2346 | { INDEX_op_orc_i64, { "r", "rZ", "rZ" } }, | |
2347 | { INDEX_op_xor_i64, { "r", "rI", "rI" } }, | |
2348 | ||
2349 | { INDEX_op_mul_i64, { "r", "rZ", "rZ" } }, | |
2350 | ||
2351 | { INDEX_op_sar_i64, { "r", "rZ", "ri" } }, | |
2352 | { INDEX_op_shl_i64, { "r", "rZ", "ri" } }, | |
2353 | { INDEX_op_shr_i64, { "r", "rZ", "ri" } }, | |
2354 | { INDEX_op_rotl_i64, { "r", "rZ", "ri" } }, | |
2355 | { INDEX_op_rotr_i64, { "r", "rZ", "ri" } }, | |
2356 | ||
2357 | { INDEX_op_ext8s_i64, { "r", "rZ"} }, | |
2358 | { INDEX_op_ext8u_i64, { "r", "rZ"} }, | |
2359 | { INDEX_op_ext16s_i64, { "r", "rZ"} }, | |
2360 | { INDEX_op_ext16u_i64, { "r", "rZ"} }, | |
2361 | { INDEX_op_ext32s_i64, { "r", "rZ"} }, | |
2362 | { INDEX_op_ext32u_i64, { "r", "rZ"} }, | |
2363 | ||
2364 | { INDEX_op_bswap16_i64, { "r", "rZ" } }, | |
2365 | { INDEX_op_bswap32_i64, { "r", "rZ" } }, | |
2366 | { INDEX_op_bswap64_i64, { "r", "rZ" } }, | |
2367 | ||
6d264b38 | 2368 | { INDEX_op_brcond_i64, { "rZ", "rZ" } }, |
477ba620 | 2369 | { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } }, |
b90cf716 | 2370 | { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } }, |
477ba620 | 2371 | |
c7d4475a RH |
2372 | { INDEX_op_deposit_i32, { "r", "rZ", "ri" } }, |
2373 | { INDEX_op_deposit_i64, { "r", "rZ", "ri" } }, | |
2374 | ||
477ba620 AJ |
2375 | { INDEX_op_qemu_ld8u, { "r", "r" } }, |
2376 | { INDEX_op_qemu_ld8s, { "r", "r" } }, | |
2377 | { INDEX_op_qemu_ld16u, { "r", "r" } }, | |
2378 | { INDEX_op_qemu_ld16s, { "r", "r" } }, | |
2379 | { INDEX_op_qemu_ld32, { "r", "r" } }, | |
2380 | { INDEX_op_qemu_ld32u, { "r", "r" } }, | |
2381 | { INDEX_op_qemu_ld32s, { "r", "r" } }, | |
2382 | { INDEX_op_qemu_ld64, { "r", "r" } }, | |
2383 | ||
2384 | { INDEX_op_qemu_st8, { "SZ", "r" } }, | |
2385 | { INDEX_op_qemu_st16, { "SZ", "r" } }, | |
2386 | { INDEX_op_qemu_st32, { "SZ", "r" } }, | |
2387 | { INDEX_op_qemu_st64, { "SZ", "r" } }, | |
2388 | ||
2389 | { -1 }, | |
2390 | }; | |
2391 | ||
2392 | /* Generate global QEMU prologue and epilogue code */ | |
e4d58b41 | 2393 | static void tcg_target_qemu_prologue(TCGContext *s) |
477ba620 AJ |
2394 | { |
2395 | int frame_size; | |
2396 | ||
2397 | /* reserve some stack space */ | |
da897bf5 BS |
2398 | frame_size = TCG_STATIC_CALL_ARGS_SIZE + |
2399 | CPU_TEMP_BUF_NLONGS * sizeof(long); | |
477ba620 AJ |
2400 | frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) & |
2401 | ~(TCG_TARGET_STACK_ALIGN - 1); | |
da897bf5 BS |
2402 | tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, |
2403 | CPU_TEMP_BUF_NLONGS * sizeof(long)); | |
477ba620 AJ |
2404 | |
2405 | /* First emit adhoc function descriptor */ | |
2406 | *(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */ | |
2407 | s->code_ptr += 16; /* skip GP */ | |
2408 | ||
2409 | /* prologue */ | |
18d445b4 | 2410 | tcg_out_bundle(s, miI, |
477ba620 | 2411 | tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34, |
18d445b4 | 2412 | TCG_REG_R34, 32, 24, 0), |
d15de15c | 2413 | INSN_NOP_I, |
477ba620 | 2414 | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, |
18d445b4 | 2415 | TCG_REG_B6, TCG_REG_R33, 0)); |
6781d08d RH |
2416 | |
2417 | /* ??? If GUEST_BASE < 0x200000, we could load the register via | |
2418 | an ADDL in the M slot of the next bundle. */ | |
2419 | if (GUEST_BASE != 0) { | |
2420 | tcg_out_bundle(s, mlx, | |
5f7b1687 | 2421 | INSN_NOP_M, |
6781d08d RH |
2422 | tcg_opc_l2 (GUEST_BASE), |
2423 | tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, | |
2424 | TCG_GUEST_BASE_REG, GUEST_BASE)); | |
2425 | tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); | |
2426 | } | |
2427 | ||
477ba620 | 2428 | tcg_out_bundle(s, miB, |
477ba620 AJ |
2429 | tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, |
2430 | TCG_REG_R12, -frame_size, TCG_REG_R12), | |
18d445b4 | 2431 | tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22, |
d15de15c | 2432 | TCG_REG_R33, TCG_REG_B0), |
477ba620 AJ |
2433 | tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6)); |
2434 | ||
2435 | /* epilogue */ | |
2436 | tb_ret_addr = s->code_ptr; | |
2437 | tcg_out_bundle(s, miI, | |
5f7b1687 | 2438 | INSN_NOP_M, |
477ba620 | 2439 | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, |
d15de15c | 2440 | TCG_REG_B0, TCG_REG_R33, 0), |
477ba620 AJ |
2441 | tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, |
2442 | TCG_REG_R12, frame_size, TCG_REG_R12)); | |
2443 | tcg_out_bundle(s, miB, | |
5f7b1687 | 2444 | INSN_NOP_M, |
477ba620 | 2445 | tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26, |
18d445b4 | 2446 | TCG_REG_PFS, TCG_REG_R34), |
477ba620 AJ |
2447 | tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4, |
2448 | TCG_REG_B0)); | |
2449 | } | |
2450 | ||
e4d58b41 | 2451 | static void tcg_target_init(TCGContext *s) |
477ba620 AJ |
2452 | { |
2453 | tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], | |
2454 | 0xffffffffffffffffull); | |
2455 | tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64], | |
2456 | 0xffffffffffffffffull); | |
477ba620 | 2457 | |
7221f058 RH |
2458 | tcg_regset_clear(tcg_target_call_clobber_regs); |
2459 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); | |
2460 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); | |
2461 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); | |
2462 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); | |
2463 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); | |
2464 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15); | |
2465 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16); | |
2466 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17); | |
2467 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18); | |
2468 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19); | |
2469 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20); | |
2470 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21); | |
2471 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22); | |
2472 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23); | |
2473 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24); | |
2474 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25); | |
2475 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26); | |
2476 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27); | |
2477 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28); | |
2478 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29); | |
2479 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30); | |
2480 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31); | |
2481 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56); | |
2482 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57); | |
2483 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58); | |
2484 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59); | |
2485 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60); | |
2486 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61); | |
2487 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62); | |
2488 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63); | |
2489 | ||
2490 | tcg_regset_clear(s->reserved_regs); | |
477ba620 AJ |
2491 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */ |
2492 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */ | |
2493 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */ | |
2494 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */ | |
2495 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */ | |
7221f058 | 2496 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ |
d15de15c | 2497 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R33); /* return address */ |
18d445b4 | 2498 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R34); /* PFS */ |
477ba620 | 2499 | |
d15de15c | 2500 | /* The following 4 are not in use, are call-saved, but *not* saved |
7221f058 RH |
2501 | by the prologue. Therefore we cannot use them without modifying |
2502 | the prologue. There doesn't seem to be any good reason to use | |
2503 | these as opposed to the windowed registers. */ | |
2504 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4); | |
2505 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5); | |
2506 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6); | |
d15de15c | 2507 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R7); |
7221f058 | 2508 | |
477ba620 AJ |
2509 | tcg_add_target_add_op_defs(ia64_op_defs); |
2510 | } |