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7316329a SW |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2009, 2011 Stefan Weil | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | /* | |
26 | * This code implements a TCG which does not generate machine code for some | |
27 | * real target machine but which generates virtual machine code for an | |
28 | * interpreter. Interpreted pseudo code is slow, but it works on any host. | |
29 | * | |
30 | * Some remarks might help in understanding the code: | |
31 | * | |
32 | * "target" or "TCG target" is the machine which runs the generated code. | |
33 | * This is different to the usual meaning in QEMU where "target" is the | |
34 | * emulated machine. So normally QEMU host is identical to TCG target. | |
35 | * Here the TCG target is a virtual machine, but this virtual machine must | |
36 | * use the same word size like the real machine. | |
37 | * Therefore, we need both 32 and 64 bit virtual machines (interpreter). | |
38 | */ | |
39 | ||
40 | #if !defined(TCG_TARGET_H) | |
41 | #define TCG_TARGET_H | |
42 | ||
43 | #include "config-host.h" | |
44 | ||
45 | #define TCG_TARGET_INTERPRETER 1 | |
46 | ||
47 | #ifdef CONFIG_DEBUG_TCG | |
48 | /* Enable debug output. */ | |
49 | #define CONFIG_DEBUG_TCG_INTERPRETER | |
50 | #endif | |
51 | ||
52 | #if 0 /* TCI tries to emulate a little endian host. */ | |
53 | #if defined(HOST_WORDS_BIGENDIAN) | |
54 | # define TCG_TARGET_WORDS_BIGENDIAN | |
55 | #endif | |
56 | #endif | |
57 | ||
58 | /* Optional instructions. */ | |
59 | ||
60 | #define TCG_TARGET_HAS_bswap16_i32 1 | |
61 | #define TCG_TARGET_HAS_bswap32_i32 1 | |
7316329a | 62 | #define TCG_TARGET_HAS_div_i32 1 |
ca675f46 | 63 | #define TCG_TARGET_HAS_rem_i32 1 |
7316329a SW |
64 | #define TCG_TARGET_HAS_ext8s_i32 1 |
65 | #define TCG_TARGET_HAS_ext16s_i32 1 | |
66 | #define TCG_TARGET_HAS_ext8u_i32 1 | |
67 | #define TCG_TARGET_HAS_ext16u_i32 1 | |
68 | #define TCG_TARGET_HAS_andc_i32 0 | |
e24dc9fe | 69 | #define TCG_TARGET_HAS_deposit_i32 1 |
7316329a SW |
70 | #define TCG_TARGET_HAS_eqv_i32 0 |
71 | #define TCG_TARGET_HAS_nand_i32 0 | |
72 | #define TCG_TARGET_HAS_nor_i32 0 | |
73 | #define TCG_TARGET_HAS_neg_i32 1 | |
74 | #define TCG_TARGET_HAS_not_i32 1 | |
75 | #define TCG_TARGET_HAS_orc_i32 0 | |
76 | #define TCG_TARGET_HAS_rot_i32 1 | |
ffc5ea09 | 77 | #define TCG_TARGET_HAS_movcond_i32 0 |
4d3203fd | 78 | #define TCG_TARGET_HAS_muls2_i32 0 |
03271524 RH |
79 | #define TCG_TARGET_HAS_muluh_i32 0 |
80 | #define TCG_TARGET_HAS_mulsh_i32 0 | |
7316329a SW |
81 | |
82 | #if TCG_TARGET_REG_BITS == 64 | |
83 | #define TCG_TARGET_HAS_bswap16_i64 1 | |
84 | #define TCG_TARGET_HAS_bswap32_i64 1 | |
85 | #define TCG_TARGET_HAS_bswap64_i64 1 | |
e24dc9fe | 86 | #define TCG_TARGET_HAS_deposit_i64 1 |
7316329a | 87 | #define TCG_TARGET_HAS_div_i64 0 |
ca675f46 | 88 | #define TCG_TARGET_HAS_rem_i64 0 |
7316329a SW |
89 | #define TCG_TARGET_HAS_ext8s_i64 1 |
90 | #define TCG_TARGET_HAS_ext16s_i64 1 | |
91 | #define TCG_TARGET_HAS_ext32s_i64 1 | |
92 | #define TCG_TARGET_HAS_ext8u_i64 1 | |
93 | #define TCG_TARGET_HAS_ext16u_i64 1 | |
94 | #define TCG_TARGET_HAS_ext32u_i64 1 | |
95 | #define TCG_TARGET_HAS_andc_i64 0 | |
96 | #define TCG_TARGET_HAS_eqv_i64 0 | |
97 | #define TCG_TARGET_HAS_nand_i64 0 | |
98 | #define TCG_TARGET_HAS_nor_i64 0 | |
99 | #define TCG_TARGET_HAS_neg_i64 1 | |
100 | #define TCG_TARGET_HAS_not_i64 1 | |
101 | #define TCG_TARGET_HAS_orc_i64 0 | |
102 | #define TCG_TARGET_HAS_rot_i64 1 | |
ffc5ea09 | 103 | #define TCG_TARGET_HAS_movcond_i64 0 |
4d3203fd | 104 | #define TCG_TARGET_HAS_muls2_i64 0 |
e6a72734 RH |
105 | #define TCG_TARGET_HAS_add2_i32 0 |
106 | #define TCG_TARGET_HAS_sub2_i32 0 | |
107 | #define TCG_TARGET_HAS_mulu2_i32 0 | |
d7156f7c RH |
108 | #define TCG_TARGET_HAS_add2_i64 0 |
109 | #define TCG_TARGET_HAS_sub2_i64 0 | |
110 | #define TCG_TARGET_HAS_mulu2_i64 0 | |
03271524 RH |
111 | #define TCG_TARGET_HAS_muluh_i64 0 |
112 | #define TCG_TARGET_HAS_mulsh_i64 0 | |
7316329a SW |
113 | #endif /* TCG_TARGET_REG_BITS == 64 */ |
114 | ||
7316329a SW |
115 | /* Number of registers available. |
116 | For 32 bit hosts, we need more than 8 registers (call arguments). */ | |
117 | /* #define TCG_TARGET_NB_REGS 8 */ | |
118 | #define TCG_TARGET_NB_REGS 16 | |
119 | /* #define TCG_TARGET_NB_REGS 32 */ | |
120 | ||
121 | /* List of registers which are used by TCG. */ | |
122 | typedef enum { | |
123 | TCG_REG_R0 = 0, | |
124 | TCG_REG_R1, | |
125 | TCG_REG_R2, | |
126 | TCG_REG_R3, | |
127 | TCG_REG_R4, | |
128 | TCG_REG_R5, | |
129 | TCG_REG_R6, | |
130 | TCG_REG_R7, | |
7316329a SW |
131 | #if TCG_TARGET_NB_REGS >= 16 |
132 | TCG_REG_R8, | |
133 | TCG_REG_R9, | |
134 | TCG_REG_R10, | |
135 | TCG_REG_R11, | |
136 | TCG_REG_R12, | |
137 | TCG_REG_R13, | |
138 | TCG_REG_R14, | |
139 | TCG_REG_R15, | |
140 | #if TCG_TARGET_NB_REGS >= 32 | |
141 | TCG_REG_R16, | |
142 | TCG_REG_R17, | |
143 | TCG_REG_R18, | |
144 | TCG_REG_R19, | |
145 | TCG_REG_R20, | |
146 | TCG_REG_R21, | |
147 | TCG_REG_R22, | |
148 | TCG_REG_R23, | |
149 | TCG_REG_R24, | |
150 | TCG_REG_R25, | |
151 | TCG_REG_R26, | |
152 | TCG_REG_R27, | |
153 | TCG_REG_R28, | |
154 | TCG_REG_R29, | |
155 | TCG_REG_R30, | |
156 | TCG_REG_R31, | |
157 | #endif | |
158 | #endif | |
159 | /* Special value UINT8_MAX is used by TCI to encode constant values. */ | |
160 | TCG_CONST = UINT8_MAX | |
771142c2 | 161 | } TCGReg; |
7316329a | 162 | |
ee79c356 RH |
163 | #define TCG_AREG0 (TCG_TARGET_NB_REGS - 2) |
164 | ||
165 | /* Used for function call generation. */ | |
166 | #define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1) | |
167 | #define TCG_TARGET_CALL_STACK_OFFSET 0 | |
168 | #define TCG_TARGET_STACK_ALIGN 16 | |
169 | ||
7316329a SW |
170 | void tci_disas(uint8_t opc); |
171 | ||
04d5a1da | 172 | uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); |
7316329a SW |
173 | #define tcg_qemu_tb_exec tcg_qemu_tb_exec |
174 | ||
b93949ef | 175 | static inline void flush_icache_range(uintptr_t start, uintptr_t stop) |
51711aee SW |
176 | { |
177 | } | |
178 | ||
7316329a | 179 | #endif /* TCG_TARGET_H */ |