[qemu.git] / tests / ide-test.c

/*
 * IDE test cases
 *
 * Copyright (c) 2013 Kevin Wolf <kwolf@redhat.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include <stdint.h>
#include <string.h>
#include <stdio.h>

#include <glib.h>

#include "libqtest.h"
#include "libqos/pci-pc.h"
#include "libqos/malloc-pc.h"

#include "qemu-common.h"
#include "hw/pci/pci_ids.h"
#include "hw/pci/pci_regs.h"

#define TEST_IMAGE_SIZE 64 * 1024 * 1024

#define IDE_PCI_DEV     1
#define IDE_PCI_FUNC    1

#define IDE_BASE 0x1f0
#define IDE_PRIMARY_IRQ 14

enum {
    reg_data        = 0x0,
    reg_nsectors    = 0x2,
    reg_lba_low     = 0x3,
    reg_lba_middle  = 0x4,
    reg_lba_high    = 0x5,
    reg_device      = 0x6,
    reg_status      = 0x7,
    reg_command     = 0x7,
};

enum {
    BSY     = 0x80,
    DRDY    = 0x40,
    DF      = 0x20,
    DRQ     = 0x08,
    ERR     = 0x01,
};

enum {
    DEV     = 0x10,
    LBA     = 0x40,
};

enum {
    bmreg_cmd       = 0x0,
    bmreg_status    = 0x2,
    bmreg_prdt      = 0x4,
};

enum {
    CMD_READ_DMA    = 0xc8,
    CMD_WRITE_DMA   = 0xca,
    CMD_FLUSH_CACHE = 0xe7,
    CMD_IDENTIFY    = 0xec,

    CMDF_ABORT      = 0x100,
    CMDF_NO_BM      = 0x200,
};

enum {
    BM_CMD_START    =  0x1,
    BM_CMD_WRITE    =  0x8, /* write = from device to memory */
};

enum {
    BM_STS_ACTIVE   =  0x1,
    BM_STS_ERROR    =  0x2,
    BM_STS_INTR     =  0x4,
};

enum {
    PRDT_EOT        = 0x80000000,
};

#define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
#define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)

static QPCIBus *pcibus = NULL;
static QGuestAllocator *guest_malloc;

static char tmp_path[] = "/tmp/qtest.XXXXXX";

static void ide_test_start(const char *cmdline_fmt, ...)
{
    va_list ap;
    char *cmdline;

    va_start(ap, cmdline_fmt);
    cmdline = g_strdup_vprintf(cmdline_fmt, ap);
    va_end(ap);

    qtest_start(cmdline);
    qtest_irq_intercept_in(global_qtest, "ioapic");
    guest_malloc = pc_alloc_init();
}

static void ide_test_quit(void)
{
    qtest_end();
}

static QPCIDevice *get_pci_device(uint16_t *bmdma_base)
{
    QPCIDevice *dev;
    uint16_t vendor_id, device_id;

    if (!pcibus) {
        pcibus = qpci_init_pc();
    }

    /* Find PCI device and verify it's the right one */
    dev = qpci_device_find(pcibus, QPCI_DEVFN(IDE_PCI_DEV, IDE_PCI_FUNC));
    g_assert(dev != NULL);

    vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID);
    device_id = qpci_config_readw(dev, PCI_DEVICE_ID);
    g_assert(vendor_id == PCI_VENDOR_ID_INTEL);
    g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1);

    /* Map bmdma BAR */
    *bmdma_base = (uint16_t)(uintptr_t) qpci_iomap(dev, 4);

    qpci_device_enable(dev);

    return dev;
}

static void free_pci_device(QPCIDevice *dev)
{
    /* libqos doesn't have a function for this, so free it manually */
    g_free(dev);
}

typedef struct PrdtEntry {
    uint32_t addr;
    uint32_t size;
} QEMU_PACKED PrdtEntry;

#define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
#define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)

static int send_dma_request(int cmd, uint64_t sector, int nb_sectors,
                            PrdtEntry *prdt, int prdt_entries)
{
    QPCIDevice *dev;
    uint16_t bmdma_base;
    uintptr_t guest_prdt;
    size_t len;
    bool from_dev;
    uint8_t status;
    int flags;

    dev = get_pci_device(&bmdma_base);

    flags = cmd & ~0xff;
    cmd &= 0xff;

    switch (cmd) {
    case CMD_READ_DMA:
        from_dev = true;
        break;
    case CMD_WRITE_DMA:
        from_dev = false;
        break;
    default:
        g_assert_not_reached();
    }

    if (flags & CMDF_NO_BM) {
        qpci_config_writew(dev, PCI_COMMAND,
                           PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
    }

    /* Select device 0 */
    outb(IDE_BASE + reg_device, 0 | LBA);

    /* Stop any running transfer, clear any pending interrupt */
    outb(bmdma_base + bmreg_cmd, 0);
    outb(bmdma_base + bmreg_status, BM_STS_INTR);

    /* Setup PRDT */
    len = sizeof(*prdt) * prdt_entries;
    guest_prdt = guest_alloc(guest_malloc, len);
    memwrite(guest_prdt, prdt, len);
    outl(bmdma_base + bmreg_prdt, guest_prdt);

    /* ATA DMA command */
    outb(IDE_BASE + reg_nsectors, nb_sectors);

    outb(IDE_BASE + reg_lba_low,    sector & 0xff);
    outb(IDE_BASE + reg_lba_middle, (sector >> 8) & 0xff);
    outb(IDE_BASE + reg_lba_high,   (sector >> 16) & 0xff);

    outb(IDE_BASE + reg_command, cmd);

    /* Start DMA transfer */
    outb(bmdma_base + bmreg_cmd, BM_CMD_START | (from_dev ? BM_CMD_WRITE : 0));

    if (flags & CMDF_ABORT) {
        outb(bmdma_base + bmreg_cmd, 0);
    }

    /* Wait for the DMA transfer to complete */
    do {
        status = inb(bmdma_base + bmreg_status);
    } while ((status & (BM_STS_ACTIVE | BM_STS_INTR)) == BM_STS_ACTIVE);

    g_assert_cmpint(get_irq(IDE_PRIMARY_IRQ), ==, !!(status & BM_STS_INTR));

    /* Check IDE status code */
    assert_bit_set(inb(IDE_BASE + reg_status), DRDY);
    assert_bit_clear(inb(IDE_BASE + reg_status), BSY | DRQ);

    /* Reading the status register clears the IRQ */
    g_assert(!get_irq(IDE_PRIMARY_IRQ));

    /* Stop DMA transfer if still active */
    if (status & BM_STS_ACTIVE) {
        outb(bmdma_base + bmreg_cmd, 0);
    }

    free_pci_device(dev);

    return status;
}

static void test_bmdma_simple_rw(void)
{
    uint8_t status;
    uint8_t *buf;
    uint8_t *cmpbuf;
    size_t len = 512;
    uintptr_t guest_buf = guest_alloc(guest_malloc, len);

    PrdtEntry prdt[] = {
        {
            .addr = cpu_to_le32(guest_buf),
            .size = cpu_to_le32(len | PRDT_EOT),
        },
    };

    buf = g_malloc(len);
    cmpbuf = g_malloc(len);

    /* Write 0x55 pattern to sector 0 */
    memset(buf, 0x55, len);
    memwrite(guest_buf, buf, len);

    status = send_dma_request(CMD_WRITE_DMA, 0, 1, prdt, ARRAY_SIZE(prdt));
    g_assert_cmphex(status, ==, BM_STS_INTR);
    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);

    /* Write 0xaa pattern to sector 1 */
    memset(buf, 0xaa, len);
    memwrite(guest_buf, buf, len);

    status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt, ARRAY_SIZE(prdt));
    g_assert_cmphex(status, ==, BM_STS_INTR);
    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);

    /* Read and verify 0x55 pattern in sector 0 */
    memset(cmpbuf, 0x55, len);

    status = send_dma_request(CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt));
    g_assert_cmphex(status, ==, BM_STS_INTR);
    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);

    memread(guest_buf, buf, len);
    g_assert(memcmp(buf, cmpbuf, len) == 0);

    /* Read and verify 0xaa pattern in sector 1 */
    memset(cmpbuf, 0xaa, len);

    status = send_dma_request(CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt));
    g_assert_cmphex(status, ==, BM_STS_INTR);
    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);

    memread(guest_buf, buf, len);
    g_assert(memcmp(buf, cmpbuf, len) == 0);


    g_free(buf);
    g_free(cmpbuf);
}

static void test_bmdma_short_prdt(void)
{
    uint8_t status;

    PrdtEntry prdt[] = {
        {
            .addr = 0,
            .size = cpu_to_le32(0x10 | PRDT_EOT),
        },
    };

    /* Normal request */
    status = send_dma_request(CMD_READ_DMA, 0, 1,
                              prdt, ARRAY_SIZE(prdt));
    g_assert_cmphex(status, ==, 0);
    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);

    /* Abort the request before it completes */
    status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1,
                              prdt, ARRAY_SIZE(prdt));
    g_assert_cmphex(status, ==, 0);
    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
}

static void test_bmdma_long_prdt(void)
{
    uint8_t status;

    PrdtEntry prdt[] = {
        {
            .addr = 0,
            .size = cpu_to_le32(0x1000 | PRDT_EOT),
        },
    };

    /* Normal request */
    status = send_dma_request(CMD_READ_DMA, 0, 1,
                              prdt, ARRAY_SIZE(prdt));
    g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR);
    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);

    /* Abort the request before it completes */
    status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1,
                              prdt, ARRAY_SIZE(prdt));
    g_assert_cmphex(status, ==, BM_STS_INTR);
    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
}

static void test_bmdma_no_busmaster(void)
{
    uint8_t status;

    /* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be
     * able to access it anyway because the Bus Master bit in the PCI command
     * register isn't set. This is complete nonsense, but it used to be pretty
     * good at confusing and occasionally crashing qemu. */
    PrdtEntry prdt[4096] = { };

    status = send_dma_request(CMD_READ_DMA | CMDF_NO_BM, 0, 512,
                              prdt, ARRAY_SIZE(prdt));

    /* Not entirely clear what the expected result is, but this is what we get
     * in practice. At least we want to be aware of any changes. */
    g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR);
    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
}

static void test_bmdma_setup(void)
{
    ide_test_start(
        "-vnc none "
        "-drive file=%s,if=ide,serial=%s,cache=writeback "
        "-global ide-hd.ver=%s",
        tmp_path, "testdisk", "version");
}

static void test_bmdma_teardown(void)
{
    ide_test_quit();
}

static void string_cpu_to_be16(uint16_t *s, size_t bytes)
{
    g_assert((bytes & 1) == 0);
    bytes /= 2;

    while (bytes--) {
        *s = cpu_to_be16(*s);
        s++;
    }
}

static void test_identify(void)
{
    uint8_t data;
    uint16_t buf[256];
    int i;
    int ret;

    ide_test_start(
        "-vnc none "
        "-drive file=%s,if=ide,serial=%s,cache=writeback "
        "-global ide-hd.ver=%s",
        tmp_path, "testdisk", "version");

    /* IDENTIFY command on device 0*/
    outb(IDE_BASE + reg_device, 0);
    outb(IDE_BASE + reg_command, CMD_IDENTIFY);

    /* Read in the IDENTIFY buffer and check registers */
    data = inb(IDE_BASE + reg_device);
    g_assert_cmpint(data & DEV, ==, 0);

    for (i = 0; i < 256; i++) {
        data = inb(IDE_BASE + reg_status);
        assert_bit_set(data, DRDY | DRQ);
        assert_bit_clear(data, BSY | DF | ERR);

        ((uint16_t*) buf)[i] = inw(IDE_BASE + reg_data);
    }

    data = inb(IDE_BASE + reg_status);
    assert_bit_set(data, DRDY);
    assert_bit_clear(data, BSY | DF | ERR | DRQ);

    /* Check serial number/version in the buffer */
    string_cpu_to_be16(&buf[10], 20);
    ret = memcmp(&buf[10], "testdisk            ", 20);
    g_assert(ret == 0);

    string_cpu_to_be16(&buf[23], 8);
    ret = memcmp(&buf[23], "version ", 8);
    g_assert(ret == 0);

    /* Write cache enabled bit */
    assert_bit_set(buf[85], 0x20);

    ide_test_quit();
}

static void test_flush(void)
{
    uint8_t data;

    ide_test_start(
        "-vnc none "
        "-drive file=blkdebug::%s,if=ide,cache=writeback",
        tmp_path);

    /* Delay the completion of the flush request until we explicitly do it */
    qmp_discard_response("{'execute':'human-monitor-command', 'arguments': {"
                         " 'command-line':"
                         " 'qemu-io ide0-hd0 \"break flush_to_os A\"'} }");

    /* FLUSH CACHE command on device 0*/
    outb(IDE_BASE + reg_device, 0);
    outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE);

    /* Check status while request is in flight*/
    data = inb(IDE_BASE + reg_status);
    assert_bit_set(data, BSY | DRDY);
    assert_bit_clear(data, DF | ERR | DRQ);

    /* Complete the command */
    qmp_discard_response("{'execute':'human-monitor-command', 'arguments': {"
                         " 'command-line':"
                         " 'qemu-io ide0-hd0 \"resume A\"'} }");

    /* Check registers */
    data = inb(IDE_BASE + reg_device);
    g_assert_cmpint(data & DEV, ==, 0);

    do {
        data = inb(IDE_BASE + reg_status);
    } while (data & BSY);

    assert_bit_set(data, DRDY);
    assert_bit_clear(data, BSY | DF | ERR | DRQ);

    ide_test_quit();
}

int main(int argc, char **argv)
{
    const char *arch = qtest_get_arch();
    int fd;
    int ret;

    /* Check architecture */
    if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
        g_test_message("Skipping test for non-x86\n");
        return 0;
    }

    /* Create a temporary raw image */
    fd = mkstemp(tmp_path);
    g_assert(fd >= 0);
    ret = ftruncate(fd, TEST_IMAGE_SIZE);
    g_assert(ret == 0);
    close(fd);

    /* Run the tests */
    g_test_init(&argc, &argv, NULL);

    qtest_add_func("/ide/identify", test_identify);

    qtest_add_func("/ide/bmdma/setup", test_bmdma_setup);
    qtest_add_func("/ide/bmdma/simple_rw", test_bmdma_simple_rw);
    qtest_add_func("/ide/bmdma/short_prdt", test_bmdma_short_prdt);
    qtest_add_func("/ide/bmdma/long_prdt", test_bmdma_long_prdt);
    qtest_add_func("/ide/bmdma/no_busmaster", test_bmdma_no_busmaster);
    qtest_add_func("/ide/bmdma/teardown", test_bmdma_teardown);

    qtest_add_func("/ide/flush", test_flush);

    ret = g_test_run();

    /* Cleanup */
    unlink(tmp_path);

    return ret;
}
Commit	Line	Data
acbe4801 KW	1	/*
	2	* IDE test cases
	3	*
	4	* Copyright (c) 2013 Kevin Wolf <kwolf@redhat.com>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include <stdint.h>
	26	#include <string.h>
	27	#include <stdio.h>
	28
	29	#include <glib.h>
	30
	31	#include "libqtest.h"
b95739dc KW	32	#include "libqos/pci-pc.h"
b95739dc KW	33	#include "libqos/malloc-pc.h"
acbe4801 KW	34
acbe4801 KW	35	#include "qemu-common.h"
b95739dc KW	36	#include "hw/pci/pci_ids.h"
b95739dc KW	37	#include "hw/pci/pci_regs.h"
acbe4801 KW	38
	39	#define TEST_IMAGE_SIZE 64 * 1024 * 1024
	40
	41	#define IDE_PCI_DEV 1
	42	#define IDE_PCI_FUNC 1
	43
	44	#define IDE_BASE 0x1f0
	45	#define IDE_PRIMARY_IRQ 14
	46
	47	enum {
	48	reg_data = 0x0,
	49	reg_nsectors = 0x2,
	50	reg_lba_low = 0x3,
	51	reg_lba_middle = 0x4,
	52	reg_lba_high = 0x5,
	53	reg_device = 0x6,
	54	reg_status = 0x7,
	55	reg_command = 0x7,
	56	};
	57
	58	enum {
	59	BSY = 0x80,
	60	DRDY = 0x40,
	61	DF = 0x20,
	62	DRQ = 0x08,
	63	ERR = 0x01,
	64	};
	65
	66	enum {
c27d5656	67	DEV = 0x10,
b95739dc KW	68	LBA = 0x40,
	69	};
	70
	71	enum {
	72	bmreg_cmd = 0x0,
	73	bmreg_status = 0x2,
	74	bmreg_prdt = 0x4,
	75	};
	76
	77	enum {
	78	CMD_READ_DMA = 0xc8,
	79	CMD_WRITE_DMA = 0xca,
bd07684a	80	CMD_FLUSH_CACHE = 0xe7,
acbe4801	81	CMD_IDENTIFY = 0xec,
948eaed1 KW	82
948eaed1 KW	83	CMDF_ABORT = 0x100,
d7b7e580	84	CMDF_NO_BM = 0x200,
acbe4801 KW	85	};
acbe4801 KW	86
b95739dc KW	87	enum {
	88	BM_CMD_START = 0x1,
	89	BM_CMD_WRITE = 0x8, /* write = from device to memory */
	90	};
	91
	92	enum {
	93	BM_STS_ACTIVE = 0x1,
	94	BM_STS_ERROR = 0x2,
	95	BM_STS_INTR = 0x4,
	96	};
	97
	98	enum {
	99	PRDT_EOT = 0x80000000,
	100	};
	101
acbe4801 KW	102	#define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
	103	#define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
	104
b95739dc KW	105	static QPCIBus *pcibus = NULL;
	106	static QGuestAllocator *guest_malloc;
	107
acbe4801 KW	108	static char tmp_path[] = "/tmp/qtest.XXXXXX";
	109
	110	static void ide_test_start(const char *cmdline_fmt, ...)
	111	{
	112	va_list ap;
	113	char *cmdline;
	114
	115	va_start(ap, cmdline_fmt);
	116	cmdline = g_strdup_vprintf(cmdline_fmt, ap);
	117	va_end(ap);
	118
	119	qtest_start(cmdline);
	120	qtest_irq_intercept_in(global_qtest, "ioapic");
b95739dc	121	guest_malloc = pc_alloc_init();
acbe4801 KW	122	}
	123
	124	static void ide_test_quit(void)
	125	{
1d9358e6	126	qtest_end();
acbe4801 KW	127	}
acbe4801 KW	128
b95739dc KW	129	static QPCIDevice get_pci_device(uint16_t bmdma_base)
	130	{
	131	QPCIDevice *dev;
	132	uint16_t vendor_id, device_id;
	133
	134	if (!pcibus) {
	135	pcibus = qpci_init_pc();
	136	}
	137
	138	/* Find PCI device and verify it's the right one */
	139	dev = qpci_device_find(pcibus, QPCI_DEVFN(IDE_PCI_DEV, IDE_PCI_FUNC));
	140	g_assert(dev != NULL);
	141
	142	vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID);
	143	device_id = qpci_config_readw(dev, PCI_DEVICE_ID);
	144	g_assert(vendor_id == PCI_VENDOR_ID_INTEL);
	145	g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1);
	146
	147	/* Map bmdma BAR */
	148	*bmdma_base = (uint16_t)(uintptr_t) qpci_iomap(dev, 4);
	149
	150	qpci_device_enable(dev);
	151
	152	return dev;
	153	}
	154
	155	static void free_pci_device(QPCIDevice *dev)
	156	{
	157	/* libqos doesn't have a function for this, so free it manually */
	158	g_free(dev);
	159	}
	160
	161	typedef struct PrdtEntry {
	162	uint32_t addr;
	163	uint32_t size;
	164	} QEMU_PACKED PrdtEntry;
	165
	166	#define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
	167	#define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
	168
	169	static int send_dma_request(int cmd, uint64_t sector, int nb_sectors,
	170	PrdtEntry *prdt, int prdt_entries)
	171	{
	172	QPCIDevice *dev;
	173	uint16_t bmdma_base;
	174	uintptr_t guest_prdt;
	175	size_t len;
	176	bool from_dev;
	177	uint8_t status;
948eaed1	178	int flags;
b95739dc KW	179
	180	dev = get_pci_device(&bmdma_base);
	181
948eaed1 KW	182	flags = cmd & ~0xff;
	183	cmd &= 0xff;
	184
b95739dc KW	185	switch (cmd) {
	186	case CMD_READ_DMA:
	187	from_dev = true;
	188	break;
	189	case CMD_WRITE_DMA:
	190	from_dev = false;
	191	break;
	192	default:
	193	g_assert_not_reached();
	194	}
	195
d7b7e580 KW	196	if (flags & CMDF_NO_BM) {
	197	qpci_config_writew(dev, PCI_COMMAND,
	198	PCI_COMMAND_IO \| PCI_COMMAND_MEMORY);
	199	}
	200
b95739dc KW	201	/* Select device 0 */
	202	outb(IDE_BASE + reg_device, 0 \| LBA);
	203
	204	/* Stop any running transfer, clear any pending interrupt */
	205	outb(bmdma_base + bmreg_cmd, 0);
	206	outb(bmdma_base + bmreg_status, BM_STS_INTR);
	207
	208	/* Setup PRDT */
	209	len = sizeof(prdt) prdt_entries;
	210	guest_prdt = guest_alloc(guest_malloc, len);
	211	memwrite(guest_prdt, prdt, len);
	212	outl(bmdma_base + bmreg_prdt, guest_prdt);
	213
	214	/* ATA DMA command */
	215	outb(IDE_BASE + reg_nsectors, nb_sectors);
	216
	217	outb(IDE_BASE + reg_lba_low, sector & 0xff);
	218	outb(IDE_BASE + reg_lba_middle, (sector >> 8) & 0xff);
	219	outb(IDE_BASE + reg_lba_high, (sector >> 16) & 0xff);
	220
	221	outb(IDE_BASE + reg_command, cmd);
	222
	223	/* Start DMA transfer */
	224	outb(bmdma_base + bmreg_cmd, BM_CMD_START \| (from_dev ? BM_CMD_WRITE : 0));
	225
948eaed1 KW	226	if (flags & CMDF_ABORT) {
	227	outb(bmdma_base + bmreg_cmd, 0);
	228	}
	229
b95739dc KW	230	/* Wait for the DMA transfer to complete */
	231	do {
	232	status = inb(bmdma_base + bmreg_status);
	233	} while ((status & (BM_STS_ACTIVE \| BM_STS_INTR)) == BM_STS_ACTIVE);
	234
	235	g_assert_cmpint(get_irq(IDE_PRIMARY_IRQ), ==, !!(status & BM_STS_INTR));
	236
	237	/* Check IDE status code */
	238	assert_bit_set(inb(IDE_BASE + reg_status), DRDY);
	239	assert_bit_clear(inb(IDE_BASE + reg_status), BSY \| DRQ);
	240
	241	/* Reading the status register clears the IRQ */
	242	g_assert(!get_irq(IDE_PRIMARY_IRQ));
	243
	244	/* Stop DMA transfer if still active */
	245	if (status & BM_STS_ACTIVE) {
	246	outb(bmdma_base + bmreg_cmd, 0);
	247	}
	248
	249	free_pci_device(dev);
	250
	251	return status;
	252	}
	253
	254	static void test_bmdma_simple_rw(void)
	255	{
	256	uint8_t status;
	257	uint8_t *buf;
	258	uint8_t *cmpbuf;
	259	size_t len = 512;
	260	uintptr_t guest_buf = guest_alloc(guest_malloc, len);
	261
	262	PrdtEntry prdt[] = {
262f27b9 KW	263	{
	264	.addr = cpu_to_le32(guest_buf),
	265	.size = cpu_to_le32(len \| PRDT_EOT),
	266	},
b95739dc KW	267	};
	268
	269	buf = g_malloc(len);
	270	cmpbuf = g_malloc(len);
	271
	272	/* Write 0x55 pattern to sector 0 */
	273	memset(buf, 0x55, len);
	274	memwrite(guest_buf, buf, len);
	275
	276	status = send_dma_request(CMD_WRITE_DMA, 0, 1, prdt, ARRAY_SIZE(prdt));
	277	g_assert_cmphex(status, ==, BM_STS_INTR);
	278	assert_bit_clear(inb(IDE_BASE + reg_status), DF \| ERR);
	279
	280	/* Write 0xaa pattern to sector 1 */
	281	memset(buf, 0xaa, len);
	282	memwrite(guest_buf, buf, len);
	283
	284	status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt, ARRAY_SIZE(prdt));
	285	g_assert_cmphex(status, ==, BM_STS_INTR);
	286	assert_bit_clear(inb(IDE_BASE + reg_status), DF \| ERR);
	287
	288	/* Read and verify 0x55 pattern in sector 0 */
	289	memset(cmpbuf, 0x55, len);
	290
	291	status = send_dma_request(CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt));
	292	g_assert_cmphex(status, ==, BM_STS_INTR);
	293	assert_bit_clear(inb(IDE_BASE + reg_status), DF \| ERR);
	294
	295	memread(guest_buf, buf, len);
	296	g_assert(memcmp(buf, cmpbuf, len) == 0);
	297
	298	/* Read and verify 0xaa pattern in sector 1 */
	299	memset(cmpbuf, 0xaa, len);
	300
	301	status = send_dma_request(CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt));
	302	g_assert_cmphex(status, ==, BM_STS_INTR);
	303	assert_bit_clear(inb(IDE_BASE + reg_status), DF \| ERR);
	304
	305	memread(guest_buf, buf, len);
	306	g_assert(memcmp(buf, cmpbuf, len) == 0);
	307
	308
	309	g_free(buf);
	310	g_free(cmpbuf);
	311	}
	312
948eaed1 KW	313	static void test_bmdma_short_prdt(void)
	314	{
	315	uint8_t status;
	316
	317	PrdtEntry prdt[] = {
262f27b9 KW	318	{
	319	.addr = 0,
	320	.size = cpu_to_le32(0x10 \| PRDT_EOT),
	321	},
948eaed1 KW	322	};
	323
	324	/* Normal request */
	325	status = send_dma_request(CMD_READ_DMA, 0, 1,
	326	prdt, ARRAY_SIZE(prdt));
	327	g_assert_cmphex(status, ==, 0);
	328	assert_bit_clear(inb(IDE_BASE + reg_status), DF \| ERR);
	329
	330	/* Abort the request before it completes */
	331	status = send_dma_request(CMD_READ_DMA \| CMDF_ABORT, 0, 1,
	332	prdt, ARRAY_SIZE(prdt));
	333	g_assert_cmphex(status, ==, 0);
	334	assert_bit_clear(inb(IDE_BASE + reg_status), DF \| ERR);
	335	}
	336
	337	static void test_bmdma_long_prdt(void)
	338	{
	339	uint8_t status;
	340
	341	PrdtEntry prdt[] = {
262f27b9 KW	342	{
	343	.addr = 0,
	344	.size = cpu_to_le32(0x1000 \| PRDT_EOT),
	345	},
948eaed1 KW	346	};
	347
	348	/* Normal request */
	349	status = send_dma_request(CMD_READ_DMA, 0, 1,
	350	prdt, ARRAY_SIZE(prdt));
	351	g_assert_cmphex(status, ==, BM_STS_ACTIVE \| BM_STS_INTR);
	352	assert_bit_clear(inb(IDE_BASE + reg_status), DF \| ERR);
	353
	354	/* Abort the request before it completes */
	355	status = send_dma_request(CMD_READ_DMA \| CMDF_ABORT, 0, 1,
	356	prdt, ARRAY_SIZE(prdt));
	357	g_assert_cmphex(status, ==, BM_STS_INTR);
	358	assert_bit_clear(inb(IDE_BASE + reg_status), DF \| ERR);
	359	}
	360
d7b7e580 KW	361	static void test_bmdma_no_busmaster(void)
	362	{
	363	uint8_t status;
	364
	365	/* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be
	366	* able to access it anyway because the Bus Master bit in the PCI command
	367	* register isn't set. This is complete nonsense, but it used to be pretty
	368	* good at confusing and occasionally crashing qemu. */
	369	PrdtEntry prdt[4096] = { };
	370
	371	status = send_dma_request(CMD_READ_DMA \| CMDF_NO_BM, 0, 512,
	372	prdt, ARRAY_SIZE(prdt));
	373
	374	/* Not entirely clear what the expected result is, but this is what we get
	375	* in practice. At least we want to be aware of any changes. */
	376	g_assert_cmphex(status, ==, BM_STS_ACTIVE \| BM_STS_INTR);
	377	assert_bit_clear(inb(IDE_BASE + reg_status), DF \| ERR);
	378	}
	379
b95739dc KW	380	static void test_bmdma_setup(void)
	381	{
	382	ide_test_start(
	383	"-vnc none "
	384	"-drive file=%s,if=ide,serial=%s,cache=writeback "
	385	"-global ide-hd.ver=%s",
	386	tmp_path, "testdisk", "version");
	387	}
	388
	389	static void test_bmdma_teardown(void)
	390	{
	391	ide_test_quit();
	392	}
	393
262f27b9 KW	394	static void string_cpu_to_be16(uint16_t *s, size_t bytes)
	395	{
	396	g_assert((bytes & 1) == 0);
	397	bytes /= 2;
	398
	399	while (bytes--) {
	400	s = cpu_to_be16(s);
	401	s++;
	402	}
	403	}
	404
acbe4801 KW	405	static void test_identify(void)
	406	{
	407	uint8_t data;
	408	uint16_t buf[256];
	409	int i;
	410	int ret;
	411
	412	ide_test_start(
	413	"-vnc none "
	414	"-drive file=%s,if=ide,serial=%s,cache=writeback "
	415	"-global ide-hd.ver=%s",
	416	tmp_path, "testdisk", "version");
	417
	418	/* IDENTIFY command on device 0*/
	419	outb(IDE_BASE + reg_device, 0);
	420	outb(IDE_BASE + reg_command, CMD_IDENTIFY);
	421
	422	/* Read in the IDENTIFY buffer and check registers */
	423	data = inb(IDE_BASE + reg_device);
c27d5656	424	g_assert_cmpint(data & DEV, ==, 0);
acbe4801 KW	425
	426	for (i = 0; i < 256; i++) {
	427	data = inb(IDE_BASE + reg_status);
	428	assert_bit_set(data, DRDY \| DRQ);
	429	assert_bit_clear(data, BSY \| DF \| ERR);
	430
	431	((uint16_t*) buf)[i] = inw(IDE_BASE + reg_data);
	432	}
	433
	434	data = inb(IDE_BASE + reg_status);
	435	assert_bit_set(data, DRDY);
	436	assert_bit_clear(data, BSY \| DF \| ERR \| DRQ);
	437
	438	/* Check serial number/version in the buffer */
262f27b9 KW	439	string_cpu_to_be16(&buf[10], 20);
262f27b9 KW	440	ret = memcmp(&buf[10], "testdisk ", 20);
acbe4801 KW	441	g_assert(ret == 0);
acbe4801 KW	442
262f27b9 KW	443	string_cpu_to_be16(&buf[23], 8);
262f27b9 KW	444	ret = memcmp(&buf[23], "version ", 8);
acbe4801 KW	445	g_assert(ret == 0);
	446
	447	/* Write cache enabled bit */
	448	assert_bit_set(buf[85], 0x20);
	449
	450	ide_test_quit();
	451	}
	452
bd07684a KW	453	static void test_flush(void)
	454	{
	455	uint8_t data;
	456
	457	ide_test_start(
	458	"-vnc none "
	459	"-drive file=blkdebug::%s,if=ide,cache=writeback",
	460	tmp_path);
	461
	462	/* Delay the completion of the flush request until we explicitly do it */
0d1aa05e SH	463	qmp_discard_response("{'execute':'human-monitor-command', 'arguments': {"
	464	" 'command-line':"
	465	" 'qemu-io ide0-hd0 \"break flush_to_os A\"'} }");
bd07684a KW	466
	467	/* FLUSH CACHE command on device 0*/
	468	outb(IDE_BASE + reg_device, 0);
	469	outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE);
	470
	471	/* Check status while request is in flight*/
	472	data = inb(IDE_BASE + reg_status);
	473	assert_bit_set(data, BSY \| DRDY);
	474	assert_bit_clear(data, DF \| ERR \| DRQ);
	475
	476	/* Complete the command */
0d1aa05e SH	477	qmp_discard_response("{'execute':'human-monitor-command', 'arguments': {"
	478	" 'command-line':"
	479	" 'qemu-io ide0-hd0 \"resume A\"'} }");
bd07684a KW	480
	481	/* Check registers */
	482	data = inb(IDE_BASE + reg_device);
	483	g_assert_cmpint(data & DEV, ==, 0);
	484
22bfa16e MR	485	do {
	486	data = inb(IDE_BASE + reg_status);
	487	} while (data & BSY);
	488
bd07684a KW	489	assert_bit_set(data, DRDY);
	490	assert_bit_clear(data, BSY \| DF \| ERR \| DRQ);
	491
	492	ide_test_quit();
	493	}
	494
acbe4801 KW	495	int main(int argc, char **argv)
	496	{
	497	const char *arch = qtest_get_arch();
	498	int fd;
	499	int ret;
	500
	501	/* Check architecture */
	502	if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
	503	g_test_message("Skipping test for non-x86\n");
	504	return 0;
	505	}
	506
	507	/* Create a temporary raw image */
	508	fd = mkstemp(tmp_path);
	509	g_assert(fd >= 0);
	510	ret = ftruncate(fd, TEST_IMAGE_SIZE);
	511	g_assert(ret == 0);
	512	close(fd);
	513
	514	/* Run the tests */
	515	g_test_init(&argc, &argv, NULL);
	516
	517	qtest_add_func("/ide/identify", test_identify);
	518
b95739dc KW	519	qtest_add_func("/ide/bmdma/setup", test_bmdma_setup);
b95739dc KW	520	qtest_add_func("/ide/bmdma/simple_rw", test_bmdma_simple_rw);
948eaed1 KW	521	qtest_add_func("/ide/bmdma/short_prdt", test_bmdma_short_prdt);
948eaed1 KW	522	qtest_add_func("/ide/bmdma/long_prdt", test_bmdma_long_prdt);
d7b7e580	523	qtest_add_func("/ide/bmdma/no_busmaster", test_bmdma_no_busmaster);
b95739dc KW	524	qtest_add_func("/ide/bmdma/teardown", test_bmdma_teardown);
b95739dc KW	525
bd07684a KW	526	qtest_add_func("/ide/flush", test_flush);
bd07684a KW	527
acbe4801 KW	528	ret = g_test_run();
	529
	530	/* Cleanup */
	531	unlink(tmp_path);
	532
	533	return ret;
	534	}