]> git.proxmox.com Git - qemu.git/blame - translate-all.c
update VERSION for 1.1.2
[qemu.git] / translate-all.c
CommitLineData
d19893da
FB
1/*
2 * Host code generation
5fafdf24 3 *
d19893da
FB
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
d19893da
FB
18 */
19#include <stdarg.h>
20#include <stdlib.h>
21#include <stdio.h>
22#include <string.h>
23#include <inttypes.h>
24
25#include "config.h"
2054396a 26
af5ad107 27#define NO_CPU_IO_DEFS
d3eead2e 28#include "cpu.h"
d19893da 29#include "disas.h"
57fec1fe 30#include "tcg.h"
29e922b6 31#include "qemu-timer.h"
d19893da 32
57fec1fe
FB
33/* code generation context */
34TCGContext tcg_ctx;
d19893da 35
d19893da 36uint16_t gen_opc_buf[OPC_BUF_SIZE];
57fec1fe 37TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE];
c4687878
FB
38
39target_ulong gen_opc_pc[OPC_BUF_SIZE];
2e70f6ef 40uint16_t gen_opc_icount[OPC_BUF_SIZE];
d19893da 41uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
d19893da 42
57fec1fe
FB
43void cpu_gen_init(void)
44{
45 tcg_context_init(&tcg_ctx);
57fec1fe
FB
46}
47
d19893da 48/* return non zero if the very first instruction is invalid so that
5fafdf24 49 the virtual CPU can trigger an exception.
d19893da
FB
50
51 '*gen_code_size_ptr' contains the size of the generated code (host
52 code).
53*/
9349b4f9 54int cpu_gen_code(CPUArchState *env, TranslationBlock *tb, int *gen_code_size_ptr)
d19893da 55{
57fec1fe 56 TCGContext *s = &tcg_ctx;
d19893da
FB
57 uint8_t *gen_code_buf;
58 int gen_code_size;
57fec1fe
FB
59#ifdef CONFIG_PROFILER
60 int64_t ti;
61#endif
62
63#ifdef CONFIG_PROFILER
b67d9a52
FB
64 s->tb_count1++; /* includes aborted translations because of
65 exceptions */
57fec1fe
FB
66 ti = profile_getclock();
67#endif
68 tcg_func_start(s);
d19893da 69
2cfc5f17
TS
70 gen_intermediate_code(env, tb);
71
ec6338ba 72 /* generate machine code */
57fec1fe 73 gen_code_buf = tb->tc_ptr;
ec6338ba
FB
74 tb->tb_next_offset[0] = 0xffff;
75 tb->tb_next_offset[1] = 0xffff;
57fec1fe 76 s->tb_next_offset = tb->tb_next_offset;
4cbb86e1 77#ifdef USE_DIRECT_JUMP
57fec1fe
FB
78 s->tb_jmp_offset = tb->tb_jmp_offset;
79 s->tb_next = NULL;
d19893da 80#else
57fec1fe
FB
81 s->tb_jmp_offset = NULL;
82 s->tb_next = tb->tb_next;
d19893da 83#endif
57fec1fe
FB
84
85#ifdef CONFIG_PROFILER
b67d9a52
FB
86 s->tb_count++;
87 s->interm_time += profile_getclock() - ti;
88 s->code_time -= profile_getclock();
57fec1fe 89#endif
54604f74 90 gen_code_size = tcg_gen_code(s, gen_code_buf);
d19893da 91 *gen_code_size_ptr = gen_code_size;
57fec1fe 92#ifdef CONFIG_PROFILER
b67d9a52
FB
93 s->code_time += profile_getclock();
94 s->code_in_len += tb->size;
95 s->code_out_len += gen_code_size;
57fec1fe
FB
96#endif
97
d19893da 98#ifdef DEBUG_DISAS
8fec2b8c 99 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
93fcfe39
AL
100 qemu_log("OUT: [size=%d]\n", *gen_code_size_ptr);
101 log_disas(tb->tc_ptr, *gen_code_size_ptr);
102 qemu_log("\n");
31b1a7b4 103 qemu_log_flush();
d19893da
FB
104 }
105#endif
106 return 0;
107}
108
5fafdf24 109/* The cpu state corresponding to 'searched_pc' is restored.
d19893da 110 */
5fafdf24 111int cpu_restore_state(TranslationBlock *tb,
6375e09e 112 CPUArchState *env, uintptr_t searched_pc)
d19893da 113{
57fec1fe
FB
114 TCGContext *s = &tcg_ctx;
115 int j;
6375e09e 116 uintptr_t tc_ptr;
57fec1fe
FB
117#ifdef CONFIG_PROFILER
118 int64_t ti;
119#endif
120
121#ifdef CONFIG_PROFILER
122 ti = profile_getclock();
123#endif
124 tcg_func_start(s);
d19893da 125
2cfc5f17 126 gen_intermediate_code_pc(env, tb);
3b46e624 127
2e70f6ef
PB
128 if (use_icount) {
129 /* Reset the cycle counter to the start of the block. */
130 env->icount_decr.u16.low += tb->icount;
131 /* Clear the IO flag. */
132 env->can_do_io = 0;
133 }
134
d19893da 135 /* find opc index corresponding to search_pc */
6375e09e 136 tc_ptr = (uintptr_t)tb->tc_ptr;
d19893da
FB
137 if (searched_pc < tc_ptr)
138 return -1;
57fec1fe
FB
139
140 s->tb_next_offset = tb->tb_next_offset;
141#ifdef USE_DIRECT_JUMP
142 s->tb_jmp_offset = tb->tb_jmp_offset;
143 s->tb_next = NULL;
144#else
145 s->tb_jmp_offset = NULL;
146 s->tb_next = tb->tb_next;
147#endif
54604f74 148 j = tcg_gen_code_search_pc(s, (uint8_t *)tc_ptr, searched_pc - tc_ptr);
57fec1fe
FB
149 if (j < 0)
150 return -1;
d19893da
FB
151 /* now find start of instruction before */
152 while (gen_opc_instr_start[j] == 0)
153 j--;
2e70f6ef 154 env->icount_decr.u16.low -= gen_opc_icount[j];
3b46e624 155
e87b7cb0 156 restore_state_to_opc(env, tb, j);
57fec1fe
FB
157
158#ifdef CONFIG_PROFILER
b67d9a52
FB
159 s->restore_time += profile_getclock() - ti;
160 s->restore_count++;
57fec1fe 161#endif
d19893da
FB
162 return 0;
163}