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[qemu.git] / hw / arm / pxa2xx.c
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "hw/sysbus.h"
11 #include "hw/arm/pxa.h"
12 #include "sysemu/sysemu.h"
13 #include "hw/char/serial.h"
14 #include "hw/i2c/i2c.h"
15 #include "hw/ssi.h"
16 #include "sysemu/char.h"
17 #include "sysemu/blockdev.h"
18
19 static struct {
20 hwaddr io_base;
21 int irqn;
22 } pxa255_serial[] = {
23 { 0x40100000, PXA2XX_PIC_FFUART },
24 { 0x40200000, PXA2XX_PIC_BTUART },
25 { 0x40700000, PXA2XX_PIC_STUART },
26 { 0x41600000, PXA25X_PIC_HWUART },
27 { 0, 0 }
28 }, pxa270_serial[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART },
30 { 0x40200000, PXA2XX_PIC_BTUART },
31 { 0x40700000, PXA2XX_PIC_STUART },
32 { 0, 0 }
33 };
34
35 typedef struct PXASSPDef {
36 hwaddr io_base;
37 int irqn;
38 } PXASSPDef;
39
40 #if 0
41 static PXASSPDef pxa250_ssp[] = {
42 { 0x41000000, PXA2XX_PIC_SSP },
43 { 0, 0 }
44 };
45 #endif
46
47 static PXASSPDef pxa255_ssp[] = {
48 { 0x41000000, PXA2XX_PIC_SSP },
49 { 0x41400000, PXA25X_PIC_NSSP },
50 { 0, 0 }
51 };
52
53 #if 0
54 static PXASSPDef pxa26x_ssp[] = {
55 { 0x41000000, PXA2XX_PIC_SSP },
56 { 0x41400000, PXA25X_PIC_NSSP },
57 { 0x41500000, PXA26X_PIC_ASSP },
58 { 0, 0 }
59 };
60 #endif
61
62 static PXASSPDef pxa27x_ssp[] = {
63 { 0x41000000, PXA2XX_PIC_SSP },
64 { 0x41700000, PXA27X_PIC_SSP2 },
65 { 0x41900000, PXA2XX_PIC_SSP3 },
66 { 0, 0 }
67 };
68
69 #define PMCR 0x00 /* Power Manager Control register */
70 #define PSSR 0x04 /* Power Manager Sleep Status register */
71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
76 #define PCFR 0x1c /* Power Manager General Configuration register */
77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
81 #define RCSR 0x30 /* Reset Controller Status register */
82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
83 #define PTSR 0x38 /* Power Manager Standby Configuration register */
84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
90
91 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
92 unsigned size)
93 {
94 PXA2xxState *s = (PXA2xxState *) opaque;
95
96 switch (addr) {
97 case PMCR ... PCMD31:
98 if (addr & 3)
99 goto fail;
100
101 return s->pm_regs[addr >> 2];
102 default:
103 fail:
104 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
105 break;
106 }
107 return 0;
108 }
109
110 static void pxa2xx_pm_write(void *opaque, hwaddr addr,
111 uint64_t value, unsigned size)
112 {
113 PXA2xxState *s = (PXA2xxState *) opaque;
114
115 switch (addr) {
116 case PMCR:
117 /* Clear the write-one-to-clear bits... */
118 s->pm_regs[addr >> 2] &= ~(value & 0x2a);
119 /* ...and set the plain r/w bits */
120 s->pm_regs[addr >> 2] &= ~0x15;
121 s->pm_regs[addr >> 2] |= value & 0x15;
122 break;
123
124 case PSSR: /* Read-clean registers */
125 case RCSR:
126 case PKSR:
127 s->pm_regs[addr >> 2] &= ~value;
128 break;
129
130 default: /* Read-write registers */
131 if (!(addr & 3)) {
132 s->pm_regs[addr >> 2] = value;
133 break;
134 }
135
136 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
137 break;
138 }
139 }
140
141 static const MemoryRegionOps pxa2xx_pm_ops = {
142 .read = pxa2xx_pm_read,
143 .write = pxa2xx_pm_write,
144 .endianness = DEVICE_NATIVE_ENDIAN,
145 };
146
147 static const VMStateDescription vmstate_pxa2xx_pm = {
148 .name = "pxa2xx_pm",
149 .version_id = 0,
150 .minimum_version_id = 0,
151 .minimum_version_id_old = 0,
152 .fields = (VMStateField[]) {
153 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
154 VMSTATE_END_OF_LIST()
155 }
156 };
157
158 #define CCCR 0x00 /* Core Clock Configuration register */
159 #define CKEN 0x04 /* Clock Enable register */
160 #define OSCC 0x08 /* Oscillator Configuration register */
161 #define CCSR 0x0c /* Core Clock Status register */
162
163 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
164 unsigned size)
165 {
166 PXA2xxState *s = (PXA2xxState *) opaque;
167
168 switch (addr) {
169 case CCCR:
170 case CKEN:
171 case OSCC:
172 return s->cm_regs[addr >> 2];
173
174 case CCSR:
175 return s->cm_regs[CCCR >> 2] | (3 << 28);
176
177 default:
178 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
179 break;
180 }
181 return 0;
182 }
183
184 static void pxa2xx_cm_write(void *opaque, hwaddr addr,
185 uint64_t value, unsigned size)
186 {
187 PXA2xxState *s = (PXA2xxState *) opaque;
188
189 switch (addr) {
190 case CCCR:
191 case CKEN:
192 s->cm_regs[addr >> 2] = value;
193 break;
194
195 case OSCC:
196 s->cm_regs[addr >> 2] &= ~0x6c;
197 s->cm_regs[addr >> 2] |= value & 0x6e;
198 if ((value >> 1) & 1) /* OON */
199 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
200 break;
201
202 default:
203 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
204 break;
205 }
206 }
207
208 static const MemoryRegionOps pxa2xx_cm_ops = {
209 .read = pxa2xx_cm_read,
210 .write = pxa2xx_cm_write,
211 .endianness = DEVICE_NATIVE_ENDIAN,
212 };
213
214 static const VMStateDescription vmstate_pxa2xx_cm = {
215 .name = "pxa2xx_cm",
216 .version_id = 0,
217 .minimum_version_id = 0,
218 .minimum_version_id_old = 0,
219 .fields = (VMStateField[]) {
220 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
221 VMSTATE_UINT32(clkcfg, PXA2xxState),
222 VMSTATE_UINT32(pmnc, PXA2xxState),
223 VMSTATE_END_OF_LIST()
224 }
225 };
226
227 static int pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri,
228 uint64_t *value)
229 {
230 PXA2xxState *s = (PXA2xxState *)ri->opaque;
231 *value = s->clkcfg;
232 return 0;
233 }
234
235 static int pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
236 uint64_t value)
237 {
238 PXA2xxState *s = (PXA2xxState *)ri->opaque;
239 s->clkcfg = value & 0xf;
240 if (value & 2) {
241 printf("%s: CPU frequency change attempt\n", __func__);
242 }
243 return 0;
244 }
245
246 static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
247 uint64_t value)
248 {
249 PXA2xxState *s = (PXA2xxState *)ri->opaque;
250 static const char *pwrmode[8] = {
251 "Normal", "Idle", "Deep-idle", "Standby",
252 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
253 };
254
255 if (value & 8) {
256 printf("%s: CPU voltage change attempt\n", __func__);
257 }
258 switch (value & 7) {
259 case 0:
260 /* Do nothing */
261 break;
262
263 case 1:
264 /* Idle */
265 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
266 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
267 break;
268 }
269 /* Fall through. */
270
271 case 2:
272 /* Deep-Idle */
273 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
274 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
275 goto message;
276
277 case 3:
278 s->cpu->env.uncached_cpsr =
279 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
280 s->cpu->env.cp15.c1_sys = 0;
281 s->cpu->env.cp15.c1_coproc = 0;
282 s->cpu->env.cp15.c2_base0 = 0;
283 s->cpu->env.cp15.c3 = 0;
284 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
285 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
286
287 /*
288 * The scratch-pad register is almost universally used
289 * for storing the return address on suspend. For the
290 * lack of a resuming bootloader, perform a jump
291 * directly to that address.
292 */
293 memset(s->cpu->env.regs, 0, 4 * 15);
294 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
295
296 #if 0
297 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
298 cpu_physical_memory_write(0, &buffer, 4);
299 buffer = s->pm_regs[PSPR >> 2];
300 cpu_physical_memory_write(8, &buffer, 4);
301 #endif
302
303 /* Suspend */
304 cpu_interrupt(CPU(arm_env_get_cpu(cpu_single_env)),
305 CPU_INTERRUPT_HALT);
306
307 goto message;
308
309 default:
310 message:
311 printf("%s: machine entered %s mode\n", __func__,
312 pwrmode[value & 7]);
313 }
314
315 return 0;
316 }
317
318 static int pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri,
319 uint64_t *value)
320 {
321 PXA2xxState *s = (PXA2xxState *)ri->opaque;
322 *value = s->pmnc;
323 return 0;
324 }
325
326 static int pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
327 uint64_t value)
328 {
329 PXA2xxState *s = (PXA2xxState *)ri->opaque;
330 s->pmnc = value;
331 return 0;
332 }
333
334 static int pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
335 uint64_t *value)
336 {
337 PXA2xxState *s = (PXA2xxState *)ri->opaque;
338 if (s->pmnc & 1) {
339 *value = qemu_get_clock_ns(vm_clock);
340 } else {
341 *value = 0;
342 }
343 return 0;
344 }
345
346 static const ARMCPRegInfo pxa_cp_reginfo[] = {
347 /* cp14 crm==1: perf registers */
348 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
349 .access = PL1_RW,
350 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write },
351 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
352 .access = PL1_RW,
353 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore },
354 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0,
355 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
356 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0,
357 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
358 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0,
359 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
360 /* cp14 crm==2: performance count registers */
361 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0,
362 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
363 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0,
364 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
365 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0,
366 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
367 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
368 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
369 /* cp14 crn==6: CLKCFG */
370 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
371 .access = PL1_RW,
372 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write },
373 /* cp14 crn==7: PWRMODE */
374 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
375 .access = PL1_RW,
376 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
377 REGINFO_SENTINEL
378 };
379
380 static void pxa2xx_setup_cp14(PXA2xxState *s)
381 {
382 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s);
383 }
384
385 #define MDCNFG 0x00 /* SDRAM Configuration register */
386 #define MDREFR 0x04 /* SDRAM Refresh Control register */
387 #define MSC0 0x08 /* Static Memory Control register 0 */
388 #define MSC1 0x0c /* Static Memory Control register 1 */
389 #define MSC2 0x10 /* Static Memory Control register 2 */
390 #define MECR 0x14 /* Expansion Memory Bus Config register */
391 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
392 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
393 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
394 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
395 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
396 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
397 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
398 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
399 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
400 #define ARB_CNTL 0x48 /* Arbiter Control register */
401 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
402 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
403 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
404 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
405 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
406 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
407 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
408
409 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
410 unsigned size)
411 {
412 PXA2xxState *s = (PXA2xxState *) opaque;
413
414 switch (addr) {
415 case MDCNFG ... SA1110:
416 if ((addr & 3) == 0)
417 return s->mm_regs[addr >> 2];
418
419 default:
420 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
421 break;
422 }
423 return 0;
424 }
425
426 static void pxa2xx_mm_write(void *opaque, hwaddr addr,
427 uint64_t value, unsigned size)
428 {
429 PXA2xxState *s = (PXA2xxState *) opaque;
430
431 switch (addr) {
432 case MDCNFG ... SA1110:
433 if ((addr & 3) == 0) {
434 s->mm_regs[addr >> 2] = value;
435 break;
436 }
437
438 default:
439 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
440 break;
441 }
442 }
443
444 static const MemoryRegionOps pxa2xx_mm_ops = {
445 .read = pxa2xx_mm_read,
446 .write = pxa2xx_mm_write,
447 .endianness = DEVICE_NATIVE_ENDIAN,
448 };
449
450 static const VMStateDescription vmstate_pxa2xx_mm = {
451 .name = "pxa2xx_mm",
452 .version_id = 0,
453 .minimum_version_id = 0,
454 .minimum_version_id_old = 0,
455 .fields = (VMStateField[]) {
456 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
457 VMSTATE_END_OF_LIST()
458 }
459 };
460
461 /* Synchronous Serial Ports */
462 typedef struct {
463 SysBusDevice busdev;
464 MemoryRegion iomem;
465 qemu_irq irq;
466 int enable;
467 SSIBus *bus;
468
469 uint32_t sscr[2];
470 uint32_t sspsp;
471 uint32_t ssto;
472 uint32_t ssitr;
473 uint32_t sssr;
474 uint8_t sstsa;
475 uint8_t ssrsa;
476 uint8_t ssacd;
477
478 uint32_t rx_fifo[16];
479 int rx_level;
480 int rx_start;
481 } PXA2xxSSPState;
482
483 #define SSCR0 0x00 /* SSP Control register 0 */
484 #define SSCR1 0x04 /* SSP Control register 1 */
485 #define SSSR 0x08 /* SSP Status register */
486 #define SSITR 0x0c /* SSP Interrupt Test register */
487 #define SSDR 0x10 /* SSP Data register */
488 #define SSTO 0x28 /* SSP Time-Out register */
489 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
490 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
491 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
492 #define SSTSS 0x38 /* SSP Time Slot Status register */
493 #define SSACD 0x3c /* SSP Audio Clock Divider register */
494
495 /* Bitfields for above registers */
496 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
497 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
498 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
499 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
500 #define SSCR0_SSE (1 << 7)
501 #define SSCR0_RIM (1 << 22)
502 #define SSCR0_TIM (1 << 23)
503 #define SSCR0_MOD (1 << 31)
504 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
505 #define SSCR1_RIE (1 << 0)
506 #define SSCR1_TIE (1 << 1)
507 #define SSCR1_LBM (1 << 2)
508 #define SSCR1_MWDS (1 << 5)
509 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
510 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
511 #define SSCR1_EFWR (1 << 14)
512 #define SSCR1_PINTE (1 << 18)
513 #define SSCR1_TINTE (1 << 19)
514 #define SSCR1_RSRE (1 << 20)
515 #define SSCR1_TSRE (1 << 21)
516 #define SSCR1_EBCEI (1 << 29)
517 #define SSITR_INT (7 << 5)
518 #define SSSR_TNF (1 << 2)
519 #define SSSR_RNE (1 << 3)
520 #define SSSR_TFS (1 << 5)
521 #define SSSR_RFS (1 << 6)
522 #define SSSR_ROR (1 << 7)
523 #define SSSR_PINT (1 << 18)
524 #define SSSR_TINT (1 << 19)
525 #define SSSR_EOC (1 << 20)
526 #define SSSR_TUR (1 << 21)
527 #define SSSR_BCE (1 << 23)
528 #define SSSR_RW 0x00bc0080
529
530 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
531 {
532 int level = 0;
533
534 level |= s->ssitr & SSITR_INT;
535 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
536 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
537 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
538 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
539 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
540 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
541 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
542 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
543 qemu_set_irq(s->irq, !!level);
544 }
545
546 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
547 {
548 s->sssr &= ~(0xf << 12); /* Clear RFL */
549 s->sssr &= ~(0xf << 8); /* Clear TFL */
550 s->sssr &= ~SSSR_TFS;
551 s->sssr &= ~SSSR_TNF;
552 if (s->enable) {
553 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
554 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
555 s->sssr |= SSSR_RFS;
556 else
557 s->sssr &= ~SSSR_RFS;
558 if (s->rx_level)
559 s->sssr |= SSSR_RNE;
560 else
561 s->sssr &= ~SSSR_RNE;
562 /* TX FIFO is never filled, so it is always in underrun
563 condition if SSP is enabled */
564 s->sssr |= SSSR_TFS;
565 s->sssr |= SSSR_TNF;
566 }
567
568 pxa2xx_ssp_int_update(s);
569 }
570
571 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
572 unsigned size)
573 {
574 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
575 uint32_t retval;
576
577 switch (addr) {
578 case SSCR0:
579 return s->sscr[0];
580 case SSCR1:
581 return s->sscr[1];
582 case SSPSP:
583 return s->sspsp;
584 case SSTO:
585 return s->ssto;
586 case SSITR:
587 return s->ssitr;
588 case SSSR:
589 return s->sssr | s->ssitr;
590 case SSDR:
591 if (!s->enable)
592 return 0xffffffff;
593 if (s->rx_level < 1) {
594 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
595 return 0xffffffff;
596 }
597 s->rx_level --;
598 retval = s->rx_fifo[s->rx_start ++];
599 s->rx_start &= 0xf;
600 pxa2xx_ssp_fifo_update(s);
601 return retval;
602 case SSTSA:
603 return s->sstsa;
604 case SSRSA:
605 return s->ssrsa;
606 case SSTSS:
607 return 0;
608 case SSACD:
609 return s->ssacd;
610 default:
611 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
612 break;
613 }
614 return 0;
615 }
616
617 static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
618 uint64_t value64, unsigned size)
619 {
620 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
621 uint32_t value = value64;
622
623 switch (addr) {
624 case SSCR0:
625 s->sscr[0] = value & 0xc7ffffff;
626 s->enable = value & SSCR0_SSE;
627 if (value & SSCR0_MOD)
628 printf("%s: Attempt to use network mode\n", __FUNCTION__);
629 if (s->enable && SSCR0_DSS(value) < 4)
630 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
631 SSCR0_DSS(value));
632 if (!(value & SSCR0_SSE)) {
633 s->sssr = 0;
634 s->ssitr = 0;
635 s->rx_level = 0;
636 }
637 pxa2xx_ssp_fifo_update(s);
638 break;
639
640 case SSCR1:
641 s->sscr[1] = value;
642 if (value & (SSCR1_LBM | SSCR1_EFWR))
643 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
644 pxa2xx_ssp_fifo_update(s);
645 break;
646
647 case SSPSP:
648 s->sspsp = value;
649 break;
650
651 case SSTO:
652 s->ssto = value;
653 break;
654
655 case SSITR:
656 s->ssitr = value & SSITR_INT;
657 pxa2xx_ssp_int_update(s);
658 break;
659
660 case SSSR:
661 s->sssr &= ~(value & SSSR_RW);
662 pxa2xx_ssp_int_update(s);
663 break;
664
665 case SSDR:
666 if (SSCR0_UWIRE(s->sscr[0])) {
667 if (s->sscr[1] & SSCR1_MWDS)
668 value &= 0xffff;
669 else
670 value &= 0xff;
671 } else
672 /* Note how 32bits overflow does no harm here */
673 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
674
675 /* Data goes from here to the Tx FIFO and is shifted out from
676 * there directly to the slave, no need to buffer it.
677 */
678 if (s->enable) {
679 uint32_t readval;
680 readval = ssi_transfer(s->bus, value);
681 if (s->rx_level < 0x10) {
682 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
683 } else {
684 s->sssr |= SSSR_ROR;
685 }
686 }
687 pxa2xx_ssp_fifo_update(s);
688 break;
689
690 case SSTSA:
691 s->sstsa = value;
692 break;
693
694 case SSRSA:
695 s->ssrsa = value;
696 break;
697
698 case SSACD:
699 s->ssacd = value;
700 break;
701
702 default:
703 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
704 break;
705 }
706 }
707
708 static const MemoryRegionOps pxa2xx_ssp_ops = {
709 .read = pxa2xx_ssp_read,
710 .write = pxa2xx_ssp_write,
711 .endianness = DEVICE_NATIVE_ENDIAN,
712 };
713
714 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
715 {
716 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
717 int i;
718
719 qemu_put_be32(f, s->enable);
720
721 qemu_put_be32s(f, &s->sscr[0]);
722 qemu_put_be32s(f, &s->sscr[1]);
723 qemu_put_be32s(f, &s->sspsp);
724 qemu_put_be32s(f, &s->ssto);
725 qemu_put_be32s(f, &s->ssitr);
726 qemu_put_be32s(f, &s->sssr);
727 qemu_put_8s(f, &s->sstsa);
728 qemu_put_8s(f, &s->ssrsa);
729 qemu_put_8s(f, &s->ssacd);
730
731 qemu_put_byte(f, s->rx_level);
732 for (i = 0; i < s->rx_level; i ++)
733 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
734 }
735
736 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
737 {
738 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
739 int i;
740
741 s->enable = qemu_get_be32(f);
742
743 qemu_get_be32s(f, &s->sscr[0]);
744 qemu_get_be32s(f, &s->sscr[1]);
745 qemu_get_be32s(f, &s->sspsp);
746 qemu_get_be32s(f, &s->ssto);
747 qemu_get_be32s(f, &s->ssitr);
748 qemu_get_be32s(f, &s->sssr);
749 qemu_get_8s(f, &s->sstsa);
750 qemu_get_8s(f, &s->ssrsa);
751 qemu_get_8s(f, &s->ssacd);
752
753 s->rx_level = qemu_get_byte(f);
754 s->rx_start = 0;
755 for (i = 0; i < s->rx_level; i ++)
756 s->rx_fifo[i] = qemu_get_byte(f);
757
758 return 0;
759 }
760
761 static int pxa2xx_ssp_init(SysBusDevice *dev)
762 {
763 PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev);
764
765 sysbus_init_irq(dev, &s->irq);
766
767 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s,
768 "pxa2xx-ssp", 0x1000);
769 sysbus_init_mmio(dev, &s->iomem);
770 register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
771 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
772
773 s->bus = ssi_create_bus(&dev->qdev, "ssi");
774 return 0;
775 }
776
777 /* Real-Time Clock */
778 #define RCNR 0x00 /* RTC Counter register */
779 #define RTAR 0x04 /* RTC Alarm register */
780 #define RTSR 0x08 /* RTC Status register */
781 #define RTTR 0x0c /* RTC Timer Trim register */
782 #define RDCR 0x10 /* RTC Day Counter register */
783 #define RYCR 0x14 /* RTC Year Counter register */
784 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
785 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
786 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
787 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
788 #define SWCR 0x28 /* RTC Stopwatch Counter register */
789 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
790 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
791 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
792 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
793
794 typedef struct {
795 SysBusDevice busdev;
796 MemoryRegion iomem;
797 uint32_t rttr;
798 uint32_t rtsr;
799 uint32_t rtar;
800 uint32_t rdar1;
801 uint32_t rdar2;
802 uint32_t ryar1;
803 uint32_t ryar2;
804 uint32_t swar1;
805 uint32_t swar2;
806 uint32_t piar;
807 uint32_t last_rcnr;
808 uint32_t last_rdcr;
809 uint32_t last_rycr;
810 uint32_t last_swcr;
811 uint32_t last_rtcpicr;
812 int64_t last_hz;
813 int64_t last_sw;
814 int64_t last_pi;
815 QEMUTimer *rtc_hz;
816 QEMUTimer *rtc_rdal1;
817 QEMUTimer *rtc_rdal2;
818 QEMUTimer *rtc_swal1;
819 QEMUTimer *rtc_swal2;
820 QEMUTimer *rtc_pi;
821 qemu_irq rtc_irq;
822 } PXA2xxRTCState;
823
824 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
825 {
826 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
827 }
828
829 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
830 {
831 int64_t rt = qemu_get_clock_ms(rtc_clock);
832 s->last_rcnr += ((rt - s->last_hz) << 15) /
833 (1000 * ((s->rttr & 0xffff) + 1));
834 s->last_rdcr += ((rt - s->last_hz) << 15) /
835 (1000 * ((s->rttr & 0xffff) + 1));
836 s->last_hz = rt;
837 }
838
839 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
840 {
841 int64_t rt = qemu_get_clock_ms(rtc_clock);
842 if (s->rtsr & (1 << 12))
843 s->last_swcr += (rt - s->last_sw) / 10;
844 s->last_sw = rt;
845 }
846
847 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
848 {
849 int64_t rt = qemu_get_clock_ms(rtc_clock);
850 if (s->rtsr & (1 << 15))
851 s->last_swcr += rt - s->last_pi;
852 s->last_pi = rt;
853 }
854
855 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
856 uint32_t rtsr)
857 {
858 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
859 qemu_mod_timer(s->rtc_hz, s->last_hz +
860 (((s->rtar - s->last_rcnr) * 1000 *
861 ((s->rttr & 0xffff) + 1)) >> 15));
862 else
863 qemu_del_timer(s->rtc_hz);
864
865 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
866 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
867 (((s->rdar1 - s->last_rdcr) * 1000 *
868 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
869 else
870 qemu_del_timer(s->rtc_rdal1);
871
872 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
873 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
874 (((s->rdar2 - s->last_rdcr) * 1000 *
875 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
876 else
877 qemu_del_timer(s->rtc_rdal2);
878
879 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
880 qemu_mod_timer(s->rtc_swal1, s->last_sw +
881 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
882 else
883 qemu_del_timer(s->rtc_swal1);
884
885 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
886 qemu_mod_timer(s->rtc_swal2, s->last_sw +
887 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
888 else
889 qemu_del_timer(s->rtc_swal2);
890
891 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
892 qemu_mod_timer(s->rtc_pi, s->last_pi +
893 (s->piar & 0xffff) - s->last_rtcpicr);
894 else
895 qemu_del_timer(s->rtc_pi);
896 }
897
898 static inline void pxa2xx_rtc_hz_tick(void *opaque)
899 {
900 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
901 s->rtsr |= (1 << 0);
902 pxa2xx_rtc_alarm_update(s, s->rtsr);
903 pxa2xx_rtc_int_update(s);
904 }
905
906 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
907 {
908 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
909 s->rtsr |= (1 << 4);
910 pxa2xx_rtc_alarm_update(s, s->rtsr);
911 pxa2xx_rtc_int_update(s);
912 }
913
914 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
915 {
916 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
917 s->rtsr |= (1 << 6);
918 pxa2xx_rtc_alarm_update(s, s->rtsr);
919 pxa2xx_rtc_int_update(s);
920 }
921
922 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
923 {
924 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
925 s->rtsr |= (1 << 8);
926 pxa2xx_rtc_alarm_update(s, s->rtsr);
927 pxa2xx_rtc_int_update(s);
928 }
929
930 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
931 {
932 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
933 s->rtsr |= (1 << 10);
934 pxa2xx_rtc_alarm_update(s, s->rtsr);
935 pxa2xx_rtc_int_update(s);
936 }
937
938 static inline void pxa2xx_rtc_pi_tick(void *opaque)
939 {
940 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
941 s->rtsr |= (1 << 13);
942 pxa2xx_rtc_piupdate(s);
943 s->last_rtcpicr = 0;
944 pxa2xx_rtc_alarm_update(s, s->rtsr);
945 pxa2xx_rtc_int_update(s);
946 }
947
948 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
949 unsigned size)
950 {
951 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
952
953 switch (addr) {
954 case RTTR:
955 return s->rttr;
956 case RTSR:
957 return s->rtsr;
958 case RTAR:
959 return s->rtar;
960 case RDAR1:
961 return s->rdar1;
962 case RDAR2:
963 return s->rdar2;
964 case RYAR1:
965 return s->ryar1;
966 case RYAR2:
967 return s->ryar2;
968 case SWAR1:
969 return s->swar1;
970 case SWAR2:
971 return s->swar2;
972 case PIAR:
973 return s->piar;
974 case RCNR:
975 return s->last_rcnr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /
976 (1000 * ((s->rttr & 0xffff) + 1));
977 case RDCR:
978 return s->last_rdcr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /
979 (1000 * ((s->rttr & 0xffff) + 1));
980 case RYCR:
981 return s->last_rycr;
982 case SWCR:
983 if (s->rtsr & (1 << 12))
984 return s->last_swcr + (qemu_get_clock_ms(rtc_clock) - s->last_sw) / 10;
985 else
986 return s->last_swcr;
987 default:
988 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
989 break;
990 }
991 return 0;
992 }
993
994 static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
995 uint64_t value64, unsigned size)
996 {
997 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
998 uint32_t value = value64;
999
1000 switch (addr) {
1001 case RTTR:
1002 if (!(s->rttr & (1 << 31))) {
1003 pxa2xx_rtc_hzupdate(s);
1004 s->rttr = value;
1005 pxa2xx_rtc_alarm_update(s, s->rtsr);
1006 }
1007 break;
1008
1009 case RTSR:
1010 if ((s->rtsr ^ value) & (1 << 15))
1011 pxa2xx_rtc_piupdate(s);
1012
1013 if ((s->rtsr ^ value) & (1 << 12))
1014 pxa2xx_rtc_swupdate(s);
1015
1016 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1017 pxa2xx_rtc_alarm_update(s, value);
1018
1019 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1020 pxa2xx_rtc_int_update(s);
1021 break;
1022
1023 case RTAR:
1024 s->rtar = value;
1025 pxa2xx_rtc_alarm_update(s, s->rtsr);
1026 break;
1027
1028 case RDAR1:
1029 s->rdar1 = value;
1030 pxa2xx_rtc_alarm_update(s, s->rtsr);
1031 break;
1032
1033 case RDAR2:
1034 s->rdar2 = value;
1035 pxa2xx_rtc_alarm_update(s, s->rtsr);
1036 break;
1037
1038 case RYAR1:
1039 s->ryar1 = value;
1040 pxa2xx_rtc_alarm_update(s, s->rtsr);
1041 break;
1042
1043 case RYAR2:
1044 s->ryar2 = value;
1045 pxa2xx_rtc_alarm_update(s, s->rtsr);
1046 break;
1047
1048 case SWAR1:
1049 pxa2xx_rtc_swupdate(s);
1050 s->swar1 = value;
1051 s->last_swcr = 0;
1052 pxa2xx_rtc_alarm_update(s, s->rtsr);
1053 break;
1054
1055 case SWAR2:
1056 s->swar2 = value;
1057 pxa2xx_rtc_alarm_update(s, s->rtsr);
1058 break;
1059
1060 case PIAR:
1061 s->piar = value;
1062 pxa2xx_rtc_alarm_update(s, s->rtsr);
1063 break;
1064
1065 case RCNR:
1066 pxa2xx_rtc_hzupdate(s);
1067 s->last_rcnr = value;
1068 pxa2xx_rtc_alarm_update(s, s->rtsr);
1069 break;
1070
1071 case RDCR:
1072 pxa2xx_rtc_hzupdate(s);
1073 s->last_rdcr = value;
1074 pxa2xx_rtc_alarm_update(s, s->rtsr);
1075 break;
1076
1077 case RYCR:
1078 s->last_rycr = value;
1079 break;
1080
1081 case SWCR:
1082 pxa2xx_rtc_swupdate(s);
1083 s->last_swcr = value;
1084 pxa2xx_rtc_alarm_update(s, s->rtsr);
1085 break;
1086
1087 case RTCPICR:
1088 pxa2xx_rtc_piupdate(s);
1089 s->last_rtcpicr = value & 0xffff;
1090 pxa2xx_rtc_alarm_update(s, s->rtsr);
1091 break;
1092
1093 default:
1094 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1095 }
1096 }
1097
1098 static const MemoryRegionOps pxa2xx_rtc_ops = {
1099 .read = pxa2xx_rtc_read,
1100 .write = pxa2xx_rtc_write,
1101 .endianness = DEVICE_NATIVE_ENDIAN,
1102 };
1103
1104 static int pxa2xx_rtc_init(SysBusDevice *dev)
1105 {
1106 PXA2xxRTCState *s = FROM_SYSBUS(PXA2xxRTCState, dev);
1107 struct tm tm;
1108 int wom;
1109
1110 s->rttr = 0x7fff;
1111 s->rtsr = 0;
1112
1113 qemu_get_timedate(&tm, 0);
1114 wom = ((tm.tm_mday - 1) / 7) + 1;
1115
1116 s->last_rcnr = (uint32_t) mktimegm(&tm);
1117 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1118 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1119 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1120 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1121 s->last_swcr = (tm.tm_hour << 19) |
1122 (tm.tm_min << 13) | (tm.tm_sec << 7);
1123 s->last_rtcpicr = 0;
1124 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rtc_clock);
1125
1126 s->rtc_hz = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_hz_tick, s);
1127 s->rtc_rdal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);
1128 s->rtc_rdal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);
1129 s->rtc_swal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);
1130 s->rtc_swal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);
1131 s->rtc_pi = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_pi_tick, s);
1132
1133 sysbus_init_irq(dev, &s->rtc_irq);
1134
1135 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_rtc_ops, s,
1136 "pxa2xx-rtc", 0x10000);
1137 sysbus_init_mmio(dev, &s->iomem);
1138
1139 return 0;
1140 }
1141
1142 static void pxa2xx_rtc_pre_save(void *opaque)
1143 {
1144 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1145
1146 pxa2xx_rtc_hzupdate(s);
1147 pxa2xx_rtc_piupdate(s);
1148 pxa2xx_rtc_swupdate(s);
1149 }
1150
1151 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1152 {
1153 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1154
1155 pxa2xx_rtc_alarm_update(s, s->rtsr);
1156
1157 return 0;
1158 }
1159
1160 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1161 .name = "pxa2xx_rtc",
1162 .version_id = 0,
1163 .minimum_version_id = 0,
1164 .minimum_version_id_old = 0,
1165 .pre_save = pxa2xx_rtc_pre_save,
1166 .post_load = pxa2xx_rtc_post_load,
1167 .fields = (VMStateField[]) {
1168 VMSTATE_UINT32(rttr, PXA2xxRTCState),
1169 VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1170 VMSTATE_UINT32(rtar, PXA2xxRTCState),
1171 VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1172 VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1173 VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1174 VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1175 VMSTATE_UINT32(swar1, PXA2xxRTCState),
1176 VMSTATE_UINT32(swar2, PXA2xxRTCState),
1177 VMSTATE_UINT32(piar, PXA2xxRTCState),
1178 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1179 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1180 VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1181 VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1182 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1183 VMSTATE_INT64(last_hz, PXA2xxRTCState),
1184 VMSTATE_INT64(last_sw, PXA2xxRTCState),
1185 VMSTATE_INT64(last_pi, PXA2xxRTCState),
1186 VMSTATE_END_OF_LIST(),
1187 },
1188 };
1189
1190 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data)
1191 {
1192 DeviceClass *dc = DEVICE_CLASS(klass);
1193 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1194
1195 k->init = pxa2xx_rtc_init;
1196 dc->desc = "PXA2xx RTC Controller";
1197 dc->vmsd = &vmstate_pxa2xx_rtc_regs;
1198 }
1199
1200 static const TypeInfo pxa2xx_rtc_sysbus_info = {
1201 .name = "pxa2xx_rtc",
1202 .parent = TYPE_SYS_BUS_DEVICE,
1203 .instance_size = sizeof(PXA2xxRTCState),
1204 .class_init = pxa2xx_rtc_sysbus_class_init,
1205 };
1206
1207 /* I2C Interface */
1208 typedef struct {
1209 I2CSlave i2c;
1210 PXA2xxI2CState *host;
1211 } PXA2xxI2CSlaveState;
1212
1213 struct PXA2xxI2CState {
1214 SysBusDevice busdev;
1215 MemoryRegion iomem;
1216 PXA2xxI2CSlaveState *slave;
1217 i2c_bus *bus;
1218 qemu_irq irq;
1219 uint32_t offset;
1220 uint32_t region_size;
1221
1222 uint16_t control;
1223 uint16_t status;
1224 uint8_t ibmr;
1225 uint8_t data;
1226 };
1227
1228 #define IBMR 0x80 /* I2C Bus Monitor register */
1229 #define IDBR 0x88 /* I2C Data Buffer register */
1230 #define ICR 0x90 /* I2C Control register */
1231 #define ISR 0x98 /* I2C Status register */
1232 #define ISAR 0xa0 /* I2C Slave Address register */
1233
1234 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1235 {
1236 uint16_t level = 0;
1237 level |= s->status & s->control & (1 << 10); /* BED */
1238 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1239 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1240 level |= s->status & (1 << 9); /* SAD */
1241 qemu_set_irq(s->irq, !!level);
1242 }
1243
1244 /* These are only stubs now. */
1245 static void pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event)
1246 {
1247 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1248 PXA2xxI2CState *s = slave->host;
1249
1250 switch (event) {
1251 case I2C_START_SEND:
1252 s->status |= (1 << 9); /* set SAD */
1253 s->status &= ~(1 << 0); /* clear RWM */
1254 break;
1255 case I2C_START_RECV:
1256 s->status |= (1 << 9); /* set SAD */
1257 s->status |= 1 << 0; /* set RWM */
1258 break;
1259 case I2C_FINISH:
1260 s->status |= (1 << 4); /* set SSD */
1261 break;
1262 case I2C_NACK:
1263 s->status |= 1 << 1; /* set ACKNAK */
1264 break;
1265 }
1266 pxa2xx_i2c_update(s);
1267 }
1268
1269 static int pxa2xx_i2c_rx(I2CSlave *i2c)
1270 {
1271 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1272 PXA2xxI2CState *s = slave->host;
1273 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1274 return 0;
1275
1276 if (s->status & (1 << 0)) { /* RWM */
1277 s->status |= 1 << 6; /* set ITE */
1278 }
1279 pxa2xx_i2c_update(s);
1280
1281 return s->data;
1282 }
1283
1284 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data)
1285 {
1286 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1287 PXA2xxI2CState *s = slave->host;
1288 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1289 return 1;
1290
1291 if (!(s->status & (1 << 0))) { /* RWM */
1292 s->status |= 1 << 7; /* set IRF */
1293 s->data = data;
1294 }
1295 pxa2xx_i2c_update(s);
1296
1297 return 1;
1298 }
1299
1300 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
1301 unsigned size)
1302 {
1303 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1304
1305 addr -= s->offset;
1306 switch (addr) {
1307 case ICR:
1308 return s->control;
1309 case ISR:
1310 return s->status | (i2c_bus_busy(s->bus) << 2);
1311 case ISAR:
1312 return s->slave->i2c.address;
1313 case IDBR:
1314 return s->data;
1315 case IBMR:
1316 if (s->status & (1 << 2))
1317 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1318 else
1319 s->ibmr = 0;
1320 return s->ibmr;
1321 default:
1322 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1323 break;
1324 }
1325 return 0;
1326 }
1327
1328 static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
1329 uint64_t value64, unsigned size)
1330 {
1331 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1332 uint32_t value = value64;
1333 int ack;
1334
1335 addr -= s->offset;
1336 switch (addr) {
1337 case ICR:
1338 s->control = value & 0xfff7;
1339 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1340 /* TODO: slave mode */
1341 if (value & (1 << 0)) { /* START condition */
1342 if (s->data & 1)
1343 s->status |= 1 << 0; /* set RWM */
1344 else
1345 s->status &= ~(1 << 0); /* clear RWM */
1346 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1347 } else {
1348 if (s->status & (1 << 0)) { /* RWM */
1349 s->data = i2c_recv(s->bus);
1350 if (value & (1 << 2)) /* ACKNAK */
1351 i2c_nack(s->bus);
1352 ack = 1;
1353 } else
1354 ack = !i2c_send(s->bus, s->data);
1355 }
1356
1357 if (value & (1 << 1)) /* STOP condition */
1358 i2c_end_transfer(s->bus);
1359
1360 if (ack) {
1361 if (value & (1 << 0)) /* START condition */
1362 s->status |= 1 << 6; /* set ITE */
1363 else
1364 if (s->status & (1 << 0)) /* RWM */
1365 s->status |= 1 << 7; /* set IRF */
1366 else
1367 s->status |= 1 << 6; /* set ITE */
1368 s->status &= ~(1 << 1); /* clear ACKNAK */
1369 } else {
1370 s->status |= 1 << 6; /* set ITE */
1371 s->status |= 1 << 10; /* set BED */
1372 s->status |= 1 << 1; /* set ACKNAK */
1373 }
1374 }
1375 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1376 if (value & (1 << 4)) /* MA */
1377 i2c_end_transfer(s->bus);
1378 pxa2xx_i2c_update(s);
1379 break;
1380
1381 case ISR:
1382 s->status &= ~(value & 0x07f0);
1383 pxa2xx_i2c_update(s);
1384 break;
1385
1386 case ISAR:
1387 i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
1388 break;
1389
1390 case IDBR:
1391 s->data = value & 0xff;
1392 break;
1393
1394 default:
1395 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1396 }
1397 }
1398
1399 static const MemoryRegionOps pxa2xx_i2c_ops = {
1400 .read = pxa2xx_i2c_read,
1401 .write = pxa2xx_i2c_write,
1402 .endianness = DEVICE_NATIVE_ENDIAN,
1403 };
1404
1405 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1406 .name = "pxa2xx_i2c_slave",
1407 .version_id = 1,
1408 .minimum_version_id = 1,
1409 .minimum_version_id_old = 1,
1410 .fields = (VMStateField []) {
1411 VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState),
1412 VMSTATE_END_OF_LIST()
1413 }
1414 };
1415
1416 static const VMStateDescription vmstate_pxa2xx_i2c = {
1417 .name = "pxa2xx_i2c",
1418 .version_id = 1,
1419 .minimum_version_id = 1,
1420 .minimum_version_id_old = 1,
1421 .fields = (VMStateField []) {
1422 VMSTATE_UINT16(control, PXA2xxI2CState),
1423 VMSTATE_UINT16(status, PXA2xxI2CState),
1424 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1425 VMSTATE_UINT8(data, PXA2xxI2CState),
1426 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1427 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState *),
1428 VMSTATE_END_OF_LIST()
1429 }
1430 };
1431
1432 static int pxa2xx_i2c_slave_init(I2CSlave *i2c)
1433 {
1434 /* Nothing to do. */
1435 return 0;
1436 }
1437
1438 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
1439 {
1440 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1441
1442 k->init = pxa2xx_i2c_slave_init;
1443 k->event = pxa2xx_i2c_event;
1444 k->recv = pxa2xx_i2c_rx;
1445 k->send = pxa2xx_i2c_tx;
1446 }
1447
1448 static const TypeInfo pxa2xx_i2c_slave_info = {
1449 .name = "pxa2xx-i2c-slave",
1450 .parent = TYPE_I2C_SLAVE,
1451 .instance_size = sizeof(PXA2xxI2CSlaveState),
1452 .class_init = pxa2xx_i2c_slave_class_init,
1453 };
1454
1455 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
1456 qemu_irq irq, uint32_t region_size)
1457 {
1458 DeviceState *dev;
1459 SysBusDevice *i2c_dev;
1460 PXA2xxI2CState *s;
1461
1462 i2c_dev = SYS_BUS_DEVICE(qdev_create(NULL, "pxa2xx_i2c"));
1463 qdev_prop_set_uint32(&i2c_dev->qdev, "size", region_size + 1);
1464 qdev_prop_set_uint32(&i2c_dev->qdev, "offset", base & region_size);
1465
1466 qdev_init_nofail(&i2c_dev->qdev);
1467
1468 sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1469 sysbus_connect_irq(i2c_dev, 0, irq);
1470
1471 s = FROM_SYSBUS(PXA2xxI2CState, i2c_dev);
1472 /* FIXME: Should the slave device really be on a separate bus? */
1473 dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0);
1474 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE(dev));
1475 s->slave->host = s;
1476
1477 return s;
1478 }
1479
1480 static int pxa2xx_i2c_initfn(SysBusDevice *dev)
1481 {
1482 PXA2xxI2CState *s = FROM_SYSBUS(PXA2xxI2CState, dev);
1483
1484 s->bus = i2c_init_bus(&dev->qdev, "i2c");
1485
1486 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_i2c_ops, s,
1487 "pxa2xx-i2c", s->region_size);
1488 sysbus_init_mmio(dev, &s->iomem);
1489 sysbus_init_irq(dev, &s->irq);
1490
1491 return 0;
1492 }
1493
1494 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1495 {
1496 return s->bus;
1497 }
1498
1499 static Property pxa2xx_i2c_properties[] = {
1500 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1501 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1502 DEFINE_PROP_END_OF_LIST(),
1503 };
1504
1505 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data)
1506 {
1507 DeviceClass *dc = DEVICE_CLASS(klass);
1508 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1509
1510 k->init = pxa2xx_i2c_initfn;
1511 dc->desc = "PXA2xx I2C Bus Controller";
1512 dc->vmsd = &vmstate_pxa2xx_i2c;
1513 dc->props = pxa2xx_i2c_properties;
1514 }
1515
1516 static const TypeInfo pxa2xx_i2c_info = {
1517 .name = "pxa2xx_i2c",
1518 .parent = TYPE_SYS_BUS_DEVICE,
1519 .instance_size = sizeof(PXA2xxI2CState),
1520 .class_init = pxa2xx_i2c_class_init,
1521 };
1522
1523 /* PXA Inter-IC Sound Controller */
1524 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1525 {
1526 i2s->rx_len = 0;
1527 i2s->tx_len = 0;
1528 i2s->fifo_len = 0;
1529 i2s->clk = 0x1a;
1530 i2s->control[0] = 0x00;
1531 i2s->control[1] = 0x00;
1532 i2s->status = 0x00;
1533 i2s->mask = 0x00;
1534 }
1535
1536 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1537 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1538 #define SACR_DREC(val) (val & (1 << 3))
1539 #define SACR_DPRL(val) (val & (1 << 4))
1540
1541 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1542 {
1543 int rfs, tfs;
1544 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1545 !SACR_DREC(i2s->control[1]);
1546 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1547 i2s->enable && !SACR_DPRL(i2s->control[1]);
1548
1549 qemu_set_irq(i2s->rx_dma, rfs);
1550 qemu_set_irq(i2s->tx_dma, tfs);
1551
1552 i2s->status &= 0xe0;
1553 if (i2s->fifo_len < 16 || !i2s->enable)
1554 i2s->status |= 1 << 0; /* TNF */
1555 if (i2s->rx_len)
1556 i2s->status |= 1 << 1; /* RNE */
1557 if (i2s->enable)
1558 i2s->status |= 1 << 2; /* BSY */
1559 if (tfs)
1560 i2s->status |= 1 << 3; /* TFS */
1561 if (rfs)
1562 i2s->status |= 1 << 4; /* RFS */
1563 if (!(i2s->tx_len && i2s->enable))
1564 i2s->status |= i2s->fifo_len << 8; /* TFL */
1565 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1566
1567 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1568 }
1569
1570 #define SACR0 0x00 /* Serial Audio Global Control register */
1571 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1572 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1573 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1574 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1575 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1576 #define SADR 0x80 /* Serial Audio Data register */
1577
1578 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
1579 unsigned size)
1580 {
1581 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1582
1583 switch (addr) {
1584 case SACR0:
1585 return s->control[0];
1586 case SACR1:
1587 return s->control[1];
1588 case SASR0:
1589 return s->status;
1590 case SAIMR:
1591 return s->mask;
1592 case SAICR:
1593 return 0;
1594 case SADIV:
1595 return s->clk;
1596 case SADR:
1597 if (s->rx_len > 0) {
1598 s->rx_len --;
1599 pxa2xx_i2s_update(s);
1600 return s->codec_in(s->opaque);
1601 }
1602 return 0;
1603 default:
1604 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1605 break;
1606 }
1607 return 0;
1608 }
1609
1610 static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
1611 uint64_t value, unsigned size)
1612 {
1613 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1614 uint32_t *sample;
1615
1616 switch (addr) {
1617 case SACR0:
1618 if (value & (1 << 3)) /* RST */
1619 pxa2xx_i2s_reset(s);
1620 s->control[0] = value & 0xff3d;
1621 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1622 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1623 s->codec_out(s->opaque, *sample);
1624 s->status &= ~(1 << 7); /* I2SOFF */
1625 }
1626 if (value & (1 << 4)) /* EFWR */
1627 printf("%s: Attempt to use special function\n", __FUNCTION__);
1628 s->enable = (value & 9) == 1; /* ENB && !RST*/
1629 pxa2xx_i2s_update(s);
1630 break;
1631 case SACR1:
1632 s->control[1] = value & 0x0039;
1633 if (value & (1 << 5)) /* ENLBF */
1634 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1635 if (value & (1 << 4)) /* DPRL */
1636 s->fifo_len = 0;
1637 pxa2xx_i2s_update(s);
1638 break;
1639 case SAIMR:
1640 s->mask = value & 0x0078;
1641 pxa2xx_i2s_update(s);
1642 break;
1643 case SAICR:
1644 s->status &= ~(value & (3 << 5));
1645 pxa2xx_i2s_update(s);
1646 break;
1647 case SADIV:
1648 s->clk = value & 0x007f;
1649 break;
1650 case SADR:
1651 if (s->tx_len && s->enable) {
1652 s->tx_len --;
1653 pxa2xx_i2s_update(s);
1654 s->codec_out(s->opaque, value);
1655 } else if (s->fifo_len < 16) {
1656 s->fifo[s->fifo_len ++] = value;
1657 pxa2xx_i2s_update(s);
1658 }
1659 break;
1660 default:
1661 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1662 }
1663 }
1664
1665 static const MemoryRegionOps pxa2xx_i2s_ops = {
1666 .read = pxa2xx_i2s_read,
1667 .write = pxa2xx_i2s_write,
1668 .endianness = DEVICE_NATIVE_ENDIAN,
1669 };
1670
1671 static const VMStateDescription vmstate_pxa2xx_i2s = {
1672 .name = "pxa2xx_i2s",
1673 .version_id = 0,
1674 .minimum_version_id = 0,
1675 .minimum_version_id_old = 0,
1676 .fields = (VMStateField[]) {
1677 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1678 VMSTATE_UINT32(status, PXA2xxI2SState),
1679 VMSTATE_UINT32(mask, PXA2xxI2SState),
1680 VMSTATE_UINT32(clk, PXA2xxI2SState),
1681 VMSTATE_INT32(enable, PXA2xxI2SState),
1682 VMSTATE_INT32(rx_len, PXA2xxI2SState),
1683 VMSTATE_INT32(tx_len, PXA2xxI2SState),
1684 VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1685 VMSTATE_END_OF_LIST()
1686 }
1687 };
1688
1689 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1690 {
1691 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1692 uint32_t *sample;
1693
1694 /* Signal FIFO errors */
1695 if (s->enable && s->tx_len)
1696 s->status |= 1 << 5; /* TUR */
1697 if (s->enable && s->rx_len)
1698 s->status |= 1 << 6; /* ROR */
1699
1700 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1701 * handle the cases where it makes a difference. */
1702 s->tx_len = tx - s->fifo_len;
1703 s->rx_len = rx;
1704 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1705 if (s->enable)
1706 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1707 s->codec_out(s->opaque, *sample);
1708 pxa2xx_i2s_update(s);
1709 }
1710
1711 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
1712 hwaddr base,
1713 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1714 {
1715 PXA2xxI2SState *s = (PXA2xxI2SState *)
1716 g_malloc0(sizeof(PXA2xxI2SState));
1717
1718 s->irq = irq;
1719 s->rx_dma = rx_dma;
1720 s->tx_dma = tx_dma;
1721 s->data_req = pxa2xx_i2s_data_req;
1722
1723 pxa2xx_i2s_reset(s);
1724
1725 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s,
1726 "pxa2xx-i2s", 0x100000);
1727 memory_region_add_subregion(sysmem, base, &s->iomem);
1728
1729 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1730
1731 return s;
1732 }
1733
1734 /* PXA Fast Infra-red Communications Port */
1735 struct PXA2xxFIrState {
1736 MemoryRegion iomem;
1737 qemu_irq irq;
1738 qemu_irq rx_dma;
1739 qemu_irq tx_dma;
1740 int enable;
1741 CharDriverState *chr;
1742
1743 uint8_t control[3];
1744 uint8_t status[2];
1745
1746 int rx_len;
1747 int rx_start;
1748 uint8_t rx_fifo[64];
1749 };
1750
1751 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1752 {
1753 s->control[0] = 0x00;
1754 s->control[1] = 0x00;
1755 s->control[2] = 0x00;
1756 s->status[0] = 0x00;
1757 s->status[1] = 0x00;
1758 s->enable = 0;
1759 }
1760
1761 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1762 {
1763 static const int tresh[4] = { 8, 16, 32, 0 };
1764 int intr = 0;
1765 if ((s->control[0] & (1 << 4)) && /* RXE */
1766 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1767 s->status[0] |= 1 << 4; /* RFS */
1768 else
1769 s->status[0] &= ~(1 << 4); /* RFS */
1770 if (s->control[0] & (1 << 3)) /* TXE */
1771 s->status[0] |= 1 << 3; /* TFS */
1772 else
1773 s->status[0] &= ~(1 << 3); /* TFS */
1774 if (s->rx_len)
1775 s->status[1] |= 1 << 2; /* RNE */
1776 else
1777 s->status[1] &= ~(1 << 2); /* RNE */
1778 if (s->control[0] & (1 << 4)) /* RXE */
1779 s->status[1] |= 1 << 0; /* RSY */
1780 else
1781 s->status[1] &= ~(1 << 0); /* RSY */
1782
1783 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1784 (s->status[0] & (1 << 4)); /* RFS */
1785 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1786 (s->status[0] & (1 << 3)); /* TFS */
1787 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1788 (s->status[0] & (1 << 6)); /* EOC */
1789 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1790 (s->status[0] & (1 << 1)); /* TUR */
1791 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1792
1793 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1794 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1795
1796 qemu_set_irq(s->irq, intr && s->enable);
1797 }
1798
1799 #define ICCR0 0x00 /* FICP Control register 0 */
1800 #define ICCR1 0x04 /* FICP Control register 1 */
1801 #define ICCR2 0x08 /* FICP Control register 2 */
1802 #define ICDR 0x0c /* FICP Data register */
1803 #define ICSR0 0x14 /* FICP Status register 0 */
1804 #define ICSR1 0x18 /* FICP Status register 1 */
1805 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1806
1807 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
1808 unsigned size)
1809 {
1810 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1811 uint8_t ret;
1812
1813 switch (addr) {
1814 case ICCR0:
1815 return s->control[0];
1816 case ICCR1:
1817 return s->control[1];
1818 case ICCR2:
1819 return s->control[2];
1820 case ICDR:
1821 s->status[0] &= ~0x01;
1822 s->status[1] &= ~0x72;
1823 if (s->rx_len) {
1824 s->rx_len --;
1825 ret = s->rx_fifo[s->rx_start ++];
1826 s->rx_start &= 63;
1827 pxa2xx_fir_update(s);
1828 return ret;
1829 }
1830 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1831 break;
1832 case ICSR0:
1833 return s->status[0];
1834 case ICSR1:
1835 return s->status[1] | (1 << 3); /* TNF */
1836 case ICFOR:
1837 return s->rx_len;
1838 default:
1839 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1840 break;
1841 }
1842 return 0;
1843 }
1844
1845 static void pxa2xx_fir_write(void *opaque, hwaddr addr,
1846 uint64_t value64, unsigned size)
1847 {
1848 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1849 uint32_t value = value64;
1850 uint8_t ch;
1851
1852 switch (addr) {
1853 case ICCR0:
1854 s->control[0] = value;
1855 if (!(value & (1 << 4))) /* RXE */
1856 s->rx_len = s->rx_start = 0;
1857 if (!(value & (1 << 3))) { /* TXE */
1858 /* Nop */
1859 }
1860 s->enable = value & 1; /* ITR */
1861 if (!s->enable)
1862 s->status[0] = 0;
1863 pxa2xx_fir_update(s);
1864 break;
1865 case ICCR1:
1866 s->control[1] = value;
1867 break;
1868 case ICCR2:
1869 s->control[2] = value & 0x3f;
1870 pxa2xx_fir_update(s);
1871 break;
1872 case ICDR:
1873 if (s->control[2] & (1 << 2)) /* TXP */
1874 ch = value;
1875 else
1876 ch = ~value;
1877 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1878 qemu_chr_fe_write(s->chr, &ch, 1);
1879 break;
1880 case ICSR0:
1881 s->status[0] &= ~(value & 0x66);
1882 pxa2xx_fir_update(s);
1883 break;
1884 case ICFOR:
1885 break;
1886 default:
1887 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1888 }
1889 }
1890
1891 static const MemoryRegionOps pxa2xx_fir_ops = {
1892 .read = pxa2xx_fir_read,
1893 .write = pxa2xx_fir_write,
1894 .endianness = DEVICE_NATIVE_ENDIAN,
1895 };
1896
1897 static int pxa2xx_fir_is_empty(void *opaque)
1898 {
1899 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1900 return (s->rx_len < 64);
1901 }
1902
1903 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1904 {
1905 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1906 if (!(s->control[0] & (1 << 4))) /* RXE */
1907 return;
1908
1909 while (size --) {
1910 s->status[1] |= 1 << 4; /* EOF */
1911 if (s->rx_len >= 64) {
1912 s->status[1] |= 1 << 6; /* ROR */
1913 break;
1914 }
1915
1916 if (s->control[2] & (1 << 3)) /* RXP */
1917 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1918 else
1919 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1920 }
1921
1922 pxa2xx_fir_update(s);
1923 }
1924
1925 static void pxa2xx_fir_event(void *opaque, int event)
1926 {
1927 }
1928
1929 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1930 {
1931 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1932 int i;
1933
1934 qemu_put_be32(f, s->enable);
1935
1936 qemu_put_8s(f, &s->control[0]);
1937 qemu_put_8s(f, &s->control[1]);
1938 qemu_put_8s(f, &s->control[2]);
1939 qemu_put_8s(f, &s->status[0]);
1940 qemu_put_8s(f, &s->status[1]);
1941
1942 qemu_put_byte(f, s->rx_len);
1943 for (i = 0; i < s->rx_len; i ++)
1944 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1945 }
1946
1947 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1948 {
1949 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1950 int i;
1951
1952 s->enable = qemu_get_be32(f);
1953
1954 qemu_get_8s(f, &s->control[0]);
1955 qemu_get_8s(f, &s->control[1]);
1956 qemu_get_8s(f, &s->control[2]);
1957 qemu_get_8s(f, &s->status[0]);
1958 qemu_get_8s(f, &s->status[1]);
1959
1960 s->rx_len = qemu_get_byte(f);
1961 s->rx_start = 0;
1962 for (i = 0; i < s->rx_len; i ++)
1963 s->rx_fifo[i] = qemu_get_byte(f);
1964
1965 return 0;
1966 }
1967
1968 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
1969 hwaddr base,
1970 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
1971 CharDriverState *chr)
1972 {
1973 PXA2xxFIrState *s = (PXA2xxFIrState *)
1974 g_malloc0(sizeof(PXA2xxFIrState));
1975
1976 s->irq = irq;
1977 s->rx_dma = rx_dma;
1978 s->tx_dma = tx_dma;
1979 s->chr = chr;
1980
1981 pxa2xx_fir_reset(s);
1982
1983 memory_region_init_io(&s->iomem, NULL, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000);
1984 memory_region_add_subregion(sysmem, base, &s->iomem);
1985
1986 if (chr) {
1987 qemu_chr_fe_claim_no_fail(chr);
1988 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
1989 pxa2xx_fir_rx, pxa2xx_fir_event, s);
1990 }
1991
1992 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
1993 pxa2xx_fir_load, s);
1994
1995 return s;
1996 }
1997
1998 static void pxa2xx_reset(void *opaque, int line, int level)
1999 {
2000 PXA2xxState *s = (PXA2xxState *) opaque;
2001
2002 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2003 cpu_reset(CPU(s->cpu));
2004 /* TODO: reset peripherals */
2005 }
2006 }
2007
2008 /* Initialise a PXA270 integrated chip (ARM based core). */
2009 PXA2xxState *pxa270_init(MemoryRegion *address_space,
2010 unsigned int sdram_size, const char *revision)
2011 {
2012 PXA2xxState *s;
2013 int i;
2014 DriveInfo *dinfo;
2015 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2016
2017 if (revision && strncmp(revision, "pxa27", 5)) {
2018 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2019 exit(1);
2020 }
2021 if (!revision)
2022 revision = "pxa270";
2023
2024 s->cpu = cpu_arm_init(revision);
2025 if (s->cpu == NULL) {
2026 fprintf(stderr, "Unable to find CPU definition\n");
2027 exit(1);
2028 }
2029 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2030
2031 /* SDRAM & Internal Memory Storage */
2032 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size);
2033 vmstate_register_ram_global(&s->sdram);
2034 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2035 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000);
2036 vmstate_register_ram_global(&s->internal);
2037 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2038 &s->internal);
2039
2040 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2041
2042 s->dma = pxa27x_dma_init(0x40000000,
2043 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2044
2045 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2046 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2047 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2048 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2049 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2050 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2051 NULL);
2052
2053 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121);
2054
2055 dinfo = drive_get(IF_SD, 0, 0);
2056 if (!dinfo) {
2057 fprintf(stderr, "qemu: missing SecureDigital device\n");
2058 exit(1);
2059 }
2060 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv,
2061 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2062 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2063 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2064
2065 for (i = 0; pxa270_serial[i].io_base; i++) {
2066 if (serial_hds[i]) {
2067 serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
2068 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2069 14857000 / 16, serial_hds[i],
2070 DEVICE_NATIVE_ENDIAN);
2071 } else {
2072 break;
2073 }
2074 }
2075 if (serial_hds[i])
2076 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2077 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2078 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2079 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2080 serial_hds[i]);
2081
2082 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2083 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2084
2085 s->cm_base = 0x41300000;
2086 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2087 s->clkcfg = 0x00000009; /* Turbo mode active */
2088 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2089 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2090 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2091
2092 pxa2xx_setup_cp14(s);
2093
2094 s->mm_base = 0x48000000;
2095 s->mm_regs[MDMRS >> 2] = 0x00020002;
2096 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2097 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2098 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2099 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2100 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2101
2102 s->pm_base = 0x40f00000;
2103 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2104 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2105 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2106
2107 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2108 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2109 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2110 DeviceState *dev;
2111 dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
2112 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2113 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2114 }
2115
2116 if (usb_enabled(false)) {
2117 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2118 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2119 }
2120
2121 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2122 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2123
2124 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2125 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2126
2127 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2128 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2129 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2130 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2131
2132 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2133 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2134 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2135 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2136
2137 s->kp = pxa27x_keypad_init(address_space, 0x41500000,
2138 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2139
2140 /* GPIO1 resets the processor */
2141 /* The handler can be overridden by board-specific code */
2142 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2143 return s;
2144 }
2145
2146 /* Initialise a PXA255 integrated chip (ARM based core). */
2147 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
2148 {
2149 PXA2xxState *s;
2150 int i;
2151 DriveInfo *dinfo;
2152
2153 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2154
2155 s->cpu = cpu_arm_init("pxa255");
2156 if (s->cpu == NULL) {
2157 fprintf(stderr, "Unable to find CPU definition\n");
2158 exit(1);
2159 }
2160 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2161
2162 /* SDRAM & Internal Memory Storage */
2163 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size);
2164 vmstate_register_ram_global(&s->sdram);
2165 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2166 memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
2167 PXA2XX_INTERNAL_SIZE);
2168 vmstate_register_ram_global(&s->internal);
2169 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2170 &s->internal);
2171
2172 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2173
2174 s->dma = pxa255_dma_init(0x40000000,
2175 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2176
2177 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2178 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2179 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2180 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2181 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2182 NULL);
2183
2184 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85);
2185
2186 dinfo = drive_get(IF_SD, 0, 0);
2187 if (!dinfo) {
2188 fprintf(stderr, "qemu: missing SecureDigital device\n");
2189 exit(1);
2190 }
2191 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv,
2192 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2193 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2194 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2195
2196 for (i = 0; pxa255_serial[i].io_base; i++) {
2197 if (serial_hds[i]) {
2198 serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
2199 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2200 14745600 / 16, serial_hds[i],
2201 DEVICE_NATIVE_ENDIAN);
2202 } else {
2203 break;
2204 }
2205 }
2206 if (serial_hds[i])
2207 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2208 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2209 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2210 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2211 serial_hds[i]);
2212
2213 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2214 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2215
2216 s->cm_base = 0x41300000;
2217 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2218 s->clkcfg = 0x00000009; /* Turbo mode active */
2219 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2220 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2221 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2222
2223 pxa2xx_setup_cp14(s);
2224
2225 s->mm_base = 0x48000000;
2226 s->mm_regs[MDMRS >> 2] = 0x00020002;
2227 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2228 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2229 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2230 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2231 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2232
2233 s->pm_base = 0x40f00000;
2234 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2235 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2236 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2237
2238 for (i = 0; pxa255_ssp[i].io_base; i ++);
2239 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2240 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2241 DeviceState *dev;
2242 dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
2243 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2244 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2245 }
2246
2247 if (usb_enabled(false)) {
2248 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2249 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2250 }
2251
2252 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2253 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2254
2255 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2256 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2257
2258 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2259 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2260 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2261 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2262
2263 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2264 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2265 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2266 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2267
2268 /* GPIO1 resets the processor */
2269 /* The handler can be overridden by board-specific code */
2270 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2271 return s;
2272 }
2273
2274 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
2275 {
2276 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
2277
2278 sdc->init = pxa2xx_ssp_init;
2279 }
2280
2281 static const TypeInfo pxa2xx_ssp_info = {
2282 .name = "pxa2xx-ssp",
2283 .parent = TYPE_SYS_BUS_DEVICE,
2284 .instance_size = sizeof(PXA2xxSSPState),
2285 .class_init = pxa2xx_ssp_class_init,
2286 };
2287
2288 static void pxa2xx_register_types(void)
2289 {
2290 type_register_static(&pxa2xx_i2c_slave_info);
2291 type_register_static(&pxa2xx_ssp_info);
2292 type_register_static(&pxa2xx_i2c_info);
2293 type_register_static(&pxa2xx_rtc_sysbus_info);
2294 }
2295
2296 type_init(pxa2xx_register_types)
Qemu copy for testing