hw/ide/macio.c

   1 /*
   2  * QEMU IDE Emulation: MacIO support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <hw/hw.h>
  26 #include <hw/ppc_mac.h>
  27 #include <hw/mac_dbdma.h>
  28 #include "block.h"
  29 #include "dma.h"
  30
  31 #include <hw/ide/internal.h>
  32
  33 /***********************************************************/
  34 /* MacIO based PowerPC IDE */
  35
  36 typedef struct MACIOIDEState {
  37     MemoryRegion mem;
  38     IDEBus bus;
  39     BlockDriverAIOCB *aiocb;
  40 } MACIOIDEState;
  41
  42 #define MACIO_PAGE_SIZE 4096
  43
  44 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
  45 {
  46     DBDMA_io *io = opaque;
  47     MACIOIDEState *m = io->opaque;
  48     IDEState *s = idebus_active_if(&m->bus);
  49
  50     if (ret < 0) {
  51         m->aiocb = NULL;
  52         qemu_sglist_destroy(&s->sg);
  53         ide_atapi_io_error(s, ret);
  54         goto done;
  55     }
  56
  57     if (s->io_buffer_size > 0) {
  58         m->aiocb = NULL;
  59         qemu_sglist_destroy(&s->sg);
  60
  61         s->packet_transfer_size -= s->io_buffer_size;
  62
  63         s->io_buffer_index += s->io_buffer_size;
  64         s->lba += s->io_buffer_index >> 11;
  65         s->io_buffer_index &= 0x7ff;
  66     }
  67
  68     if (s->packet_transfer_size <= 0)
  69         ide_atapi_cmd_ok(s);
  70
  71     if (io->len == 0) {
  72         goto done;
  73     }
  74
  75     /* launch next transfer */
  76
  77     s->io_buffer_size = io->len;
  78
  79     qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1,
  80                      &dma_context_memory);
  81     qemu_sglist_add(&s->sg, io->addr, io->len);
  82     io->addr += io->len;
  83     io->len = 0;
  84
  85     m->aiocb = dma_bdrv_read(s->bs, &s->sg,
  86                              (int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
  87                              pmac_ide_atapi_transfer_cb, io);
  88     return;
  89
  90 done:
  91     bdrv_acct_done(s->bs, &s->acct);
  92     io->dma_end(opaque);
  93 }
  94
  95 static void pmac_ide_transfer_cb(void *opaque, int ret)
  96 {
  97     DBDMA_io *io = opaque;
  98     MACIOIDEState *m = io->opaque;
  99     IDEState *s = idebus_active_if(&m->bus);
 100     int n;
 101     int64_t sector_num;
 102
 103     if (ret < 0) {
 104         m->aiocb = NULL;
 105         qemu_sglist_destroy(&s->sg);
 106         ide_dma_error(s);
 107         goto done;
 108     }
 109
 110     sector_num = ide_get_sector(s);
 111     if (s->io_buffer_size > 0) {
 112         m->aiocb = NULL;
 113         qemu_sglist_destroy(&s->sg);
 114         n = (s->io_buffer_size + 0x1ff) >> 9;
 115         sector_num += n;
 116         ide_set_sector(s, sector_num);
 117         s->nsector -= n;
 118     }
 119
 120     /* end of transfer ? */
 121     if (s->nsector == 0) {
 122         s->status = READY_STAT | SEEK_STAT;
 123         ide_set_irq(s->bus);
 124     }
 125
 126     /* end of DMA ? */
 127     if (io->len == 0) {
 128         goto done;
 129     }
 130
 131     /* launch next transfer */
 132
 133     s->io_buffer_index = 0;
 134     s->io_buffer_size = io->len;
 135
 136     qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1,
 137                      &dma_context_memory);
 138     qemu_sglist_add(&s->sg, io->addr, io->len);
 139     io->addr += io->len;
 140     io->len = 0;
 141
 142     switch (s->dma_cmd) {
 143     case IDE_DMA_READ:
 144         m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
 145                                  pmac_ide_transfer_cb, io);
 146         break;
 147     case IDE_DMA_WRITE:
 148         m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
 149                                   pmac_ide_transfer_cb, io);
 150         break;
 151     case IDE_DMA_TRIM:
 152         m->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
 153                                ide_issue_trim, pmac_ide_transfer_cb, s,
 154                                DMA_DIRECTION_TO_DEVICE);
 155         break;
 156     }
 157     return;
 158
 159 done:
 160     if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
 161         bdrv_acct_done(s->bs, &s->acct);
 162     }
 163     io->dma_end(io);
 164 }
 165
 166 static void pmac_ide_transfer(DBDMA_io *io)
 167 {
 168     MACIOIDEState *m = io->opaque;
 169     IDEState *s = idebus_active_if(&m->bus);
 170
 171     s->io_buffer_size = 0;
 172     if (s->drive_kind == IDE_CD) {
 173         bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
 174         pmac_ide_atapi_transfer_cb(io, 0);
 175         return;
 176     }
 177
 178     switch (s->dma_cmd) {
 179     case IDE_DMA_READ:
 180         bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
 181         break;
 182     case IDE_DMA_WRITE:
 183         bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_WRITE);
 184         break;
 185     default:
 186         break;
 187     }
 188
 189     pmac_ide_transfer_cb(io, 0);
 190 }
 191
 192 static void pmac_ide_flush(DBDMA_io *io)
 193 {
 194     MACIOIDEState *m = io->opaque;
 195
 196     if (m->aiocb) {
 197         bdrv_drain_all();
 198     }
 199 }
 200
 201 /* PowerMac IDE memory IO */
 202 static void pmac_ide_writeb (void *opaque,
 203                              hwaddr addr, uint32_t val)
 204 {
 205     MACIOIDEState *d = opaque;
 206
 207     addr = (addr & 0xFFF) >> 4;
 208     switch (addr) {
 209     case 1 ... 7:
 210         ide_ioport_write(&d->bus, addr, val);
 211         break;
 212     case 8:
 213     case 22:
 214         ide_cmd_write(&d->bus, 0, val);
 215         break;
 216     default:
 217         break;
 218     }
 219 }
 220
 221 static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
 222 {
 223     uint8_t retval;
 224     MACIOIDEState *d = opaque;
 225
 226     addr = (addr & 0xFFF) >> 4;
 227     switch (addr) {
 228     case 1 ... 7:
 229         retval = ide_ioport_read(&d->bus, addr);
 230         break;
 231     case 8:
 232     case 22:
 233         retval = ide_status_read(&d->bus, 0);
 234         break;
 235     default:
 236         retval = 0xFF;
 237         break;
 238     }
 239     return retval;
 240 }
 241
 242 static void pmac_ide_writew (void *opaque,
 243                              hwaddr addr, uint32_t val)
 244 {
 245     MACIOIDEState *d = opaque;
 246
 247     addr = (addr & 0xFFF) >> 4;
 248     val = bswap16(val);
 249     if (addr == 0) {
 250         ide_data_writew(&d->bus, 0, val);
 251     }
 252 }
 253
 254 static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
 255 {
 256     uint16_t retval;
 257     MACIOIDEState *d = opaque;
 258
 259     addr = (addr & 0xFFF) >> 4;
 260     if (addr == 0) {
 261         retval = ide_data_readw(&d->bus, 0);
 262     } else {
 263         retval = 0xFFFF;
 264     }
 265     retval = bswap16(retval);
 266     return retval;
 267 }
 268
 269 static void pmac_ide_writel (void *opaque,
 270                              hwaddr addr, uint32_t val)
 271 {
 272     MACIOIDEState *d = opaque;
 273
 274     addr = (addr & 0xFFF) >> 4;
 275     val = bswap32(val);
 276     if (addr == 0) {
 277         ide_data_writel(&d->bus, 0, val);
 278     }
 279 }
 280
 281 static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
 282 {
 283     uint32_t retval;
 284     MACIOIDEState *d = opaque;
 285
 286     addr = (addr & 0xFFF) >> 4;
 287     if (addr == 0) {
 288         retval = ide_data_readl(&d->bus, 0);
 289     } else {
 290         retval = 0xFFFFFFFF;
 291     }
 292     retval = bswap32(retval);
 293     return retval;
 294 }
 295
 296 static const MemoryRegionOps pmac_ide_ops = {
 297     .old_mmio = {
 298         .write = {
 299             pmac_ide_writeb,
 300             pmac_ide_writew,
 301             pmac_ide_writel,
 302         },
 303         .read = {
 304             pmac_ide_readb,
 305             pmac_ide_readw,
 306             pmac_ide_readl,
 307         },
 308     },
 309     .endianness = DEVICE_NATIVE_ENDIAN,
 310 };
 311
 312 static const VMStateDescription vmstate_pmac = {
 313     .name = "ide",
 314     .version_id = 3,
 315     .minimum_version_id = 0,
 316     .minimum_version_id_old = 0,
 317     .fields      = (VMStateField []) {
 318         VMSTATE_IDE_BUS(bus, MACIOIDEState),
 319         VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
 320         VMSTATE_END_OF_LIST()
 321     }
 322 };
 323
 324 static void pmac_ide_reset(void *opaque)
 325 {
 326     MACIOIDEState *d = opaque;
 327
 328     ide_bus_reset(&d->bus);
 329 }
 330
 331 /* hd_table must contain 4 block drivers */
 332 /* PowerMac uses memory mapped registers, not I/O. Return the memory
 333    I/O index to access the ide. */
 334 MemoryRegion *pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
 335                              void *dbdma, int channel, qemu_irq dma_irq)
 336 {
 337     MACIOIDEState *d;
 338
 339     d = g_malloc0(sizeof(MACIOIDEState));
 340     ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq);
 341
 342     if (dbdma)
 343         DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
 344
 345     memory_region_init_io(&d->mem, &pmac_ide_ops, d, "pmac-ide", 0x1000);
 346     vmstate_register(NULL, 0, &vmstate_pmac, d);
 347     qemu_register_reset(pmac_ide_reset, d);
 348
 349     return &d->mem;
 350 }