2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "sysemu/sysemu.h"
31 #include "sysemu/blockdev.h"
32 #include "sysemu/cpus.h"
33 #include "sysemu/kvm.h"
35 #include "mmu-hash64.h"
37 #include "hw/boards.h"
38 #include "hw/ppc/ppc.h"
39 #include "hw/loader.h"
41 #include "hw/ppc/spapr.h"
42 #include "hw/ppc/spapr_vio.h"
43 #include "hw/pci-host/spapr.h"
44 #include "hw/ppc/xics.h"
45 #include "hw/pci/msi.h"
47 #include "hw/pci/pci.h"
49 #include "exec/address-spaces.h"
51 #include "qemu/config-file.h"
55 /* SLOF memory layout:
57 * SLOF raw image loaded at 0, copies its romfs right below the flat
58 * device-tree, then position SLOF itself 31M below that
60 * So we set FW_OVERHEAD to 40MB which should account for all of that
63 * We load our kernel at 4M, leaving space for SLOF initial image
65 #define FDT_MAX_SIZE 0x10000
66 #define RTAS_MAX_SIZE 0x10000
67 #define FW_MAX_SIZE 0x400000
68 #define FW_FILE_NAME "slof.bin"
69 #define FW_OVERHEAD 0x2800000
70 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
72 #define MIN_RMA_SLOF 128UL
74 #define TIMEBASE_FREQ 512000000ULL
77 #define XICS_IRQS 1024
79 #define PHANDLE_XICP 0x00001111
81 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
83 sPAPREnvironment
*spapr
;
85 int spapr_allocate_irq(int hint
, bool lsi
)
91 /* FIXME: we should probably check for collisions somehow */
93 irq
= spapr
->next_irq
++;
96 /* Configure irq type */
97 if (!xics_get_qirq(spapr
->icp
, irq
)) {
101 xics_set_irq_type(spapr
->icp
, irq
, lsi
);
106 /* Allocate block of consequtive IRQs, returns a number of the first */
107 int spapr_allocate_irq_block(int num
, bool lsi
)
112 for (i
= 0; i
< num
; ++i
) {
115 irq
= spapr_allocate_irq(0, lsi
);
124 /* If the above doesn't create a consecutive block then that's
126 assert(irq
== (first
+ i
));
132 static XICSState
*try_create_xics(const char *type
, int nr_servers
,
137 dev
= qdev_create(NULL
, type
);
138 qdev_prop_set_uint32(dev
, "nr_servers", nr_servers
);
139 qdev_prop_set_uint32(dev
, "nr_irqs", nr_irqs
);
140 if (qdev_init(dev
) < 0) {
147 static XICSState
*xics_system_init(int nr_servers
, int nr_irqs
)
149 XICSState
*icp
= NULL
;
151 icp
= try_create_xics(TYPE_XICS
, nr_servers
, nr_irqs
);
153 perror("Failed to create XICS\n");
160 static int spapr_fixup_cpu_dt(void *fdt
, sPAPREnvironment
*spapr
)
165 int smt
= kvmppc_smt_threads();
166 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
168 assert(spapr
->cpu_model
);
170 for (cpu
= first_cpu
; cpu
!= NULL
; cpu
= cpu
->next_cpu
) {
171 uint32_t associativity
[] = {cpu_to_be32(0x5),
175 cpu_to_be32(cpu
->numa_node
),
176 cpu_to_be32(cpu
->cpu_index
)};
178 if ((cpu
->cpu_index
% smt
) != 0) {
182 snprintf(cpu_model
, 32, "/cpus/%s@%x", spapr
->cpu_model
,
185 offset
= fdt_path_offset(fdt
, cpu_model
);
190 if (nb_numa_nodes
> 1) {
191 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
192 sizeof(associativity
));
198 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
199 pft_size_prop
, sizeof(pft_size_prop
));
208 static size_t create_page_sizes_prop(CPUPPCState
*env
, uint32_t *prop
,
211 size_t maxcells
= maxsize
/ sizeof(uint32_t);
215 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
216 struct ppc_one_seg_page_size
*sps
= &env
->sps
.sps
[i
];
218 if (!sps
->page_shift
) {
221 for (count
= 0; count
< PPC_PAGE_SIZES_MAX_SZ
; count
++) {
222 if (sps
->enc
[count
].page_shift
== 0) {
226 if ((p
- prop
) >= (maxcells
- 3 - count
* 2)) {
229 *(p
++) = cpu_to_be32(sps
->page_shift
);
230 *(p
++) = cpu_to_be32(sps
->slb_enc
);
231 *(p
++) = cpu_to_be32(count
);
232 for (j
= 0; j
< count
; j
++) {
233 *(p
++) = cpu_to_be32(sps
->enc
[j
].page_shift
);
234 *(p
++) = cpu_to_be32(sps
->enc
[j
].pte_enc
);
238 return (p
- prop
) * sizeof(uint32_t);
245 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
246 #exp, fdt_strerror(ret)); \
252 static void *spapr_create_fdt_skel(const char *cpu_model
,
256 const char *boot_device
,
257 const char *kernel_cmdline
,
262 uint32_t start_prop
= cpu_to_be32(initrd_base
);
263 uint32_t end_prop
= cpu_to_be32(initrd_base
+ initrd_size
);
264 char hypertas_prop
[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
265 "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk";
266 char qemu_hypertas_prop
[] = "hcall-memop1";
267 uint32_t refpoints
[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
268 uint32_t interrupt_server_ranges_prop
[] = {0, cpu_to_be32(smp_cpus
)};
270 int i
, smt
= kvmppc_smt_threads();
271 unsigned char vec5
[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
273 fdt
= g_malloc0(FDT_MAX_SIZE
);
274 _FDT((fdt_create(fdt
, FDT_MAX_SIZE
)));
277 _FDT((fdt_add_reservemap_entry(fdt
, KERNEL_LOAD_ADDR
, kernel_size
)));
280 _FDT((fdt_add_reservemap_entry(fdt
, initrd_base
, initrd_size
)));
282 _FDT((fdt_finish_reservemap(fdt
)));
285 _FDT((fdt_begin_node(fdt
, "")));
286 _FDT((fdt_property_string(fdt
, "device_type", "chrp")));
287 _FDT((fdt_property_string(fdt
, "model", "IBM pSeries (emulated by qemu)")));
288 _FDT((fdt_property_string(fdt
, "compatible", "qemu,pseries")));
290 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x2)));
291 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x2)));
294 _FDT((fdt_begin_node(fdt
, "chosen")));
296 /* Set Form1_affinity */
297 _FDT((fdt_property(fdt
, "ibm,architecture-vec-5", vec5
, sizeof(vec5
))));
299 _FDT((fdt_property_string(fdt
, "bootargs", kernel_cmdline
)));
300 _FDT((fdt_property(fdt
, "linux,initrd-start",
301 &start_prop
, sizeof(start_prop
))));
302 _FDT((fdt_property(fdt
, "linux,initrd-end",
303 &end_prop
, sizeof(end_prop
))));
305 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
306 cpu_to_be64(kernel_size
) };
308 _FDT((fdt_property(fdt
, "qemu,boot-kernel", &kprop
, sizeof(kprop
))));
311 _FDT((fdt_property_string(fdt
, "qemu,boot-device", boot_device
)));
313 _FDT((fdt_property_cell(fdt
, "qemu,graphic-width", graphic_width
)));
314 _FDT((fdt_property_cell(fdt
, "qemu,graphic-height", graphic_height
)));
315 _FDT((fdt_property_cell(fdt
, "qemu,graphic-depth", graphic_depth
)));
317 _FDT((fdt_end_node(fdt
)));
320 _FDT((fdt_begin_node(fdt
, "cpus")));
322 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x1)));
323 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x0)));
325 modelname
= g_strdup(cpu_model
);
327 for (i
= 0; i
< strlen(modelname
); i
++) {
328 modelname
[i
] = toupper(modelname
[i
]);
331 /* This is needed during FDT finalization */
332 spapr
->cpu_model
= g_strdup(modelname
);
334 for (cs
= first_cpu
; cs
!= NULL
; cs
= cs
->next_cpu
) {
335 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
336 CPUPPCState
*env
= &cpu
->env
;
337 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
338 int index
= cs
->cpu_index
;
339 uint32_t servers_prop
[smp_threads
];
340 uint32_t gservers_prop
[smp_threads
* 2];
342 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
343 0xffffffff, 0xffffffff};
344 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ
;
345 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
346 uint32_t page_sizes_prop
[64];
347 size_t page_sizes_prop_size
;
349 if ((index
% smt
) != 0) {
353 nodename
= g_strdup_printf("%s@%x", modelname
, index
);
355 _FDT((fdt_begin_node(fdt
, nodename
)));
359 _FDT((fdt_property_cell(fdt
, "reg", index
)));
360 _FDT((fdt_property_string(fdt
, "device_type", "cpu")));
362 _FDT((fdt_property_cell(fdt
, "cpu-version", env
->spr
[SPR_PVR
])));
363 _FDT((fdt_property_cell(fdt
, "d-cache-block-size",
364 env
->dcache_line_size
)));
365 _FDT((fdt_property_cell(fdt
, "d-cache-line-size",
366 env
->dcache_line_size
)));
367 _FDT((fdt_property_cell(fdt
, "i-cache-block-size",
368 env
->icache_line_size
)));
369 _FDT((fdt_property_cell(fdt
, "i-cache-line-size",
370 env
->icache_line_size
)));
372 if (pcc
->l1_dcache_size
) {
373 _FDT((fdt_property_cell(fdt
, "d-cache-size", pcc
->l1_dcache_size
)));
375 fprintf(stderr
, "Warning: Unknown L1 dcache size for cpu\n");
377 if (pcc
->l1_icache_size
) {
378 _FDT((fdt_property_cell(fdt
, "i-cache-size", pcc
->l1_icache_size
)));
380 fprintf(stderr
, "Warning: Unknown L1 icache size for cpu\n");
383 _FDT((fdt_property_cell(fdt
, "timebase-frequency", tbfreq
)));
384 _FDT((fdt_property_cell(fdt
, "clock-frequency", cpufreq
)));
385 _FDT((fdt_property_cell(fdt
, "ibm,slb-size", env
->slb_nr
)));
386 _FDT((fdt_property_string(fdt
, "status", "okay")));
387 _FDT((fdt_property(fdt
, "64-bit", NULL
, 0)));
389 /* Build interrupt servers and gservers properties */
390 for (i
= 0; i
< smp_threads
; i
++) {
391 servers_prop
[i
] = cpu_to_be32(index
+ i
);
392 /* Hack, direct the group queues back to cpu 0 */
393 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
394 gservers_prop
[i
*2 + 1] = 0;
396 _FDT((fdt_property(fdt
, "ibm,ppc-interrupt-server#s",
397 servers_prop
, sizeof(servers_prop
))));
398 _FDT((fdt_property(fdt
, "ibm,ppc-interrupt-gserver#s",
399 gservers_prop
, sizeof(gservers_prop
))));
401 if (env
->mmu_model
& POWERPC_MMU_1TSEG
) {
402 _FDT((fdt_property(fdt
, "ibm,processor-segment-sizes",
403 segs
, sizeof(segs
))));
406 /* Advertise VMX/VSX (vector extensions) if available
407 * 0 / no property == no vector extensions
408 * 1 == VMX / Altivec available
409 * 2 == VSX available */
410 if (env
->insns_flags
& PPC_ALTIVEC
) {
411 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
413 _FDT((fdt_property_cell(fdt
, "ibm,vmx", vmx
)));
416 /* Advertise DFP (Decimal Floating Point) if available
417 * 0 / no property == no DFP
418 * 1 == DFP available */
419 if (env
->insns_flags2
& PPC2_DFP
) {
420 _FDT((fdt_property_cell(fdt
, "ibm,dfp", 1)));
423 page_sizes_prop_size
= create_page_sizes_prop(env
, page_sizes_prop
,
424 sizeof(page_sizes_prop
));
425 if (page_sizes_prop_size
) {
426 _FDT((fdt_property(fdt
, "ibm,segment-page-sizes",
427 page_sizes_prop
, page_sizes_prop_size
)));
430 _FDT((fdt_end_node(fdt
)));
435 _FDT((fdt_end_node(fdt
)));
438 _FDT((fdt_begin_node(fdt
, "rtas")));
440 _FDT((fdt_property(fdt
, "ibm,hypertas-functions", hypertas_prop
,
441 sizeof(hypertas_prop
))));
442 _FDT((fdt_property(fdt
, "qemu,hypertas-functions", qemu_hypertas_prop
,
443 sizeof(qemu_hypertas_prop
))));
445 _FDT((fdt_property(fdt
, "ibm,associativity-reference-points",
446 refpoints
, sizeof(refpoints
))));
448 _FDT((fdt_property_cell(fdt
, "rtas-error-log-max", RTAS_ERROR_LOG_MAX
)));
450 _FDT((fdt_end_node(fdt
)));
452 /* interrupt controller */
453 _FDT((fdt_begin_node(fdt
, "interrupt-controller")));
455 _FDT((fdt_property_string(fdt
, "device_type",
456 "PowerPC-External-Interrupt-Presentation")));
457 _FDT((fdt_property_string(fdt
, "compatible", "IBM,ppc-xicp")));
458 _FDT((fdt_property(fdt
, "interrupt-controller", NULL
, 0)));
459 _FDT((fdt_property(fdt
, "ibm,interrupt-server-ranges",
460 interrupt_server_ranges_prop
,
461 sizeof(interrupt_server_ranges_prop
))));
462 _FDT((fdt_property_cell(fdt
, "#interrupt-cells", 2)));
463 _FDT((fdt_property_cell(fdt
, "linux,phandle", PHANDLE_XICP
)));
464 _FDT((fdt_property_cell(fdt
, "phandle", PHANDLE_XICP
)));
466 _FDT((fdt_end_node(fdt
)));
469 _FDT((fdt_begin_node(fdt
, "vdevice")));
471 _FDT((fdt_property_string(fdt
, "device_type", "vdevice")));
472 _FDT((fdt_property_string(fdt
, "compatible", "IBM,vdevice")));
473 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x1)));
474 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x0)));
475 _FDT((fdt_property_cell(fdt
, "#interrupt-cells", 0x2)));
476 _FDT((fdt_property(fdt
, "interrupt-controller", NULL
, 0)));
478 _FDT((fdt_end_node(fdt
)));
481 spapr_events_fdt_skel(fdt
, epow_irq
);
483 _FDT((fdt_end_node(fdt
))); /* close root node */
484 _FDT((fdt_finish(fdt
)));
489 static int spapr_populate_memory(sPAPREnvironment
*spapr
, void *fdt
)
491 uint32_t associativity
[] = {cpu_to_be32(0x4), cpu_to_be32(0x0),
492 cpu_to_be32(0x0), cpu_to_be32(0x0),
495 hwaddr node0_size
, mem_start
;
496 uint64_t mem_reg_property
[2];
500 node0_size
= (nb_numa_nodes
> 1) ? node_mem
[0] : ram_size
;
501 if (spapr
->rma_size
> node0_size
) {
502 spapr
->rma_size
= node0_size
;
506 mem_reg_property
[0] = 0;
507 mem_reg_property
[1] = cpu_to_be64(spapr
->rma_size
);
508 off
= fdt_add_subnode(fdt
, 0, "memory@0");
510 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
511 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
512 sizeof(mem_reg_property
))));
513 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
514 sizeof(associativity
))));
517 if (node0_size
> spapr
->rma_size
) {
518 mem_reg_property
[0] = cpu_to_be64(spapr
->rma_size
);
519 mem_reg_property
[1] = cpu_to_be64(node0_size
- spapr
->rma_size
);
521 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, spapr
->rma_size
);
522 off
= fdt_add_subnode(fdt
, 0, mem_name
);
524 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
525 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
526 sizeof(mem_reg_property
))));
527 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
528 sizeof(associativity
))));
531 /* RAM: Node 1 and beyond */
532 mem_start
= node0_size
;
533 for (i
= 1; i
< nb_numa_nodes
; i
++) {
534 mem_reg_property
[0] = cpu_to_be64(mem_start
);
535 mem_reg_property
[1] = cpu_to_be64(node_mem
[i
]);
536 associativity
[3] = associativity
[4] = cpu_to_be32(i
);
537 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, mem_start
);
538 off
= fdt_add_subnode(fdt
, 0, mem_name
);
540 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
541 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
542 sizeof(mem_reg_property
))));
543 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
544 sizeof(associativity
))));
545 mem_start
+= node_mem
[i
];
551 static void spapr_finalize_fdt(sPAPREnvironment
*spapr
,
560 fdt
= g_malloc(FDT_MAX_SIZE
);
562 /* open out the base tree into a temp buffer for the final tweaks */
563 _FDT((fdt_open_into(spapr
->fdt_skel
, fdt
, FDT_MAX_SIZE
)));
565 ret
= spapr_populate_memory(spapr
, fdt
);
567 fprintf(stderr
, "couldn't setup memory nodes in fdt\n");
571 ret
= spapr_populate_vdevice(spapr
->vio_bus
, fdt
);
573 fprintf(stderr
, "couldn't setup vio devices in fdt\n");
577 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
578 ret
= spapr_populate_pci_dt(phb
, PHANDLE_XICP
, fdt
);
582 fprintf(stderr
, "couldn't setup PCI devices in fdt\n");
587 ret
= spapr_rtas_device_tree_setup(fdt
, rtas_addr
, rtas_size
);
589 fprintf(stderr
, "Couldn't set up RTAS device tree properties\n");
592 /* Advertise NUMA via ibm,associativity */
593 ret
= spapr_fixup_cpu_dt(fdt
, spapr
);
595 fprintf(stderr
, "Couldn't finalize CPU device tree properties\n");
598 if (!spapr
->has_graphics
) {
599 spapr_populate_chosen_stdout(fdt
, spapr
->vio_bus
);
602 _FDT((fdt_pack(fdt
)));
604 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
605 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
606 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
610 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
615 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
617 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
620 static void emulate_spapr_hypercall(PowerPCCPU
*cpu
)
622 CPUPPCState
*env
= &cpu
->env
;
625 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
626 env
->gpr
[3] = H_PRIVILEGE
;
628 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
632 static void spapr_reset_htab(sPAPREnvironment
*spapr
)
636 /* allocate hash page table. For now we always make this 16mb,
637 * later we should probably make it scale to the size of guest
640 shift
= kvmppc_reset_htab(spapr
->htab_shift
);
643 /* Kernel handles htab, we don't need to allocate one */
644 spapr
->htab_shift
= shift
;
647 /* Allocate an htab if we don't yet have one */
648 spapr
->htab
= qemu_memalign(HTAB_SIZE(spapr
), HTAB_SIZE(spapr
));
652 memset(spapr
->htab
, 0, HTAB_SIZE(spapr
));
655 /* Update the RMA size if necessary */
656 if (spapr
->vrma_adjust
) {
657 spapr
->rma_size
= kvmppc_rma_size(ram_size
, spapr
->htab_shift
);
661 static void ppc_spapr_reset(void)
663 PowerPCCPU
*first_ppc_cpu
;
665 /* Reset the hash table & recalc the RMA */
666 spapr_reset_htab(spapr
);
668 qemu_devices_reset();
671 spapr_finalize_fdt(spapr
, spapr
->fdt_addr
, spapr
->rtas_addr
,
674 /* Set up the entry state */
675 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
676 first_ppc_cpu
->env
.gpr
[3] = spapr
->fdt_addr
;
677 first_ppc_cpu
->env
.gpr
[5] = 0;
678 first_cpu
->halted
= 0;
679 first_ppc_cpu
->env
.nip
= spapr
->entry_point
;
683 static void spapr_cpu_reset(void *opaque
)
685 PowerPCCPU
*cpu
= opaque
;
686 CPUState
*cs
= CPU(cpu
);
687 CPUPPCState
*env
= &cpu
->env
;
691 /* All CPUs start halted. CPU0 is unhalted from the machine level
692 * reset code and the rest are explicitly started up by the guest
693 * using an RTAS call */
696 env
->spr
[SPR_HIOR
] = 0;
698 env
->external_htab
= (uint8_t *)spapr
->htab
;
700 env
->htab_mask
= HTAB_SIZE(spapr
) - 1;
701 env
->spr
[SPR_SDR1
] = (target_ulong
)(uintptr_t)spapr
->htab
|
702 (spapr
->htab_shift
- 18);
705 static void spapr_create_nvram(sPAPREnvironment
*spapr
)
707 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
708 const char *drivename
= qemu_opt_get(qemu_get_machine_opts(), "nvram");
711 BlockDriverState
*bs
;
713 bs
= bdrv_find(drivename
);
715 fprintf(stderr
, "No such block device \"%s\" for nvram\n",
719 qdev_prop_set_drive_nofail(dev
, "drive", bs
);
722 qdev_init_nofail(dev
);
724 spapr
->nvram
= (struct sPAPRNVRAM
*)dev
;
727 /* Returns whether we want to use VGA or not */
728 static int spapr_vga_init(PCIBus
*pci_bus
)
730 switch (vga_interface_type
) {
733 return pci_vga_init(pci_bus
) != NULL
;
735 fprintf(stderr
, "This vga model is not supported,"
736 "currently it only supports -vga std\n");
742 static const VMStateDescription vmstate_spapr
= {
745 .minimum_version_id
= 1,
746 .minimum_version_id_old
= 1,
747 .fields
= (VMStateField
[]) {
748 VMSTATE_UINT32(next_irq
, sPAPREnvironment
),
751 VMSTATE_UINT64(rtc_offset
, sPAPREnvironment
),
753 VMSTATE_END_OF_LIST()
757 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
758 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
759 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
760 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
762 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
764 sPAPREnvironment
*spapr
= opaque
;
766 /* "Iteration" header */
767 qemu_put_be32(f
, spapr
->htab_shift
);
770 spapr
->htab_save_index
= 0;
771 spapr
->htab_first_pass
= true;
773 assert(kvm_enabled());
775 spapr
->htab_fd
= kvmppc_get_htab_fd(false);
776 if (spapr
->htab_fd
< 0) {
777 fprintf(stderr
, "Unable to open fd for reading hash table from KVM: %s\n",
787 static void htab_save_first_pass(QEMUFile
*f
, sPAPREnvironment
*spapr
,
790 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
791 int index
= spapr
->htab_save_index
;
792 int64_t starttime
= qemu_get_clock_ns(rt_clock
);
794 assert(spapr
->htab_first_pass
);
799 /* Consume invalid HPTEs */
800 while ((index
< htabslots
)
801 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
803 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
806 /* Consume valid HPTEs */
808 while ((index
< htabslots
)
809 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
811 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
814 if (index
> chunkstart
) {
815 int n_valid
= index
- chunkstart
;
817 qemu_put_be32(f
, chunkstart
);
818 qemu_put_be16(f
, n_valid
);
820 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
821 HASH_PTE_SIZE_64
* n_valid
);
823 if ((qemu_get_clock_ns(rt_clock
) - starttime
) > max_ns
) {
827 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
829 if (index
>= htabslots
) {
830 assert(index
== htabslots
);
832 spapr
->htab_first_pass
= false;
834 spapr
->htab_save_index
= index
;
837 static int htab_save_later_pass(QEMUFile
*f
, sPAPREnvironment
*spapr
,
840 bool final
= max_ns
< 0;
841 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
842 int examined
= 0, sent
= 0;
843 int index
= spapr
->htab_save_index
;
844 int64_t starttime
= qemu_get_clock_ns(rt_clock
);
846 assert(!spapr
->htab_first_pass
);
849 int chunkstart
, invalidstart
;
851 /* Consume non-dirty HPTEs */
852 while ((index
< htabslots
)
853 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
859 /* Consume valid dirty HPTEs */
860 while ((index
< htabslots
)
861 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
862 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
863 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
868 invalidstart
= index
;
869 /* Consume invalid dirty HPTEs */
870 while ((index
< htabslots
)
871 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
872 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
873 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
878 if (index
> chunkstart
) {
879 int n_valid
= invalidstart
- chunkstart
;
880 int n_invalid
= index
- invalidstart
;
882 qemu_put_be32(f
, chunkstart
);
883 qemu_put_be16(f
, n_valid
);
884 qemu_put_be16(f
, n_invalid
);
885 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
886 HASH_PTE_SIZE_64
* n_valid
);
887 sent
+= index
- chunkstart
;
889 if (!final
&& (qemu_get_clock_ns(rt_clock
) - starttime
) > max_ns
) {
894 if (examined
>= htabslots
) {
898 if (index
>= htabslots
) {
899 assert(index
== htabslots
);
902 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
904 if (index
>= htabslots
) {
905 assert(index
== htabslots
);
909 spapr
->htab_save_index
= index
;
911 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
914 #define MAX_ITERATION_NS 5000000 /* 5 ms */
915 #define MAX_KVM_BUF_SIZE 2048
917 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
919 sPAPREnvironment
*spapr
= opaque
;
922 /* Iteration header */
926 assert(kvm_enabled());
928 rc
= kvmppc_save_htab(f
, spapr
->htab_fd
,
929 MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
933 } else if (spapr
->htab_first_pass
) {
934 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
936 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
947 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
949 sPAPREnvironment
*spapr
= opaque
;
951 /* Iteration header */
957 assert(kvm_enabled());
959 rc
= kvmppc_save_htab(f
, spapr
->htab_fd
, MAX_KVM_BUF_SIZE
, -1);
963 close(spapr
->htab_fd
);
966 htab_save_later_pass(f
, spapr
, -1);
977 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
979 sPAPREnvironment
*spapr
= opaque
;
980 uint32_t section_hdr
;
983 if (version_id
< 1 || version_id
> 1) {
984 fprintf(stderr
, "htab_load() bad version\n");
988 section_hdr
= qemu_get_be32(f
);
991 /* First section, just the hash shift */
992 if (spapr
->htab_shift
!= section_hdr
) {
999 assert(kvm_enabled());
1001 fd
= kvmppc_get_htab_fd(true);
1003 fprintf(stderr
, "Unable to open fd to restore KVM hash table: %s\n",
1010 uint16_t n_valid
, n_invalid
;
1012 index
= qemu_get_be32(f
);
1013 n_valid
= qemu_get_be16(f
);
1014 n_invalid
= qemu_get_be16(f
);
1016 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
1021 if ((index
+ n_valid
+ n_invalid
) >
1022 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
1023 /* Bad index in stream */
1024 fprintf(stderr
, "htab_load() bad index %d (%hd+%hd entries) "
1025 "in htab stream (htab_shift=%d)\n", index
, n_valid
, n_invalid
,
1032 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
1033 HASH_PTE_SIZE_64
* n_valid
);
1036 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
1037 HASH_PTE_SIZE_64
* n_invalid
);
1044 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
1059 static SaveVMHandlers savevm_htab_handlers
= {
1060 .save_live_setup
= htab_save_setup
,
1061 .save_live_iterate
= htab_save_iterate
,
1062 .save_live_complete
= htab_save_complete
,
1063 .load_state
= htab_load
,
1066 /* pSeries LPAR / sPAPR hardware init */
1067 static void ppc_spapr_init(QEMUMachineInitArgs
*args
)
1069 ram_addr_t ram_size
= args
->ram_size
;
1070 const char *cpu_model
= args
->cpu_model
;
1071 const char *kernel_filename
= args
->kernel_filename
;
1072 const char *kernel_cmdline
= args
->kernel_cmdline
;
1073 const char *initrd_filename
= args
->initrd_filename
;
1074 const char *boot_device
= args
->boot_device
;
1079 MemoryRegion
*sysmem
= get_system_memory();
1080 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1081 hwaddr rma_alloc_size
;
1082 uint32_t initrd_base
= 0;
1083 long kernel_size
= 0, initrd_size
= 0;
1084 long load_limit
, rtas_limit
, fw_size
;
1087 msi_supported
= true;
1089 spapr
= g_malloc0(sizeof(*spapr
));
1090 QLIST_INIT(&spapr
->phbs
);
1092 cpu_ppc_hypercall
= emulate_spapr_hypercall
;
1094 /* Allocate RMA if necessary */
1095 rma_alloc_size
= kvmppc_alloc_rma("ppc_spapr.rma", sysmem
);
1097 if (rma_alloc_size
== -1) {
1098 hw_error("qemu: Unable to create RMA\n");
1102 if (rma_alloc_size
&& (rma_alloc_size
< ram_size
)) {
1103 spapr
->rma_size
= rma_alloc_size
;
1105 spapr
->rma_size
= ram_size
;
1107 /* With KVM, we don't actually know whether KVM supports an
1108 * unbounded RMA (PR KVM) or is limited by the hash table size
1109 * (HV KVM using VRMA), so we always assume the latter
1111 * In that case, we also limit the initial allocations for RTAS
1112 * etc... to 256M since we have no way to know what the VRMA size
1113 * is going to be as it depends on the size of the hash table
1114 * isn't determined yet.
1116 if (kvm_enabled()) {
1117 spapr
->vrma_adjust
= 1;
1118 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
1122 /* We place the device tree and RTAS just below either the top of the RMA,
1123 * or just below 2GB, whichever is lowere, so that it can be
1124 * processed with 32-bit real mode code if necessary */
1125 rtas_limit
= MIN(spapr
->rma_size
, 0x80000000);
1126 spapr
->rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
1127 spapr
->fdt_addr
= spapr
->rtas_addr
- FDT_MAX_SIZE
;
1128 load_limit
= spapr
->fdt_addr
- FW_OVERHEAD
;
1130 /* We aim for a hash table of size 1/128 the size of RAM. The
1131 * normal rule of thumb is 1/64 the size of RAM, but that's much
1132 * more than needed for the Linux guests we support. */
1133 spapr
->htab_shift
= 18; /* Minimum architected size */
1134 while (spapr
->htab_shift
<= 46) {
1135 if ((1ULL << (spapr
->htab_shift
+ 7)) >= ram_size
) {
1138 spapr
->htab_shift
++;
1141 /* Set up Interrupt Controller before we create the VCPUs */
1142 spapr
->icp
= xics_system_init(smp_cpus
* kvmppc_smt_threads() / smp_threads
,
1144 spapr
->next_irq
= XICS_IRQ_BASE
;
1147 if (cpu_model
== NULL
) {
1148 cpu_model
= kvm_enabled() ? "host" : "POWER7";
1150 for (i
= 0; i
< smp_cpus
; i
++) {
1151 cpu
= cpu_ppc_init(cpu_model
);
1153 fprintf(stderr
, "Unable to find PowerPC CPU definition\n");
1158 xics_cpu_setup(spapr
->icp
, cpu
);
1160 /* Set time-base frequency to 512 MHz */
1161 cpu_ppc_tb_init(env
, TIMEBASE_FREQ
);
1163 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
1164 * MSR[IP] should never be set.
1166 env
->msr_mask
&= ~(1 << 6);
1168 /* Tell KVM that we're in PAPR mode */
1169 if (kvm_enabled()) {
1170 kvmppc_set_papr(cpu
);
1173 qemu_register_reset(spapr_cpu_reset
, cpu
);
1177 spapr
->ram_limit
= ram_size
;
1178 if (spapr
->ram_limit
> rma_alloc_size
) {
1179 ram_addr_t nonrma_base
= rma_alloc_size
;
1180 ram_addr_t nonrma_size
= spapr
->ram_limit
- rma_alloc_size
;
1182 memory_region_init_ram(ram
, NULL
, "ppc_spapr.ram", nonrma_size
);
1183 vmstate_register_ram_global(ram
);
1184 memory_region_add_subregion(sysmem
, nonrma_base
, ram
);
1187 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
1188 spapr
->rtas_size
= load_image_targphys(filename
, spapr
->rtas_addr
,
1189 rtas_limit
- spapr
->rtas_addr
);
1190 if (spapr
->rtas_size
< 0) {
1191 hw_error("qemu: could not load LPAR rtas '%s'\n", filename
);
1194 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
1195 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n",
1196 spapr
->rtas_size
, RTAS_MAX_SIZE
);
1201 /* Set up EPOW events infrastructure */
1202 spapr_events_init(spapr
);
1204 /* Set up VIO bus */
1205 spapr
->vio_bus
= spapr_vio_bus_init();
1207 for (i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
1208 if (serial_hds
[i
]) {
1209 spapr_vty_create(spapr
->vio_bus
, serial_hds
[i
]);
1213 /* We always have at least the nvram device on VIO */
1214 spapr_create_nvram(spapr
);
1217 spapr_pci_rtas_init();
1219 phb
= spapr_create_phb(spapr
, 0);
1221 for (i
= 0; i
< nb_nics
; i
++) {
1222 NICInfo
*nd
= &nd_table
[i
];
1225 nd
->model
= g_strdup("ibmveth");
1228 if (strcmp(nd
->model
, "ibmveth") == 0) {
1229 spapr_vlan_create(spapr
->vio_bus
, nd
);
1231 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
1235 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
1236 spapr_vscsi_create(spapr
->vio_bus
);
1240 if (spapr_vga_init(phb
->bus
)) {
1241 spapr
->has_graphics
= true;
1244 if (usb_enabled(spapr
->has_graphics
)) {
1245 pci_create_simple(phb
->bus
, -1, "pci-ohci");
1246 if (spapr
->has_graphics
) {
1247 usbdevice_create("keyboard");
1248 usbdevice_create("mouse");
1252 if (spapr
->rma_size
< (MIN_RMA_SLOF
<< 20)) {
1253 fprintf(stderr
, "qemu: pSeries SLOF firmware requires >= "
1254 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF
);
1258 if (kernel_filename
) {
1259 uint64_t lowaddr
= 0;
1261 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
1262 NULL
, &lowaddr
, NULL
, 1, ELF_MACHINE
, 0);
1263 if (kernel_size
< 0) {
1264 kernel_size
= load_image_targphys(kernel_filename
,
1266 load_limit
- KERNEL_LOAD_ADDR
);
1268 if (kernel_size
< 0) {
1269 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
1275 if (initrd_filename
) {
1276 /* Try to locate the initrd in the gap between the kernel
1277 * and the firmware. Add a bit of space just in case
1279 initrd_base
= (KERNEL_LOAD_ADDR
+ kernel_size
+ 0x1ffff) & ~0xffff;
1280 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
1281 load_limit
- initrd_base
);
1282 if (initrd_size
< 0) {
1283 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
1293 if (bios_name
== NULL
) {
1294 bios_name
= FW_FILE_NAME
;
1296 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1297 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
1299 hw_error("qemu: could not load LPAR rtas '%s'\n", filename
);
1304 spapr
->entry_point
= 0x100;
1306 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
1307 register_savevm_live(NULL
, "spapr/htab", -1, 1,
1308 &savevm_htab_handlers
, spapr
);
1310 /* Prepare the device tree */
1311 spapr
->fdt_skel
= spapr_create_fdt_skel(cpu_model
,
1312 initrd_base
, initrd_size
,
1314 boot_device
, kernel_cmdline
,
1316 assert(spapr
->fdt_skel
!= NULL
);
1319 static QEMUMachine spapr_machine
= {
1321 .desc
= "pSeries Logical Partition (PAPR compliant)",
1323 .init
= ppc_spapr_init
,
1324 .reset
= ppc_spapr_reset
,
1325 .block_default_type
= IF_SCSI
,
1326 .max_cpus
= MAX_CPUS
,
1331 static void spapr_machine_init(void)
1333 qemu_register_machine(&spapr_machine
);
1336 machine_init(spapr_machine_init
);