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[qemu.git] / hw / usb-ehci.c
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "hw.h"
26 #include "qemu-timer.h"
27 #include "usb.h"
28 #include "pci.h"
29 #include "monitor.h"
30 #include "trace.h"
31 #include "dma.h"
32
33 #define EHCI_DEBUG 0
34
35 #if EHCI_DEBUG
36 #define DPRINTF printf
37 #else
38 #define DPRINTF(...)
39 #endif
40
41 /* internal processing - reset HC to try and recover */
42 #define USB_RET_PROCERR (-99)
43
44 #define MMIO_SIZE 0x1000
45
46 /* Capability Registers Base Address - section 2.2 */
47 #define CAPREGBASE 0x0000
48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
52 #define EECP HCCPARAMS + 1
53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
55
56 #define OPREGBASE 0x0020 // Operational Registers Base Address
57
58 #define USBCMD OPREGBASE + 0x0000
59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
60 #define USBCMD_HCRESET (1 << 1) // HC Reset
61 #define USBCMD_FLS (3 << 2) // Frame List Size
62 #define USBCMD_FLS_SH 2 // Frame List Size Shift
63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
71
72 #define USBSTS OPREGBASE + 0x0004
73 #define USBSTS_RO_MASK 0x0000003f
74 #define USBSTS_INT (1 << 0) // USB Interrupt
75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
76 #define USBSTS_PCD (1 << 2) // Port Change Detect
77 #define USBSTS_FLR (1 << 3) // Frame List Rollover
78 #define USBSTS_HSE (1 << 4) // Host System Error
79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
80 #define USBSTS_HALT (1 << 12) // HC Halted
81 #define USBSTS_REC (1 << 13) // Reclamation
82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
84
85 /*
86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
87 * so no need to redefine here.
88 */
89 #define USBINTR OPREGBASE + 0x0008
90 #define USBINTR_MASK 0x0000003f
91
92 #define FRINDEX OPREGBASE + 0x000c
93 #define CTRLDSSEGMENT OPREGBASE + 0x0010
94 #define PERIODICLISTBASE OPREGBASE + 0x0014
95 #define ASYNCLISTADDR OPREGBASE + 0x0018
96 #define ASYNCLISTADDR_MASK 0xffffffe0
97
98 #define CONFIGFLAG OPREGBASE + 0x0040
99
100 #define PORTSC (OPREGBASE + 0x0044)
101 #define PORTSC_BEGIN PORTSC
102 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
103 /*
104 * Bits that are reserved or are read-only are masked out of values
105 * written to us by software
106 */
107 #define PORTSC_RO_MASK 0x007001c0
108 #define PORTSC_RWC_MASK 0x0000002a
109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
112 #define PORTSC_PTC (15 << 16) // Port Test Control
113 #define PORTSC_PTC_SH 16 // Port Test Control shift
114 #define PORTSC_PIC (3 << 14) // Port Indicator Control
115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
116 #define PORTSC_POWNER (1 << 13) // Port Owner
117 #define PORTSC_PPOWER (1 << 12) // Port Power
118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
120 #define PORTSC_PRESET (1 << 8) // Port Reset
121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
122 #define PORTSC_FPRES (1 << 6) // Force Port Resume
123 #define PORTSC_OCC (1 << 5) // Over Current Change
124 #define PORTSC_OCA (1 << 4) // Over Current Active
125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
126 #define PORTSC_PED (1 << 2) // Port Enable/Disable
127 #define PORTSC_CSC (1 << 1) // Connect Status Change
128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
129
130 #define FRAME_TIMER_FREQ 1000
131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
132
133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
134 #define NB_PORTS 6 // Number of downstream ports
135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
136 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
137 #define MAX_QH 100 // Max allowable queue heads in a chain
138
139 /* Internal periodic / asynchronous schedule state machine states
140 */
141 typedef enum {
142 EST_INACTIVE = 1000,
143 EST_ACTIVE,
144 EST_EXECUTING,
145 EST_SLEEPING,
146 /* The following states are internal to the state machine function
147 */
148 EST_WAITLISTHEAD,
149 EST_FETCHENTRY,
150 EST_FETCHQH,
151 EST_FETCHITD,
152 EST_ADVANCEQUEUE,
153 EST_FETCHQTD,
154 EST_EXECUTE,
155 EST_WRITEBACK,
156 EST_HORIZONTALQH
157 } EHCI_STATES;
158
159 /* macros for accessing fields within next link pointer entry */
160 #define NLPTR_GET(x) ((x) & 0xffffffe0)
161 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
162 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
163
164 /* link pointer types */
165 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
166 #define NLPTR_TYPE_QH 1 // queue head
167 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
168 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
169
170
171 /* EHCI spec version 1.0 Section 3.3
172 */
173 typedef struct EHCIitd {
174 uint32_t next;
175
176 uint32_t transact[8];
177 #define ITD_XACT_ACTIVE (1 << 31)
178 #define ITD_XACT_DBERROR (1 << 30)
179 #define ITD_XACT_BABBLE (1 << 29)
180 #define ITD_XACT_XACTERR (1 << 28)
181 #define ITD_XACT_LENGTH_MASK 0x0fff0000
182 #define ITD_XACT_LENGTH_SH 16
183 #define ITD_XACT_IOC (1 << 15)
184 #define ITD_XACT_PGSEL_MASK 0x00007000
185 #define ITD_XACT_PGSEL_SH 12
186 #define ITD_XACT_OFFSET_MASK 0x00000fff
187
188 uint32_t bufptr[7];
189 #define ITD_BUFPTR_MASK 0xfffff000
190 #define ITD_BUFPTR_SH 12
191 #define ITD_BUFPTR_EP_MASK 0x00000f00
192 #define ITD_BUFPTR_EP_SH 8
193 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
194 #define ITD_BUFPTR_DEVADDR_SH 0
195 #define ITD_BUFPTR_DIRECTION (1 << 11)
196 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
197 #define ITD_BUFPTR_MAXPKT_SH 0
198 #define ITD_BUFPTR_MULT_MASK 0x00000003
199 #define ITD_BUFPTR_MULT_SH 0
200 } EHCIitd;
201
202 /* EHCI spec version 1.0 Section 3.4
203 */
204 typedef struct EHCIsitd {
205 uint32_t next; // Standard next link pointer
206 uint32_t epchar;
207 #define SITD_EPCHAR_IO (1 << 31)
208 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
209 #define SITD_EPCHAR_PORTNUM_SH 24
210 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
211 #define SITD_EPCHAR_HUBADDR_SH 16
212 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
213 #define SITD_EPCHAR_EPNUM_SH 8
214 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
215
216 uint32_t uframe;
217 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
218 #define SITD_UFRAME_CMASK_SH 8
219 #define SITD_UFRAME_SMASK_MASK 0x000000ff
220
221 uint32_t results;
222 #define SITD_RESULTS_IOC (1 << 31)
223 #define SITD_RESULTS_PGSEL (1 << 30)
224 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
225 #define SITD_RESULTS_TYBYTES_SH 16
226 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
227 #define SITD_RESULTS_CPROGMASK_SH 8
228 #define SITD_RESULTS_ACTIVE (1 << 7)
229 #define SITD_RESULTS_ERR (1 << 6)
230 #define SITD_RESULTS_DBERR (1 << 5)
231 #define SITD_RESULTS_BABBLE (1 << 4)
232 #define SITD_RESULTS_XACTERR (1 << 3)
233 #define SITD_RESULTS_MISSEDUF (1 << 2)
234 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
235
236 uint32_t bufptr[2];
237 #define SITD_BUFPTR_MASK 0xfffff000
238 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
239 #define SITD_BUFPTR_TPOS_MASK 0x00000018
240 #define SITD_BUFPTR_TPOS_SH 3
241 #define SITD_BUFPTR_TCNT_MASK 0x00000007
242
243 uint32_t backptr; // Standard next link pointer
244 } EHCIsitd;
245
246 /* EHCI spec version 1.0 Section 3.5
247 */
248 typedef struct EHCIqtd {
249 uint32_t next; // Standard next link pointer
250 uint32_t altnext; // Standard next link pointer
251 uint32_t token;
252 #define QTD_TOKEN_DTOGGLE (1 << 31)
253 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
254 #define QTD_TOKEN_TBYTES_SH 16
255 #define QTD_TOKEN_IOC (1 << 15)
256 #define QTD_TOKEN_CPAGE_MASK 0x00007000
257 #define QTD_TOKEN_CPAGE_SH 12
258 #define QTD_TOKEN_CERR_MASK 0x00000c00
259 #define QTD_TOKEN_CERR_SH 10
260 #define QTD_TOKEN_PID_MASK 0x00000300
261 #define QTD_TOKEN_PID_SH 8
262 #define QTD_TOKEN_ACTIVE (1 << 7)
263 #define QTD_TOKEN_HALT (1 << 6)
264 #define QTD_TOKEN_DBERR (1 << 5)
265 #define QTD_TOKEN_BABBLE (1 << 4)
266 #define QTD_TOKEN_XACTERR (1 << 3)
267 #define QTD_TOKEN_MISSEDUF (1 << 2)
268 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
269 #define QTD_TOKEN_PING (1 << 0)
270
271 uint32_t bufptr[5]; // Standard buffer pointer
272 #define QTD_BUFPTR_MASK 0xfffff000
273 #define QTD_BUFPTR_SH 12
274 } EHCIqtd;
275
276 /* EHCI spec version 1.0 Section 3.6
277 */
278 typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
280
281 /* endpoint characteristics */
282 uint32_t epchar;
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
296
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
302
303 /* endpoint capabilities */
304 uint32_t epcap;
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
315
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
321
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
328 } EHCIqh;
329
330 /* EHCI spec version 1.0 Section 3.7
331 */
332 typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335 } EHCIfstn;
336
337 typedef struct EHCIQueue EHCIQueue;
338 typedef struct EHCIState EHCIState;
339
340 enum async_state {
341 EHCI_ASYNC_NONE = 0,
342 EHCI_ASYNC_INFLIGHT,
343 EHCI_ASYNC_FINISHED,
344 };
345
346 struct EHCIQueue {
347 EHCIState *ehci;
348 QTAILQ_ENTRY(EHCIQueue) next;
349 bool async_schedule;
350 uint32_t seen;
351 uint64_t ts;
352
353 /* cached data from guest - needs to be flushed
354 * when guest removes an entry (doorbell, handshake sequence)
355 */
356 EHCIqh qh; // copy of current QH (being worked on)
357 uint32_t qhaddr; // address QH read from
358 EHCIqtd qtd; // copy of current QTD (being worked on)
359 uint32_t qtdaddr; // address QTD read from
360
361 USBPacket packet;
362 QEMUSGList sgl;
363 int pid;
364 uint32_t tbytes;
365 enum async_state async;
366 int usb_status;
367 };
368
369 struct EHCIState {
370 PCIDevice dev;
371 USBBus bus;
372 qemu_irq irq;
373 MemoryRegion mem;
374 int companion_count;
375
376 /* properties */
377 uint32_t freq;
378 uint32_t maxframes;
379
380 /*
381 * EHCI spec version 1.0 Section 2.3
382 * Host Controller Operational Registers
383 */
384 union {
385 uint8_t mmio[MMIO_SIZE];
386 struct {
387 uint8_t cap[OPREGBASE];
388 uint32_t usbcmd;
389 uint32_t usbsts;
390 uint32_t usbintr;
391 uint32_t frindex;
392 uint32_t ctrldssegment;
393 uint32_t periodiclistbase;
394 uint32_t asynclistaddr;
395 uint32_t notused[9];
396 uint32_t configflag;
397 uint32_t portsc[NB_PORTS];
398 };
399 };
400
401 /*
402 * Internal states, shadow registers, etc
403 */
404 uint32_t sofv;
405 QEMUTimer *frame_timer;
406 int attach_poll_counter;
407 int astate; // Current state in asynchronous schedule
408 int pstate; // Current state in periodic schedule
409 USBPort ports[NB_PORTS];
410 USBPort *companion_ports[NB_PORTS];
411 uint32_t usbsts_pending;
412 QTAILQ_HEAD(, EHCIQueue) queues;
413
414 uint32_t a_fetch_addr; // which address to look at next
415 uint32_t p_fetch_addr; // which address to look at next
416
417 USBPacket ipacket;
418 QEMUSGList isgl;
419 int isoch_pause;
420
421 uint64_t last_run_ns;
422 };
423
424 #define SET_LAST_RUN_CLOCK(s) \
425 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
426
427 /* nifty macros from Arnon's EHCI version */
428 #define get_field(data, field) \
429 (((data) & field##_MASK) >> field##_SH)
430
431 #define set_field(data, newval, field) do { \
432 uint32_t val = *data; \
433 val &= ~ field##_MASK; \
434 val |= ((newval) << field##_SH) & field##_MASK; \
435 *data = val; \
436 } while(0)
437
438 static const char *ehci_state_names[] = {
439 [ EST_INACTIVE ] = "INACTIVE",
440 [ EST_ACTIVE ] = "ACTIVE",
441 [ EST_EXECUTING ] = "EXECUTING",
442 [ EST_SLEEPING ] = "SLEEPING",
443 [ EST_WAITLISTHEAD ] = "WAITLISTHEAD",
444 [ EST_FETCHENTRY ] = "FETCH ENTRY",
445 [ EST_FETCHQH ] = "FETCH QH",
446 [ EST_FETCHITD ] = "FETCH ITD",
447 [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE",
448 [ EST_FETCHQTD ] = "FETCH QTD",
449 [ EST_EXECUTE ] = "EXECUTE",
450 [ EST_WRITEBACK ] = "WRITEBACK",
451 [ EST_HORIZONTALQH ] = "HORIZONTALQH",
452 };
453
454 static const char *ehci_mmio_names[] = {
455 [ CAPLENGTH ] = "CAPLENGTH",
456 [ HCIVERSION ] = "HCIVERSION",
457 [ HCSPARAMS ] = "HCSPARAMS",
458 [ HCCPARAMS ] = "HCCPARAMS",
459 [ USBCMD ] = "USBCMD",
460 [ USBSTS ] = "USBSTS",
461 [ USBINTR ] = "USBINTR",
462 [ FRINDEX ] = "FRINDEX",
463 [ PERIODICLISTBASE ] = "P-LIST BASE",
464 [ ASYNCLISTADDR ] = "A-LIST ADDR",
465 [ PORTSC_BEGIN ] = "PORTSC #0",
466 [ PORTSC_BEGIN + 4] = "PORTSC #1",
467 [ PORTSC_BEGIN + 8] = "PORTSC #2",
468 [ PORTSC_BEGIN + 12] = "PORTSC #3",
469 [ CONFIGFLAG ] = "CONFIGFLAG",
470 };
471
472 static const char *nr2str(const char **n, size_t len, uint32_t nr)
473 {
474 if (nr < len && n[nr] != NULL) {
475 return n[nr];
476 } else {
477 return "unknown";
478 }
479 }
480
481 static const char *state2str(uint32_t state)
482 {
483 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
484 }
485
486 static const char *addr2str(target_phys_addr_t addr)
487 {
488 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
489 }
490
491 static void ehci_trace_usbsts(uint32_t mask, int state)
492 {
493 /* interrupts */
494 if (mask & USBSTS_INT) {
495 trace_usb_ehci_usbsts("INT", state);
496 }
497 if (mask & USBSTS_ERRINT) {
498 trace_usb_ehci_usbsts("ERRINT", state);
499 }
500 if (mask & USBSTS_PCD) {
501 trace_usb_ehci_usbsts("PCD", state);
502 }
503 if (mask & USBSTS_FLR) {
504 trace_usb_ehci_usbsts("FLR", state);
505 }
506 if (mask & USBSTS_HSE) {
507 trace_usb_ehci_usbsts("HSE", state);
508 }
509 if (mask & USBSTS_IAA) {
510 trace_usb_ehci_usbsts("IAA", state);
511 }
512
513 /* status */
514 if (mask & USBSTS_HALT) {
515 trace_usb_ehci_usbsts("HALT", state);
516 }
517 if (mask & USBSTS_REC) {
518 trace_usb_ehci_usbsts("REC", state);
519 }
520 if (mask & USBSTS_PSS) {
521 trace_usb_ehci_usbsts("PSS", state);
522 }
523 if (mask & USBSTS_ASS) {
524 trace_usb_ehci_usbsts("ASS", state);
525 }
526 }
527
528 static inline void ehci_set_usbsts(EHCIState *s, int mask)
529 {
530 if ((s->usbsts & mask) == mask) {
531 return;
532 }
533 ehci_trace_usbsts(mask, 1);
534 s->usbsts |= mask;
535 }
536
537 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
538 {
539 if ((s->usbsts & mask) == 0) {
540 return;
541 }
542 ehci_trace_usbsts(mask, 0);
543 s->usbsts &= ~mask;
544 }
545
546 static inline void ehci_set_interrupt(EHCIState *s, int intr)
547 {
548 int level = 0;
549
550 // TODO honour interrupt threshold requests
551
552 ehci_set_usbsts(s, intr);
553
554 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
555 level = 1;
556 }
557
558 qemu_set_irq(s->irq, level);
559 }
560
561 static inline void ehci_record_interrupt(EHCIState *s, int intr)
562 {
563 s->usbsts_pending |= intr;
564 }
565
566 static inline void ehci_commit_interrupt(EHCIState *s)
567 {
568 if (!s->usbsts_pending) {
569 return;
570 }
571 ehci_set_interrupt(s, s->usbsts_pending);
572 s->usbsts_pending = 0;
573 }
574
575 static void ehci_set_state(EHCIState *s, int async, int state)
576 {
577 if (async) {
578 trace_usb_ehci_state("async", state2str(state));
579 s->astate = state;
580 } else {
581 trace_usb_ehci_state("periodic", state2str(state));
582 s->pstate = state;
583 }
584 }
585
586 static int ehci_get_state(EHCIState *s, int async)
587 {
588 return async ? s->astate : s->pstate;
589 }
590
591 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
592 {
593 if (async) {
594 s->a_fetch_addr = addr;
595 } else {
596 s->p_fetch_addr = addr;
597 }
598 }
599
600 static int ehci_get_fetch_addr(EHCIState *s, int async)
601 {
602 return async ? s->a_fetch_addr : s->p_fetch_addr;
603 }
604
605 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
606 {
607 /* need three here due to argument count limits */
608 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
609 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
610 trace_usb_ehci_qh_fields(addr,
611 get_field(qh->epchar, QH_EPCHAR_RL),
612 get_field(qh->epchar, QH_EPCHAR_MPLEN),
613 get_field(qh->epchar, QH_EPCHAR_EPS),
614 get_field(qh->epchar, QH_EPCHAR_EP),
615 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
616 trace_usb_ehci_qh_bits(addr,
617 (bool)(qh->epchar & QH_EPCHAR_C),
618 (bool)(qh->epchar & QH_EPCHAR_H),
619 (bool)(qh->epchar & QH_EPCHAR_DTC),
620 (bool)(qh->epchar & QH_EPCHAR_I));
621 }
622
623 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
624 {
625 /* need three here due to argument count limits */
626 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
627 trace_usb_ehci_qtd_fields(addr,
628 get_field(qtd->token, QTD_TOKEN_TBYTES),
629 get_field(qtd->token, QTD_TOKEN_CPAGE),
630 get_field(qtd->token, QTD_TOKEN_CERR),
631 get_field(qtd->token, QTD_TOKEN_PID));
632 trace_usb_ehci_qtd_bits(addr,
633 (bool)(qtd->token & QTD_TOKEN_IOC),
634 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
635 (bool)(qtd->token & QTD_TOKEN_HALT),
636 (bool)(qtd->token & QTD_TOKEN_BABBLE),
637 (bool)(qtd->token & QTD_TOKEN_XACTERR));
638 }
639
640 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
641 {
642 trace_usb_ehci_itd(addr, itd->next,
643 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
644 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
645 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
646 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
647 }
648
649 /* queue management */
650
651 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async)
652 {
653 EHCIQueue *q;
654
655 q = qemu_mallocz(sizeof(*q));
656 q->ehci = ehci;
657 q->async_schedule = async;
658 QTAILQ_INSERT_HEAD(&ehci->queues, q, next);
659 trace_usb_ehci_queue_action(q, "alloc");
660 return q;
661 }
662
663 static void ehci_free_queue(EHCIQueue *q)
664 {
665 trace_usb_ehci_queue_action(q, "free");
666 if (q->async == EHCI_ASYNC_INFLIGHT) {
667 usb_cancel_packet(&q->packet);
668 }
669 QTAILQ_REMOVE(&q->ehci->queues, q, next);
670 qemu_free(q);
671 }
672
673 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr)
674 {
675 EHCIQueue *q;
676
677 QTAILQ_FOREACH(q, &ehci->queues, next) {
678 if (addr == q->qhaddr) {
679 return q;
680 }
681 }
682 return NULL;
683 }
684
685 static void ehci_queues_rip_unused(EHCIState *ehci)
686 {
687 EHCIQueue *q, *tmp;
688
689 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
690 if (q->seen) {
691 q->seen = 0;
692 q->ts = ehci->last_run_ns;
693 continue;
694 }
695 if (ehci->last_run_ns < q->ts + 250000000) {
696 /* allow 0.25 sec idle */
697 continue;
698 }
699 ehci_free_queue(q);
700 }
701 }
702
703 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev)
704 {
705 EHCIQueue *q, *tmp;
706
707 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
708 if (q->packet.owner != dev) {
709 continue;
710 }
711 ehci_free_queue(q);
712 }
713 }
714
715 static void ehci_queues_rip_all(EHCIState *ehci)
716 {
717 EHCIQueue *q, *tmp;
718
719 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
720 ehci_free_queue(q);
721 }
722 }
723
724 /* Attach or detach a device on root hub */
725
726 static void ehci_attach(USBPort *port)
727 {
728 EHCIState *s = port->opaque;
729 uint32_t *portsc = &s->portsc[port->index];
730
731 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
732
733 if (*portsc & PORTSC_POWNER) {
734 USBPort *companion = s->companion_ports[port->index];
735 companion->dev = port->dev;
736 companion->ops->attach(companion);
737 return;
738 }
739
740 *portsc |= PORTSC_CONNECT;
741 *portsc |= PORTSC_CSC;
742
743 ehci_set_interrupt(s, USBSTS_PCD);
744 }
745
746 static void ehci_detach(USBPort *port)
747 {
748 EHCIState *s = port->opaque;
749 uint32_t *portsc = &s->portsc[port->index];
750
751 trace_usb_ehci_port_detach(port->index);
752
753 if (*portsc & PORTSC_POWNER) {
754 USBPort *companion = s->companion_ports[port->index];
755 companion->ops->detach(companion);
756 companion->dev = NULL;
757 return;
758 }
759
760 ehci_queues_rip_device(s, port->dev);
761
762 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
763 *portsc |= PORTSC_CSC;
764
765 ehci_set_interrupt(s, USBSTS_PCD);
766 }
767
768 static void ehci_child_detach(USBPort *port, USBDevice *child)
769 {
770 EHCIState *s = port->opaque;
771 uint32_t portsc = s->portsc[port->index];
772
773 if (portsc & PORTSC_POWNER) {
774 USBPort *companion = s->companion_ports[port->index];
775 companion->ops->child_detach(companion, child);
776 companion->dev = NULL;
777 return;
778 }
779
780 ehci_queues_rip_device(s, child);
781 }
782
783 static void ehci_wakeup(USBPort *port)
784 {
785 EHCIState *s = port->opaque;
786 uint32_t portsc = s->portsc[port->index];
787
788 if (portsc & PORTSC_POWNER) {
789 USBPort *companion = s->companion_ports[port->index];
790 if (companion->ops->wakeup) {
791 companion->ops->wakeup(companion);
792 }
793 }
794 }
795
796 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
797 uint32_t portcount, uint32_t firstport)
798 {
799 EHCIState *s = container_of(bus, EHCIState, bus);
800 uint32_t i;
801
802 if (firstport + portcount > NB_PORTS) {
803 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
804 "firstport on masterbus");
805 error_printf_unless_qmp(
806 "firstport value of %u makes companion take ports %u - %u, which "
807 "is outside of the valid range of 0 - %u\n", firstport, firstport,
808 firstport + portcount - 1, NB_PORTS - 1);
809 return -1;
810 }
811
812 for (i = 0; i < portcount; i++) {
813 if (s->companion_ports[firstport + i]) {
814 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
815 "an USB masterbus");
816 error_printf_unless_qmp(
817 "port %u on masterbus %s already has a companion assigned\n",
818 firstport + i, bus->qbus.name);
819 return -1;
820 }
821 }
822
823 for (i = 0; i < portcount; i++) {
824 s->companion_ports[firstport + i] = ports[i];
825 s->ports[firstport + i].speedmask |=
826 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
827 /* Ensure devs attached before the initial reset go to the companion */
828 s->portsc[firstport + i] = PORTSC_POWNER;
829 }
830
831 s->companion_count++;
832 s->mmio[0x05] = (s->companion_count << 4) | portcount;
833
834 return 0;
835 }
836
837 /* 4.1 host controller initialization */
838 static void ehci_reset(void *opaque)
839 {
840 EHCIState *s = opaque;
841 int i;
842 USBDevice *devs[NB_PORTS];
843
844 trace_usb_ehci_reset();
845
846 /*
847 * Do the detach before touching portsc, so that it correctly gets send to
848 * us or to our companion based on PORTSC_POWNER before the reset.
849 */
850 for(i = 0; i < NB_PORTS; i++) {
851 devs[i] = s->ports[i].dev;
852 if (devs[i]) {
853 usb_attach(&s->ports[i], NULL);
854 }
855 }
856
857 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
858
859 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
860 s->usbsts = USBSTS_HALT;
861
862 s->astate = EST_INACTIVE;
863 s->pstate = EST_INACTIVE;
864 s->isoch_pause = -1;
865 s->attach_poll_counter = 0;
866
867 for(i = 0; i < NB_PORTS; i++) {
868 if (s->companion_ports[i]) {
869 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
870 } else {
871 s->portsc[i] = PORTSC_PPOWER;
872 }
873 if (devs[i]) {
874 usb_attach(&s->ports[i], devs[i]);
875 }
876 }
877 ehci_queues_rip_all(s);
878 }
879
880 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
881 {
882 EHCIState *s = ptr;
883 uint32_t val;
884
885 val = s->mmio[addr];
886
887 return val;
888 }
889
890 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
891 {
892 EHCIState *s = ptr;
893 uint32_t val;
894
895 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
896
897 return val;
898 }
899
900 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
901 {
902 EHCIState *s = ptr;
903 uint32_t val;
904
905 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
906 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
907
908 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
909 return val;
910 }
911
912 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
913 {
914 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
915 exit(1);
916 }
917
918 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
919 {
920 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
921 exit(1);
922 }
923
924 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
925 {
926 USBDevice *dev = s->ports[port].dev;
927 uint32_t *portsc = &s->portsc[port];
928 uint32_t orig;
929
930 if (s->companion_ports[port] == NULL)
931 return;
932
933 owner = owner & PORTSC_POWNER;
934 orig = *portsc & PORTSC_POWNER;
935
936 if (!(owner ^ orig)) {
937 return;
938 }
939
940 if (dev) {
941 usb_attach(&s->ports[port], NULL);
942 }
943
944 *portsc &= ~PORTSC_POWNER;
945 *portsc |= owner;
946
947 if (dev) {
948 usb_attach(&s->ports[port], dev);
949 }
950 }
951
952 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
953 {
954 uint32_t *portsc = &s->portsc[port];
955 USBDevice *dev = s->ports[port].dev;
956
957 /* Clear rwc bits */
958 *portsc &= ~(val & PORTSC_RWC_MASK);
959 /* The guest may clear, but not set the PED bit */
960 *portsc &= val | ~PORTSC_PED;
961 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
962 handle_port_owner_write(s, port, val);
963 /* And finally apply RO_MASK */
964 val &= PORTSC_RO_MASK;
965
966 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
967 trace_usb_ehci_port_reset(port, 1);
968 }
969
970 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
971 trace_usb_ehci_port_reset(port, 0);
972 if (dev) {
973 usb_attach(&s->ports[port], dev);
974 usb_send_msg(dev, USB_MSG_RESET);
975 *portsc &= ~PORTSC_CSC;
976 }
977
978 /*
979 * Table 2.16 Set the enable bit(and enable bit change) to indicate
980 * to SW that this port has a high speed device attached
981 */
982 if (dev && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
983 val |= PORTSC_PED;
984 }
985 }
986
987 *portsc &= ~PORTSC_RO_MASK;
988 *portsc |= val;
989 }
990
991 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
992 {
993 EHCIState *s = ptr;
994 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
995 uint32_t old = *mmio;
996 int i;
997
998 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
999
1000 /* Only aligned reads are allowed on OHCI */
1001 if (addr & 3) {
1002 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
1003 TARGET_FMT_plx "\n", addr);
1004 return;
1005 }
1006
1007 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
1008 handle_port_status_write(s, (addr-PORTSC)/4, val);
1009 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1010 return;
1011 }
1012
1013 if (addr < OPREGBASE) {
1014 fprintf(stderr, "usb-ehci: write attempt to read-only register"
1015 TARGET_FMT_plx "\n", addr);
1016 return;
1017 }
1018
1019
1020 /* Do any register specific pre-write processing here. */
1021 switch(addr) {
1022 case USBCMD:
1023 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
1024 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
1025 SET_LAST_RUN_CLOCK(s);
1026 ehci_clear_usbsts(s, USBSTS_HALT);
1027 }
1028
1029 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
1030 qemu_del_timer(s->frame_timer);
1031 // TODO - should finish out some stuff before setting halt
1032 ehci_set_usbsts(s, USBSTS_HALT);
1033 }
1034
1035 if (val & USBCMD_HCRESET) {
1036 ehci_reset(s);
1037 val &= ~USBCMD_HCRESET;
1038 }
1039
1040 /* not supporting dynamic frame list size at the moment */
1041 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1042 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1043 val & USBCMD_FLS);
1044 val &= ~USBCMD_FLS;
1045 }
1046 break;
1047
1048 case USBSTS:
1049 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
1050 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
1051 val = s->usbsts;
1052 ehci_set_interrupt(s, 0);
1053 break;
1054
1055 case USBINTR:
1056 val &= USBINTR_MASK;
1057 break;
1058
1059 case FRINDEX:
1060 s->sofv = val >> 3;
1061 break;
1062
1063 case CONFIGFLAG:
1064 val &= 0x1;
1065 if (val) {
1066 for(i = 0; i < NB_PORTS; i++)
1067 handle_port_owner_write(s, i, 0);
1068 }
1069 break;
1070
1071 case PERIODICLISTBASE:
1072 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
1073 fprintf(stderr,
1074 "ehci: PERIODIC list base register set while periodic schedule\n"
1075 " is enabled and HC is enabled\n");
1076 }
1077 break;
1078
1079 case ASYNCLISTADDR:
1080 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
1081 fprintf(stderr,
1082 "ehci: ASYNC list address register set while async schedule\n"
1083 " is enabled and HC is enabled\n");
1084 }
1085 break;
1086 }
1087
1088 *mmio = val;
1089 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1090 }
1091
1092
1093 // TODO : Put in common header file, duplication from usb-ohci.c
1094
1095 /* Get an array of dwords from main memory */
1096 static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
1097 {
1098 int i;
1099
1100 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1101 cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0);
1102 *buf = le32_to_cpu(*buf);
1103 }
1104
1105 return 1;
1106 }
1107
1108 /* Put an array of dwords in to main memory */
1109 static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
1110 {
1111 int i;
1112
1113 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1114 uint32_t tmp = cpu_to_le32(*buf);
1115 cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1);
1116 }
1117
1118 return 1;
1119 }
1120
1121 // 4.10.2
1122
1123 static int ehci_qh_do_overlay(EHCIQueue *q)
1124 {
1125 int i;
1126 int dtoggle;
1127 int ping;
1128 int eps;
1129 int reload;
1130
1131 // remember values in fields to preserve in qh after overlay
1132
1133 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1134 ping = q->qh.token & QTD_TOKEN_PING;
1135
1136 q->qh.current_qtd = q->qtdaddr;
1137 q->qh.next_qtd = q->qtd.next;
1138 q->qh.altnext_qtd = q->qtd.altnext;
1139 q->qh.token = q->qtd.token;
1140
1141
1142 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1143 if (eps == EHCI_QH_EPS_HIGH) {
1144 q->qh.token &= ~QTD_TOKEN_PING;
1145 q->qh.token |= ping;
1146 }
1147
1148 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1149 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1150
1151 for (i = 0; i < 5; i++) {
1152 q->qh.bufptr[i] = q->qtd.bufptr[i];
1153 }
1154
1155 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1156 // preserve QH DT bit
1157 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1158 q->qh.token |= dtoggle;
1159 }
1160
1161 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1162 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1163
1164 put_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1165
1166 return 0;
1167 }
1168
1169 static int ehci_init_transfer(EHCIQueue *q)
1170 {
1171 uint32_t cpage, offset, bytes, plen;
1172 target_phys_addr_t page;
1173
1174 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1175 bytes = get_field(q->qh.token, QTD_TOKEN_TBYTES);
1176 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1177 qemu_sglist_init(&q->sgl, 5);
1178
1179 while (bytes > 0) {
1180 if (cpage > 4) {
1181 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1182 return USB_RET_PROCERR;
1183 }
1184
1185 page = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK;
1186 page += offset;
1187 plen = bytes;
1188 if (plen > 4096 - offset) {
1189 plen = 4096 - offset;
1190 offset = 0;
1191 cpage++;
1192 }
1193
1194 qemu_sglist_add(&q->sgl, page, plen);
1195 bytes -= plen;
1196 }
1197 return 0;
1198 }
1199
1200 static void ehci_finish_transfer(EHCIQueue *q, int status)
1201 {
1202 uint32_t cpage, offset;
1203
1204 qemu_sglist_destroy(&q->sgl);
1205
1206 if (status > 0) {
1207 /* update cpage & offset */
1208 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1209 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1210
1211 offset += status;
1212 cpage += offset >> QTD_BUFPTR_SH;
1213 offset &= ~QTD_BUFPTR_MASK;
1214
1215 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1216 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1217 q->qh.bufptr[0] |= offset;
1218 }
1219 }
1220
1221 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1222 {
1223 EHCIQueue *q;
1224 EHCIState *s = port->opaque;
1225 uint32_t portsc = s->portsc[port->index];
1226
1227 if (portsc & PORTSC_POWNER) {
1228 USBPort *companion = s->companion_ports[port->index];
1229 companion->ops->complete(companion, packet);
1230 return;
1231 }
1232
1233 q = container_of(packet, EHCIQueue, packet);
1234 trace_usb_ehci_queue_action(q, "wakeup");
1235 assert(q->async == EHCI_ASYNC_INFLIGHT);
1236 q->async = EHCI_ASYNC_FINISHED;
1237 q->usb_status = packet->result;
1238 }
1239
1240 static void ehci_execute_complete(EHCIQueue *q)
1241 {
1242 int c_err, reload;
1243
1244 assert(q->async != EHCI_ASYNC_INFLIGHT);
1245 q->async = EHCI_ASYNC_NONE;
1246
1247 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1248 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1249
1250 if (q->usb_status < 0) {
1251 err:
1252 /* TO-DO: put this is in a function that can be invoked below as well */
1253 c_err = get_field(q->qh.token, QTD_TOKEN_CERR);
1254 c_err--;
1255 set_field(&q->qh.token, c_err, QTD_TOKEN_CERR);
1256
1257 switch(q->usb_status) {
1258 case USB_RET_NODEV:
1259 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1260 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1261 break;
1262 case USB_RET_STALL:
1263 q->qh.token |= QTD_TOKEN_HALT;
1264 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1265 break;
1266 case USB_RET_NAK:
1267 /* 4.10.3 */
1268 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1269 if ((q->pid == USB_TOKEN_IN) && reload) {
1270 int nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1271 nakcnt--;
1272 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1273 } else if (!reload) {
1274 return;
1275 }
1276 break;
1277 case USB_RET_BABBLE:
1278 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1279 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1280 break;
1281 default:
1282 /* should not be triggerable */
1283 fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status);
1284 assert(0);
1285 break;
1286 }
1287 } else {
1288 // DPRINTF("Short packet condition\n");
1289 // TODO check 4.12 for splits
1290
1291 if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) {
1292 q->usb_status = USB_RET_BABBLE;
1293 goto err;
1294 }
1295
1296 if (q->tbytes && q->pid == USB_TOKEN_IN) {
1297 q->tbytes -= q->usb_status;
1298 } else {
1299 q->tbytes = 0;
1300 }
1301
1302 DPRINTF("updating tbytes to %d\n", q->tbytes);
1303 set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES);
1304 }
1305 ehci_finish_transfer(q, q->usb_status);
1306 usb_packet_unmap(&q->packet);
1307
1308 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1309 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1310
1311 if ((q->usb_status >= 0) && (q->qh.token & QTD_TOKEN_IOC)) {
1312 ehci_record_interrupt(q->ehci, USBSTS_INT);
1313 }
1314 }
1315
1316 // 4.10.3
1317
1318 static int ehci_execute(EHCIQueue *q)
1319 {
1320 USBPort *port;
1321 USBDevice *dev;
1322 int ret;
1323 int i;
1324 int endp;
1325 int devadr;
1326
1327 if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) {
1328 fprintf(stderr, "Attempting to execute inactive QH\n");
1329 return USB_RET_PROCERR;
1330 }
1331
1332 q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1333 if (q->tbytes > BUFF_SIZE) {
1334 fprintf(stderr, "Request for more bytes than allowed\n");
1335 return USB_RET_PROCERR;
1336 }
1337
1338 q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1339 switch(q->pid) {
1340 case 0: q->pid = USB_TOKEN_OUT; break;
1341 case 1: q->pid = USB_TOKEN_IN; break;
1342 case 2: q->pid = USB_TOKEN_SETUP; break;
1343 default: fprintf(stderr, "bad token\n"); break;
1344 }
1345
1346 if (ehci_init_transfer(q) != 0) {
1347 return USB_RET_PROCERR;
1348 }
1349
1350 endp = get_field(q->qh.epchar, QH_EPCHAR_EP);
1351 devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1352
1353 ret = USB_RET_NODEV;
1354
1355 usb_packet_setup(&q->packet, q->pid, devadr, endp);
1356 usb_packet_map(&q->packet, &q->sgl);
1357
1358 // TO-DO: associating device with ehci port
1359 for(i = 0; i < NB_PORTS; i++) {
1360 port = &q->ehci->ports[i];
1361 dev = port->dev;
1362
1363 if (!(q->ehci->portsc[i] &(PORTSC_CONNECT))) {
1364 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1365 i, q->ehci->portsc[i]);
1366 continue;
1367 }
1368
1369 ret = usb_handle_packet(dev, &q->packet);
1370
1371 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1372 "(total %d) endp %x ret %d\n",
1373 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1374 q->packet.iov.size, q->tbytes, endp, ret);
1375
1376 if (ret != USB_RET_NODEV) {
1377 break;
1378 }
1379 }
1380
1381 if (ret > BUFF_SIZE) {
1382 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1383 return USB_RET_PROCERR;
1384 }
1385
1386 return ret;
1387 }
1388
1389 /* 4.7.2
1390 */
1391
1392 static int ehci_process_itd(EHCIState *ehci,
1393 EHCIitd *itd)
1394 {
1395 USBPort *port;
1396 USBDevice *dev;
1397 int ret;
1398 uint32_t i, j, len, pid, dir, devaddr, endp;
1399 uint32_t pg, off, ptr1, ptr2, max, mult;
1400
1401 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1402 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1403 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1404 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1405 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1406
1407 for(i = 0; i < 8; i++) {
1408 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1409 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1410 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1411 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1412 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1413 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1414
1415 if (len > max * mult) {
1416 len = max * mult;
1417 }
1418
1419 if (len > BUFF_SIZE) {
1420 return USB_RET_PROCERR;
1421 }
1422
1423 qemu_sglist_init(&ehci->isgl, 2);
1424 if (off + len > 4096) {
1425 /* transfer crosses page border */
1426 uint32_t len2 = off + len - 4096;
1427 uint32_t len1 = len - len2;
1428 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1429 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1430 } else {
1431 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1432 }
1433
1434 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1435
1436 usb_packet_setup(&ehci->ipacket, pid, devaddr, endp);
1437 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1438
1439 ret = USB_RET_NODEV;
1440 for (j = 0; j < NB_PORTS; j++) {
1441 port = &ehci->ports[j];
1442 dev = port->dev;
1443
1444 if (!(ehci->portsc[j] &(PORTSC_CONNECT))) {
1445 continue;
1446 }
1447
1448 ret = usb_handle_packet(dev, &ehci->ipacket);
1449
1450 if (ret != USB_RET_NODEV) {
1451 break;
1452 }
1453 }
1454
1455 usb_packet_unmap(&ehci->ipacket);
1456 qemu_sglist_destroy(&ehci->isgl);
1457
1458 #if 0
1459 /* In isoch, there is no facility to indicate a NAK so let's
1460 * instead just complete a zero-byte transaction. Setting
1461 * DBERR seems too draconian.
1462 */
1463
1464 if (ret == USB_RET_NAK) {
1465 if (ehci->isoch_pause > 0) {
1466 DPRINTF("ISOCH: received a NAK but paused so returning\n");
1467 ehci->isoch_pause--;
1468 return 0;
1469 } else if (ehci->isoch_pause == -1) {
1470 DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
1471 // Pause frindex for up to 50 msec waiting for data from
1472 // remote
1473 ehci->isoch_pause = 50;
1474 return 0;
1475 } else {
1476 DPRINTF("ISOCH: isoch pause timeout! return 0\n");
1477 ret = 0;
1478 }
1479 } else {
1480 DPRINTF("ISOCH: received ACK, clearing pause\n");
1481 ehci->isoch_pause = -1;
1482 }
1483 #else
1484 if (ret == USB_RET_NAK) {
1485 ret = 0;
1486 }
1487 #endif
1488
1489 if (ret >= 0) {
1490 if (!dir) {
1491 /* OUT */
1492 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1493 } else {
1494 /* IN */
1495 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1496 }
1497
1498 if (itd->transact[i] & ITD_XACT_IOC) {
1499 ehci_record_interrupt(ehci, USBSTS_INT);
1500 }
1501 }
1502 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1503 }
1504 }
1505 return 0;
1506 }
1507
1508 /* This state is the entry point for asynchronous schedule
1509 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1510 */
1511 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1512 {
1513 EHCIqh qh;
1514 int i = 0;
1515 int again = 0;
1516 uint32_t entry = ehci->asynclistaddr;
1517
1518 /* set reclamation flag at start event (4.8.6) */
1519 if (async) {
1520 ehci_set_usbsts(ehci, USBSTS_REC);
1521 }
1522
1523 ehci_queues_rip_unused(ehci);
1524
1525 /* Find the head of the list (4.9.1.1) */
1526 for(i = 0; i < MAX_QH; i++) {
1527 get_dwords(NLPTR_GET(entry), (uint32_t *) &qh, sizeof(EHCIqh) >> 2);
1528 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1529
1530 if (qh.epchar & QH_EPCHAR_H) {
1531 if (async) {
1532 entry |= (NLPTR_TYPE_QH << 1);
1533 }
1534
1535 ehci_set_fetch_addr(ehci, async, entry);
1536 ehci_set_state(ehci, async, EST_FETCHENTRY);
1537 again = 1;
1538 goto out;
1539 }
1540
1541 entry = qh.next;
1542 if (entry == ehci->asynclistaddr) {
1543 break;
1544 }
1545 }
1546
1547 /* no head found for list. */
1548
1549 ehci_set_state(ehci, async, EST_ACTIVE);
1550
1551 out:
1552 return again;
1553 }
1554
1555
1556 /* This state is the entry point for periodic schedule processing as
1557 * well as being a continuation state for async processing.
1558 */
1559 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1560 {
1561 int again = 0;
1562 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1563
1564 if (entry < 0x1000) {
1565 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
1566 ehci_set_state(ehci, async, EST_ACTIVE);
1567 goto out;
1568 }
1569
1570 /* section 4.8, only QH in async schedule */
1571 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1572 fprintf(stderr, "non queue head request in async schedule\n");
1573 return -1;
1574 }
1575
1576 switch (NLPTR_TYPE_GET(entry)) {
1577 case NLPTR_TYPE_QH:
1578 ehci_set_state(ehci, async, EST_FETCHQH);
1579 again = 1;
1580 break;
1581
1582 case NLPTR_TYPE_ITD:
1583 ehci_set_state(ehci, async, EST_FETCHITD);
1584 again = 1;
1585 break;
1586
1587 default:
1588 // TODO: handle siTD and FSTN types
1589 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1590 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1591 return -1;
1592 }
1593
1594 out:
1595 return again;
1596 }
1597
1598 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1599 {
1600 uint32_t entry;
1601 EHCIQueue *q;
1602 int reload;
1603
1604 entry = ehci_get_fetch_addr(ehci, async);
1605 q = ehci_find_queue_by_qh(ehci, entry);
1606 if (NULL == q) {
1607 q = ehci_alloc_queue(ehci, async);
1608 }
1609 q->qhaddr = entry;
1610 q->seen++;
1611
1612 if (q->seen > 1) {
1613 /* we are going in circles -- stop processing */
1614 ehci_set_state(ehci, async, EST_ACTIVE);
1615 q = NULL;
1616 goto out;
1617 }
1618
1619 get_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1620 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1621
1622 if (q->async == EHCI_ASYNC_INFLIGHT) {
1623 /* I/O still in progress -- skip queue */
1624 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1625 goto out;
1626 }
1627 if (q->async == EHCI_ASYNC_FINISHED) {
1628 /* I/O finished -- continue processing queue */
1629 trace_usb_ehci_queue_action(q, "resume");
1630 ehci_set_state(ehci, async, EST_EXECUTING);
1631 goto out;
1632 }
1633
1634 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1635
1636 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1637 if (ehci->usbsts & USBSTS_REC) {
1638 ehci_clear_usbsts(ehci, USBSTS_REC);
1639 } else {
1640 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1641 " - done processing\n", q->qhaddr);
1642 ehci_set_state(ehci, async, EST_ACTIVE);
1643 q = NULL;
1644 goto out;
1645 }
1646 }
1647
1648 #if EHCI_DEBUG
1649 if (q->qhaddr != q->qh.next) {
1650 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1651 q->qhaddr,
1652 q->qh.epchar & QH_EPCHAR_H,
1653 q->qh.token & QTD_TOKEN_HALT,
1654 q->qh.token & QTD_TOKEN_ACTIVE,
1655 q->qh.next);
1656 }
1657 #endif
1658
1659 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1660 if (reload) {
1661 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1662 }
1663
1664 if (q->qh.token & QTD_TOKEN_HALT) {
1665 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1666
1667 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && (q->qh.current_qtd > 0x1000)) {
1668 q->qtdaddr = q->qh.current_qtd;
1669 ehci_set_state(ehci, async, EST_FETCHQTD);
1670
1671 } else {
1672 /* EHCI spec version 1.0 Section 4.10.2 */
1673 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1674 }
1675
1676 out:
1677 return q;
1678 }
1679
1680 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1681 {
1682 uint32_t entry;
1683 EHCIitd itd;
1684
1685 assert(!async);
1686 entry = ehci_get_fetch_addr(ehci, async);
1687
1688 get_dwords(NLPTR_GET(entry),(uint32_t *) &itd,
1689 sizeof(EHCIitd) >> 2);
1690 ehci_trace_itd(ehci, entry, &itd);
1691
1692 if (ehci_process_itd(ehci, &itd) != 0) {
1693 return -1;
1694 }
1695
1696 put_dwords(NLPTR_GET(entry), (uint32_t *) &itd,
1697 sizeof(EHCIitd) >> 2);
1698 ehci_set_fetch_addr(ehci, async, itd.next);
1699 ehci_set_state(ehci, async, EST_FETCHENTRY);
1700
1701 return 1;
1702 }
1703
1704 /* Section 4.10.2 - paragraph 3 */
1705 static int ehci_state_advqueue(EHCIQueue *q, int async)
1706 {
1707 #if 0
1708 /* TO-DO: 4.10.2 - paragraph 2
1709 * if I-bit is set to 1 and QH is not active
1710 * go to horizontal QH
1711 */
1712 if (I-bit set) {
1713 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1714 goto out;
1715 }
1716 #endif
1717
1718 /*
1719 * want data and alt-next qTD is valid
1720 */
1721 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1722 (q->qh.altnext_qtd > 0x1000) &&
1723 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1724 q->qtdaddr = q->qh.altnext_qtd;
1725 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1726
1727 /*
1728 * next qTD is valid
1729 */
1730 } else if ((q->qh.next_qtd > 0x1000) &&
1731 (NLPTR_TBIT(q->qh.next_qtd) == 0)) {
1732 q->qtdaddr = q->qh.next_qtd;
1733 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1734
1735 /*
1736 * no valid qTD, try next QH
1737 */
1738 } else {
1739 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1740 }
1741
1742 return 1;
1743 }
1744
1745 /* Section 4.10.2 - paragraph 4 */
1746 static int ehci_state_fetchqtd(EHCIQueue *q, int async)
1747 {
1748 int again = 0;
1749
1750 get_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qtd, sizeof(EHCIqtd) >> 2);
1751 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd);
1752
1753 if (q->qtd.token & QTD_TOKEN_ACTIVE) {
1754 ehci_set_state(q->ehci, async, EST_EXECUTE);
1755 again = 1;
1756 } else {
1757 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1758 again = 1;
1759 }
1760
1761 return again;
1762 }
1763
1764 static int ehci_state_horizqh(EHCIQueue *q, int async)
1765 {
1766 int again = 0;
1767
1768 if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) {
1769 ehci_set_fetch_addr(q->ehci, async, q->qh.next);
1770 ehci_set_state(q->ehci, async, EST_FETCHENTRY);
1771 again = 1;
1772 } else {
1773 ehci_set_state(q->ehci, async, EST_ACTIVE);
1774 }
1775
1776 return again;
1777 }
1778
1779 /*
1780 * Write the qh back to guest physical memory. This step isn't
1781 * in the EHCI spec but we need to do it since we don't share
1782 * physical memory with our guest VM.
1783 *
1784 * The first three dwords are read-only for the EHCI, so skip them
1785 * when writing back the qh.
1786 */
1787 static void ehci_flush_qh(EHCIQueue *q)
1788 {
1789 uint32_t *qh = (uint32_t *) &q->qh;
1790 uint32_t dwords = sizeof(EHCIqh) >> 2;
1791 uint32_t addr = NLPTR_GET(q->qhaddr);
1792
1793 put_dwords(addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1794 }
1795
1796 static int ehci_state_execute(EHCIQueue *q, int async)
1797 {
1798 int again = 0;
1799 int reload, nakcnt;
1800 int smask;
1801
1802 if (ehci_qh_do_overlay(q) != 0) {
1803 return -1;
1804 }
1805
1806 smask = get_field(q->qh.epcap, QH_EPCAP_SMASK);
1807
1808 if (!smask) {
1809 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1810 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1811 if (reload && !nakcnt) {
1812 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1813 again = 1;
1814 goto out;
1815 }
1816 }
1817
1818 // TODO verify enough time remains in the uframe as in 4.4.1.1
1819 // TODO write back ptr to async list when done or out of time
1820 // TODO Windows does not seem to ever set the MULT field
1821
1822 if (!async) {
1823 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1824 if (!transactCtr) {
1825 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1826 again = 1;
1827 goto out;
1828 }
1829 }
1830
1831 if (async) {
1832 ehci_set_usbsts(q->ehci, USBSTS_REC);
1833 }
1834
1835 q->usb_status = ehci_execute(q);
1836 if (q->usb_status == USB_RET_PROCERR) {
1837 again = -1;
1838 goto out;
1839 }
1840 if (q->usb_status == USB_RET_ASYNC) {
1841 ehci_flush_qh(q);
1842 trace_usb_ehci_queue_action(q, "suspend");
1843 q->async = EHCI_ASYNC_INFLIGHT;
1844 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1845 again = 1;
1846 goto out;
1847 }
1848
1849 ehci_set_state(q->ehci, async, EST_EXECUTING);
1850 again = 1;
1851
1852 out:
1853 return again;
1854 }
1855
1856 static int ehci_state_executing(EHCIQueue *q, int async)
1857 {
1858 int again = 0;
1859 int reload, nakcnt;
1860
1861 ehci_execute_complete(q);
1862 if (q->usb_status == USB_RET_ASYNC) {
1863 goto out;
1864 }
1865 if (q->usb_status == USB_RET_PROCERR) {
1866 again = -1;
1867 goto out;
1868 }
1869
1870 // 4.10.3
1871 if (!async) {
1872 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1873 transactCtr--;
1874 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
1875 // 4.10.3, bottom of page 82, should exit this state when transaction
1876 // counter decrements to 0
1877 }
1878
1879 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1880 if (reload) {
1881 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1882 if (q->usb_status == USB_RET_NAK) {
1883 if (nakcnt) {
1884 nakcnt--;
1885 }
1886 } else {
1887 nakcnt = reload;
1888 }
1889 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1890 }
1891
1892 /* 4.10.5 */
1893 if ((q->usb_status == USB_RET_NAK) || (q->qh.token & QTD_TOKEN_ACTIVE)) {
1894 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1895 } else {
1896 ehci_set_state(q->ehci, async, EST_WRITEBACK);
1897 }
1898
1899 again = 1;
1900
1901 out:
1902 ehci_flush_qh(q);
1903 return again;
1904 }
1905
1906
1907 static int ehci_state_writeback(EHCIQueue *q, int async)
1908 {
1909 int again = 0;
1910
1911 /* Write back the QTD from the QH area */
1912 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd);
1913 put_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qh.next_qtd,
1914 sizeof(EHCIqtd) >> 2);
1915
1916 /*
1917 * EHCI specs say go horizontal here.
1918 *
1919 * We can also advance the queue here for performance reasons. We
1920 * need to take care to only take that shortcut in case we've
1921 * processed the qtd just written back without errors, i.e. halt
1922 * bit is clear.
1923 */
1924 if (q->qh.token & QTD_TOKEN_HALT) {
1925 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1926 again = 1;
1927 } else {
1928 ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE);
1929 again = 1;
1930 }
1931 return again;
1932 }
1933
1934 /*
1935 * This is the state machine that is common to both async and periodic
1936 */
1937
1938 static void ehci_advance_state(EHCIState *ehci,
1939 int async)
1940 {
1941 EHCIQueue *q = NULL;
1942 int again;
1943 int iter = 0;
1944
1945 do {
1946 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
1947 iter++;
1948 /* if we are roaming a lot of QH without executing a qTD
1949 * something is wrong with the linked list. TO-DO: why is
1950 * this hack needed?
1951 */
1952 assert(iter < MAX_ITERATIONS);
1953 #if 0
1954 if (iter > MAX_ITERATIONS) {
1955 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1956 ehci_set_state(ehci, async, EST_ACTIVE);
1957 break;
1958 }
1959 #endif
1960 }
1961 switch(ehci_get_state(ehci, async)) {
1962 case EST_WAITLISTHEAD:
1963 again = ehci_state_waitlisthead(ehci, async);
1964 break;
1965
1966 case EST_FETCHENTRY:
1967 again = ehci_state_fetchentry(ehci, async);
1968 break;
1969
1970 case EST_FETCHQH:
1971 q = ehci_state_fetchqh(ehci, async);
1972 again = q ? 1 : 0;
1973 break;
1974
1975 case EST_FETCHITD:
1976 again = ehci_state_fetchitd(ehci, async);
1977 break;
1978
1979 case EST_ADVANCEQUEUE:
1980 again = ehci_state_advqueue(q, async);
1981 break;
1982
1983 case EST_FETCHQTD:
1984 again = ehci_state_fetchqtd(q, async);
1985 break;
1986
1987 case EST_HORIZONTALQH:
1988 again = ehci_state_horizqh(q, async);
1989 break;
1990
1991 case EST_EXECUTE:
1992 iter = 0;
1993 again = ehci_state_execute(q, async);
1994 break;
1995
1996 case EST_EXECUTING:
1997 assert(q != NULL);
1998 again = ehci_state_executing(q, async);
1999 break;
2000
2001 case EST_WRITEBACK:
2002 again = ehci_state_writeback(q, async);
2003 break;
2004
2005 default:
2006 fprintf(stderr, "Bad state!\n");
2007 again = -1;
2008 assert(0);
2009 break;
2010 }
2011
2012 if (again < 0) {
2013 fprintf(stderr, "processing error - resetting ehci HC\n");
2014 ehci_reset(ehci);
2015 again = 0;
2016 assert(0);
2017 }
2018 }
2019 while (again);
2020
2021 ehci_commit_interrupt(ehci);
2022 }
2023
2024 static void ehci_advance_async_state(EHCIState *ehci)
2025 {
2026 int async = 1;
2027
2028 switch(ehci_get_state(ehci, async)) {
2029 case EST_INACTIVE:
2030 if (!(ehci->usbcmd & USBCMD_ASE)) {
2031 break;
2032 }
2033 ehci_set_usbsts(ehci, USBSTS_ASS);
2034 ehci_set_state(ehci, async, EST_ACTIVE);
2035 // No break, fall through to ACTIVE
2036
2037 case EST_ACTIVE:
2038 if ( !(ehci->usbcmd & USBCMD_ASE)) {
2039 ehci_clear_usbsts(ehci, USBSTS_ASS);
2040 ehci_set_state(ehci, async, EST_INACTIVE);
2041 break;
2042 }
2043
2044 /* If the doorbell is set, the guest wants to make a change to the
2045 * schedule. The host controller needs to release cached data.
2046 * (section 4.8.2)
2047 */
2048 if (ehci->usbcmd & USBCMD_IAAD) {
2049 DPRINTF("ASYNC: doorbell request acknowledged\n");
2050 ehci->usbcmd &= ~USBCMD_IAAD;
2051 ehci_set_interrupt(ehci, USBSTS_IAA);
2052 break;
2053 }
2054
2055 /* make sure guest has acknowledged */
2056 /* TO-DO: is this really needed? */
2057 if (ehci->usbsts & USBSTS_IAA) {
2058 DPRINTF("IAA status bit still set.\n");
2059 break;
2060 }
2061
2062 /* check that address register has been set */
2063 if (ehci->asynclistaddr == 0) {
2064 break;
2065 }
2066
2067 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2068 ehci_advance_state(ehci, async);
2069 break;
2070
2071 default:
2072 /* this should only be due to a developer mistake */
2073 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2074 "Resetting to active\n", ehci->astate);
2075 assert(0);
2076 }
2077 }
2078
2079 static void ehci_advance_periodic_state(EHCIState *ehci)
2080 {
2081 uint32_t entry;
2082 uint32_t list;
2083 int async = 0;
2084
2085 // 4.6
2086
2087 switch(ehci_get_state(ehci, async)) {
2088 case EST_INACTIVE:
2089 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
2090 ehci_set_usbsts(ehci, USBSTS_PSS);
2091 ehci_set_state(ehci, async, EST_ACTIVE);
2092 // No break, fall through to ACTIVE
2093 } else
2094 break;
2095
2096 case EST_ACTIVE:
2097 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
2098 ehci_clear_usbsts(ehci, USBSTS_PSS);
2099 ehci_set_state(ehci, async, EST_INACTIVE);
2100 break;
2101 }
2102
2103 list = ehci->periodiclistbase & 0xfffff000;
2104 /* check that register has been set */
2105 if (list == 0) {
2106 break;
2107 }
2108 list |= ((ehci->frindex & 0x1ff8) >> 1);
2109
2110 cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0);
2111 entry = le32_to_cpu(entry);
2112
2113 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2114 ehci->frindex / 8, list, entry);
2115 ehci_set_fetch_addr(ehci, async,entry);
2116 ehci_set_state(ehci, async, EST_FETCHENTRY);
2117 ehci_advance_state(ehci, async);
2118 break;
2119
2120 default:
2121 /* this should only be due to a developer mistake */
2122 fprintf(stderr, "ehci: Bad periodic state %d. "
2123 "Resetting to active\n", ehci->pstate);
2124 assert(0);
2125 }
2126 }
2127
2128 static void ehci_frame_timer(void *opaque)
2129 {
2130 EHCIState *ehci = opaque;
2131 int64_t expire_time, t_now;
2132 uint64_t ns_elapsed;
2133 int frames;
2134 int i;
2135 int skipped_frames = 0;
2136
2137 t_now = qemu_get_clock_ns(vm_clock);
2138 expire_time = t_now + (get_ticks_per_sec() / ehci->freq);
2139
2140 ns_elapsed = t_now - ehci->last_run_ns;
2141 frames = ns_elapsed / FRAME_TIMER_NS;
2142
2143 for (i = 0; i < frames; i++) {
2144 if ( !(ehci->usbsts & USBSTS_HALT)) {
2145 if (ehci->isoch_pause <= 0) {
2146 ehci->frindex += 8;
2147 }
2148
2149 if (ehci->frindex > 0x00001fff) {
2150 ehci->frindex = 0;
2151 ehci_set_interrupt(ehci, USBSTS_FLR);
2152 }
2153
2154 ehci->sofv = (ehci->frindex - 1) >> 3;
2155 ehci->sofv &= 0x000003ff;
2156 }
2157
2158 if (frames - i > ehci->maxframes) {
2159 skipped_frames++;
2160 } else {
2161 ehci_advance_periodic_state(ehci);
2162 }
2163
2164 ehci->last_run_ns += FRAME_TIMER_NS;
2165 }
2166
2167 #if 0
2168 if (skipped_frames) {
2169 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2170 }
2171 #endif
2172
2173 /* Async is not inside loop since it executes everything it can once
2174 * called
2175 */
2176 ehci_advance_async_state(ehci);
2177
2178 qemu_mod_timer(ehci->frame_timer, expire_time);
2179 }
2180
2181
2182 static const MemoryRegionOps ehci_mem_ops = {
2183 .old_mmio = {
2184 .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
2185 .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
2186 },
2187 .endianness = DEVICE_LITTLE_ENDIAN,
2188 };
2189
2190 static int usb_ehci_initfn(PCIDevice *dev);
2191
2192 static USBPortOps ehci_port_ops = {
2193 .attach = ehci_attach,
2194 .detach = ehci_detach,
2195 .child_detach = ehci_child_detach,
2196 .wakeup = ehci_wakeup,
2197 .complete = ehci_async_complete_packet,
2198 };
2199
2200 static USBBusOps ehci_bus_ops = {
2201 .register_companion = ehci_register_companion,
2202 };
2203
2204 static const VMStateDescription vmstate_ehci = {
2205 .name = "ehci",
2206 .unmigratable = 1,
2207 };
2208
2209 static Property ehci_properties[] = {
2210 DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ),
2211 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128),
2212 DEFINE_PROP_END_OF_LIST(),
2213 };
2214
2215 static PCIDeviceInfo ehci_info[] = {
2216 {
2217 .qdev.name = "usb-ehci",
2218 .qdev.size = sizeof(EHCIState),
2219 .qdev.vmsd = &vmstate_ehci,
2220 .init = usb_ehci_initfn,
2221 .vendor_id = PCI_VENDOR_ID_INTEL,
2222 .device_id = PCI_DEVICE_ID_INTEL_82801D, /* ich4 */
2223 .revision = 0x10,
2224 .class_id = PCI_CLASS_SERIAL_USB,
2225 .qdev.props = ehci_properties,
2226 },{
2227 .qdev.name = "ich9-usb-ehci1",
2228 .qdev.size = sizeof(EHCIState),
2229 .qdev.vmsd = &vmstate_ehci,
2230 .init = usb_ehci_initfn,
2231 .vendor_id = PCI_VENDOR_ID_INTEL,
2232 .device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1,
2233 .revision = 0x03,
2234 .class_id = PCI_CLASS_SERIAL_USB,
2235 .qdev.props = ehci_properties,
2236 },{
2237 /* end of list */
2238 }
2239 };
2240
2241 static int usb_ehci_initfn(PCIDevice *dev)
2242 {
2243 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2244 uint8_t *pci_conf = s->dev.config;
2245 int i;
2246
2247 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2248
2249 /* capabilities pointer */
2250 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2251 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2252
2253 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3
2254 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2255 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2256
2257 // pci_conf[0x50] = 0x01; // power management caps
2258
2259 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
2260 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2261 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2262
2263 pci_conf[0x64] = 0x00;
2264 pci_conf[0x65] = 0x00;
2265 pci_conf[0x66] = 0x00;
2266 pci_conf[0x67] = 0x00;
2267 pci_conf[0x68] = 0x01;
2268 pci_conf[0x69] = 0x00;
2269 pci_conf[0x6a] = 0x00;
2270 pci_conf[0x6b] = 0x00; // USBLEGSUP
2271 pci_conf[0x6c] = 0x00;
2272 pci_conf[0x6d] = 0x00;
2273 pci_conf[0x6e] = 0x00;
2274 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2275
2276 // 2.2 host controller interface version
2277 s->mmio[0x00] = (uint8_t) OPREGBASE;
2278 s->mmio[0x01] = 0x00;
2279 s->mmio[0x02] = 0x00;
2280 s->mmio[0x03] = 0x01; // HC version
2281 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2282 s->mmio[0x05] = 0x00; // No companion ports at present
2283 s->mmio[0x06] = 0x00;
2284 s->mmio[0x07] = 0x00;
2285 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2286 s->mmio[0x09] = 0x68; // EECP
2287 s->mmio[0x0a] = 0x00;
2288 s->mmio[0x0b] = 0x00;
2289
2290 s->irq = s->dev.irq[3];
2291
2292 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2293 for(i = 0; i < NB_PORTS; i++) {
2294 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2295 USB_SPEED_MASK_HIGH);
2296 s->ports[i].dev = 0;
2297 }
2298
2299 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2300 QTAILQ_INIT(&s->queues);
2301
2302 qemu_register_reset(ehci_reset, s);
2303
2304 memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
2305 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
2306
2307 fprintf(stderr, "*** EHCI support is under development ***\n");
2308
2309 return 0;
2310 }
2311
2312 static void ehci_register(void)
2313 {
2314 pci_qdev_register_many(ehci_info);
2315 }
2316 device_init(ehci_register);
2317
2318 /*
2319 * vim: expandtab ts=4
2320 */
Qemu copy for testing