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[qemu.git] / hw / usb / hcd-ehci.c
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "hw/hw.h"
26 #include "qemu-timer.h"
27 #include "hw/usb.h"
28 #include "hw/pci.h"
29 #include "monitor.h"
30 #include "trace.h"
31 #include "dma.h"
32
33 #define EHCI_DEBUG 0
34
35 #if EHCI_DEBUG
36 #define DPRINTF printf
37 #else
38 #define DPRINTF(...)
39 #endif
40
41 /* internal processing - reset HC to try and recover */
42 #define USB_RET_PROCERR (-99)
43
44 #define MMIO_SIZE 0x1000
45
46 /* Capability Registers Base Address - section 2.2 */
47 #define CAPREGBASE 0x0000
48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
52 #define EECP HCCPARAMS + 1
53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
55
56 #define OPREGBASE 0x0020 // Operational Registers Base Address
57
58 #define USBCMD OPREGBASE + 0x0000
59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
60 #define USBCMD_HCRESET (1 << 1) // HC Reset
61 #define USBCMD_FLS (3 << 2) // Frame List Size
62 #define USBCMD_FLS_SH 2 // Frame List Size Shift
63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
71
72 #define USBSTS OPREGBASE + 0x0004
73 #define USBSTS_RO_MASK 0x0000003f
74 #define USBSTS_INT (1 << 0) // USB Interrupt
75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
76 #define USBSTS_PCD (1 << 2) // Port Change Detect
77 #define USBSTS_FLR (1 << 3) // Frame List Rollover
78 #define USBSTS_HSE (1 << 4) // Host System Error
79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
80 #define USBSTS_HALT (1 << 12) // HC Halted
81 #define USBSTS_REC (1 << 13) // Reclamation
82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
84
85 /*
86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
87 * so no need to redefine here.
88 */
89 #define USBINTR OPREGBASE + 0x0008
90 #define USBINTR_MASK 0x0000003f
91
92 #define FRINDEX OPREGBASE + 0x000c
93 #define CTRLDSSEGMENT OPREGBASE + 0x0010
94 #define PERIODICLISTBASE OPREGBASE + 0x0014
95 #define ASYNCLISTADDR OPREGBASE + 0x0018
96 #define ASYNCLISTADDR_MASK 0xffffffe0
97
98 #define CONFIGFLAG OPREGBASE + 0x0040
99
100 #define PORTSC (OPREGBASE + 0x0044)
101 #define PORTSC_BEGIN PORTSC
102 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
103 /*
104 * Bits that are reserved or are read-only are masked out of values
105 * written to us by software
106 */
107 #define PORTSC_RO_MASK 0x007001c0
108 #define PORTSC_RWC_MASK 0x0000002a
109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
112 #define PORTSC_PTC (15 << 16) // Port Test Control
113 #define PORTSC_PTC_SH 16 // Port Test Control shift
114 #define PORTSC_PIC (3 << 14) // Port Indicator Control
115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
116 #define PORTSC_POWNER (1 << 13) // Port Owner
117 #define PORTSC_PPOWER (1 << 12) // Port Power
118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
120 #define PORTSC_PRESET (1 << 8) // Port Reset
121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
122 #define PORTSC_FPRES (1 << 6) // Force Port Resume
123 #define PORTSC_OCC (1 << 5) // Over Current Change
124 #define PORTSC_OCA (1 << 4) // Over Current Active
125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
126 #define PORTSC_PED (1 << 2) // Port Enable/Disable
127 #define PORTSC_CSC (1 << 1) // Connect Status Change
128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
129
130 #define FRAME_TIMER_FREQ 1000
131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
132
133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
134 #define NB_PORTS 6 // Number of downstream ports
135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
136 #define MAX_QH 100 // Max allowable queue heads in a chain
137
138 /* Internal periodic / asynchronous schedule state machine states
139 */
140 typedef enum {
141 EST_INACTIVE = 1000,
142 EST_ACTIVE,
143 EST_EXECUTING,
144 EST_SLEEPING,
145 /* The following states are internal to the state machine function
146 */
147 EST_WAITLISTHEAD,
148 EST_FETCHENTRY,
149 EST_FETCHQH,
150 EST_FETCHITD,
151 EST_FETCHSITD,
152 EST_ADVANCEQUEUE,
153 EST_FETCHQTD,
154 EST_EXECUTE,
155 EST_WRITEBACK,
156 EST_HORIZONTALQH
157 } EHCI_STATES;
158
159 /* macros for accessing fields within next link pointer entry */
160 #define NLPTR_GET(x) ((x) & 0xffffffe0)
161 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
162 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
163
164 /* link pointer types */
165 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
166 #define NLPTR_TYPE_QH 1 // queue head
167 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
168 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
169
170
171 /* EHCI spec version 1.0 Section 3.3
172 */
173 typedef struct EHCIitd {
174 uint32_t next;
175
176 uint32_t transact[8];
177 #define ITD_XACT_ACTIVE (1 << 31)
178 #define ITD_XACT_DBERROR (1 << 30)
179 #define ITD_XACT_BABBLE (1 << 29)
180 #define ITD_XACT_XACTERR (1 << 28)
181 #define ITD_XACT_LENGTH_MASK 0x0fff0000
182 #define ITD_XACT_LENGTH_SH 16
183 #define ITD_XACT_IOC (1 << 15)
184 #define ITD_XACT_PGSEL_MASK 0x00007000
185 #define ITD_XACT_PGSEL_SH 12
186 #define ITD_XACT_OFFSET_MASK 0x00000fff
187
188 uint32_t bufptr[7];
189 #define ITD_BUFPTR_MASK 0xfffff000
190 #define ITD_BUFPTR_SH 12
191 #define ITD_BUFPTR_EP_MASK 0x00000f00
192 #define ITD_BUFPTR_EP_SH 8
193 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
194 #define ITD_BUFPTR_DEVADDR_SH 0
195 #define ITD_BUFPTR_DIRECTION (1 << 11)
196 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
197 #define ITD_BUFPTR_MAXPKT_SH 0
198 #define ITD_BUFPTR_MULT_MASK 0x00000003
199 #define ITD_BUFPTR_MULT_SH 0
200 } EHCIitd;
201
202 /* EHCI spec version 1.0 Section 3.4
203 */
204 typedef struct EHCIsitd {
205 uint32_t next; // Standard next link pointer
206 uint32_t epchar;
207 #define SITD_EPCHAR_IO (1 << 31)
208 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
209 #define SITD_EPCHAR_PORTNUM_SH 24
210 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
211 #define SITD_EPCHAR_HUBADDR_SH 16
212 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
213 #define SITD_EPCHAR_EPNUM_SH 8
214 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
215
216 uint32_t uframe;
217 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
218 #define SITD_UFRAME_CMASK_SH 8
219 #define SITD_UFRAME_SMASK_MASK 0x000000ff
220
221 uint32_t results;
222 #define SITD_RESULTS_IOC (1 << 31)
223 #define SITD_RESULTS_PGSEL (1 << 30)
224 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
225 #define SITD_RESULTS_TYBYTES_SH 16
226 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
227 #define SITD_RESULTS_CPROGMASK_SH 8
228 #define SITD_RESULTS_ACTIVE (1 << 7)
229 #define SITD_RESULTS_ERR (1 << 6)
230 #define SITD_RESULTS_DBERR (1 << 5)
231 #define SITD_RESULTS_BABBLE (1 << 4)
232 #define SITD_RESULTS_XACTERR (1 << 3)
233 #define SITD_RESULTS_MISSEDUF (1 << 2)
234 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
235
236 uint32_t bufptr[2];
237 #define SITD_BUFPTR_MASK 0xfffff000
238 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
239 #define SITD_BUFPTR_TPOS_MASK 0x00000018
240 #define SITD_BUFPTR_TPOS_SH 3
241 #define SITD_BUFPTR_TCNT_MASK 0x00000007
242
243 uint32_t backptr; // Standard next link pointer
244 } EHCIsitd;
245
246 /* EHCI spec version 1.0 Section 3.5
247 */
248 typedef struct EHCIqtd {
249 uint32_t next; // Standard next link pointer
250 uint32_t altnext; // Standard next link pointer
251 uint32_t token;
252 #define QTD_TOKEN_DTOGGLE (1 << 31)
253 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
254 #define QTD_TOKEN_TBYTES_SH 16
255 #define QTD_TOKEN_IOC (1 << 15)
256 #define QTD_TOKEN_CPAGE_MASK 0x00007000
257 #define QTD_TOKEN_CPAGE_SH 12
258 #define QTD_TOKEN_CERR_MASK 0x00000c00
259 #define QTD_TOKEN_CERR_SH 10
260 #define QTD_TOKEN_PID_MASK 0x00000300
261 #define QTD_TOKEN_PID_SH 8
262 #define QTD_TOKEN_ACTIVE (1 << 7)
263 #define QTD_TOKEN_HALT (1 << 6)
264 #define QTD_TOKEN_DBERR (1 << 5)
265 #define QTD_TOKEN_BABBLE (1 << 4)
266 #define QTD_TOKEN_XACTERR (1 << 3)
267 #define QTD_TOKEN_MISSEDUF (1 << 2)
268 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
269 #define QTD_TOKEN_PING (1 << 0)
270
271 uint32_t bufptr[5]; // Standard buffer pointer
272 #define QTD_BUFPTR_MASK 0xfffff000
273 #define QTD_BUFPTR_SH 12
274 } EHCIqtd;
275
276 /* EHCI spec version 1.0 Section 3.6
277 */
278 typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
280
281 /* endpoint characteristics */
282 uint32_t epchar;
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
296
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
302
303 /* endpoint capabilities */
304 uint32_t epcap;
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
315
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
321
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
328 } EHCIqh;
329
330 /* EHCI spec version 1.0 Section 3.7
331 */
332 typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335 } EHCIfstn;
336
337 typedef struct EHCIPacket EHCIPacket;
338 typedef struct EHCIQueue EHCIQueue;
339 typedef struct EHCIState EHCIState;
340
341 enum async_state {
342 EHCI_ASYNC_NONE = 0,
343 EHCI_ASYNC_INFLIGHT,
344 EHCI_ASYNC_FINISHED,
345 };
346
347 struct EHCIPacket {
348 EHCIQueue *queue;
349 QTAILQ_ENTRY(EHCIPacket) next;
350
351 EHCIqtd qtd; /* copy of current QTD (being worked on) */
352 uint32_t qtdaddr; /* address QTD read from */
353
354 USBPacket packet;
355 QEMUSGList sgl;
356 int pid;
357 uint32_t tbytes;
358 enum async_state async;
359 int usb_status;
360 };
361
362 struct EHCIQueue {
363 EHCIState *ehci;
364 QTAILQ_ENTRY(EHCIQueue) next;
365 uint32_t seen;
366 uint64_t ts;
367 int async;
368 int revalidate;
369
370 /* cached data from guest - needs to be flushed
371 * when guest removes an entry (doorbell, handshake sequence)
372 */
373 EHCIqh qh; /* copy of current QH (being worked on) */
374 uint32_t qhaddr; /* address QH read from */
375 uint32_t qtdaddr; /* address QTD read from */
376 USBDevice *dev;
377 QTAILQ_HEAD(, EHCIPacket) packets;
378 };
379
380 typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
381
382 struct EHCIState {
383 PCIDevice dev;
384 USBBus bus;
385 qemu_irq irq;
386 MemoryRegion mem;
387 int companion_count;
388
389 /* properties */
390 uint32_t maxframes;
391
392 /*
393 * EHCI spec version 1.0 Section 2.3
394 * Host Controller Operational Registers
395 */
396 union {
397 uint8_t mmio[MMIO_SIZE];
398 struct {
399 uint8_t cap[OPREGBASE];
400 uint32_t usbcmd;
401 uint32_t usbsts;
402 uint32_t usbintr;
403 uint32_t frindex;
404 uint32_t ctrldssegment;
405 uint32_t periodiclistbase;
406 uint32_t asynclistaddr;
407 uint32_t notused[9];
408 uint32_t configflag;
409 uint32_t portsc[NB_PORTS];
410 };
411 };
412
413 /*
414 * Internal states, shadow registers, etc
415 */
416 QEMUTimer *frame_timer;
417 QEMUBH *async_bh;
418 uint32_t astate; /* Current state in asynchronous schedule */
419 uint32_t pstate; /* Current state in periodic schedule */
420 USBPort ports[NB_PORTS];
421 USBPort *companion_ports[NB_PORTS];
422 uint32_t usbsts_pending;
423 uint32_t usbsts_frindex;
424 EHCIQueueHead aqueues;
425 EHCIQueueHead pqueues;
426
427 /* which address to look at next */
428 uint32_t a_fetch_addr;
429 uint32_t p_fetch_addr;
430
431 USBPacket ipacket;
432 QEMUSGList isgl;
433
434 uint64_t last_run_ns;
435 uint32_t async_stepdown;
436 };
437
438 #define SET_LAST_RUN_CLOCK(s) \
439 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
440
441 /* nifty macros from Arnon's EHCI version */
442 #define get_field(data, field) \
443 (((data) & field##_MASK) >> field##_SH)
444
445 #define set_field(data, newval, field) do { \
446 uint32_t val = *data; \
447 val &= ~ field##_MASK; \
448 val |= ((newval) << field##_SH) & field##_MASK; \
449 *data = val; \
450 } while(0)
451
452 static const char *ehci_state_names[] = {
453 [EST_INACTIVE] = "INACTIVE",
454 [EST_ACTIVE] = "ACTIVE",
455 [EST_EXECUTING] = "EXECUTING",
456 [EST_SLEEPING] = "SLEEPING",
457 [EST_WAITLISTHEAD] = "WAITLISTHEAD",
458 [EST_FETCHENTRY] = "FETCH ENTRY",
459 [EST_FETCHQH] = "FETCH QH",
460 [EST_FETCHITD] = "FETCH ITD",
461 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
462 [EST_FETCHQTD] = "FETCH QTD",
463 [EST_EXECUTE] = "EXECUTE",
464 [EST_WRITEBACK] = "WRITEBACK",
465 [EST_HORIZONTALQH] = "HORIZONTALQH",
466 };
467
468 static const char *ehci_mmio_names[] = {
469 [CAPLENGTH] = "CAPLENGTH",
470 [HCIVERSION] = "HCIVERSION",
471 [HCSPARAMS] = "HCSPARAMS",
472 [HCCPARAMS] = "HCCPARAMS",
473 [USBCMD] = "USBCMD",
474 [USBSTS] = "USBSTS",
475 [USBINTR] = "USBINTR",
476 [FRINDEX] = "FRINDEX",
477 [PERIODICLISTBASE] = "P-LIST BASE",
478 [ASYNCLISTADDR] = "A-LIST ADDR",
479 [PORTSC_BEGIN] = "PORTSC #0",
480 [PORTSC_BEGIN + 4] = "PORTSC #1",
481 [PORTSC_BEGIN + 8] = "PORTSC #2",
482 [PORTSC_BEGIN + 12] = "PORTSC #3",
483 [PORTSC_BEGIN + 16] = "PORTSC #4",
484 [PORTSC_BEGIN + 20] = "PORTSC #5",
485 [CONFIGFLAG] = "CONFIGFLAG",
486 };
487
488 static const char *nr2str(const char **n, size_t len, uint32_t nr)
489 {
490 if (nr < len && n[nr] != NULL) {
491 return n[nr];
492 } else {
493 return "unknown";
494 }
495 }
496
497 static const char *state2str(uint32_t state)
498 {
499 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
500 }
501
502 static const char *addr2str(target_phys_addr_t addr)
503 {
504 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
505 }
506
507 static void ehci_trace_usbsts(uint32_t mask, int state)
508 {
509 /* interrupts */
510 if (mask & USBSTS_INT) {
511 trace_usb_ehci_usbsts("INT", state);
512 }
513 if (mask & USBSTS_ERRINT) {
514 trace_usb_ehci_usbsts("ERRINT", state);
515 }
516 if (mask & USBSTS_PCD) {
517 trace_usb_ehci_usbsts("PCD", state);
518 }
519 if (mask & USBSTS_FLR) {
520 trace_usb_ehci_usbsts("FLR", state);
521 }
522 if (mask & USBSTS_HSE) {
523 trace_usb_ehci_usbsts("HSE", state);
524 }
525 if (mask & USBSTS_IAA) {
526 trace_usb_ehci_usbsts("IAA", state);
527 }
528
529 /* status */
530 if (mask & USBSTS_HALT) {
531 trace_usb_ehci_usbsts("HALT", state);
532 }
533 if (mask & USBSTS_REC) {
534 trace_usb_ehci_usbsts("REC", state);
535 }
536 if (mask & USBSTS_PSS) {
537 trace_usb_ehci_usbsts("PSS", state);
538 }
539 if (mask & USBSTS_ASS) {
540 trace_usb_ehci_usbsts("ASS", state);
541 }
542 }
543
544 static inline void ehci_set_usbsts(EHCIState *s, int mask)
545 {
546 if ((s->usbsts & mask) == mask) {
547 return;
548 }
549 ehci_trace_usbsts(mask, 1);
550 s->usbsts |= mask;
551 }
552
553 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
554 {
555 if ((s->usbsts & mask) == 0) {
556 return;
557 }
558 ehci_trace_usbsts(mask, 0);
559 s->usbsts &= ~mask;
560 }
561
562 /* update irq line */
563 static inline void ehci_update_irq(EHCIState *s)
564 {
565 int level = 0;
566
567 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
568 level = 1;
569 }
570
571 trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr);
572 qemu_set_irq(s->irq, level);
573 }
574
575 /* flag interrupt condition */
576 static inline void ehci_raise_irq(EHCIState *s, int intr)
577 {
578 if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) {
579 s->usbsts |= intr;
580 ehci_update_irq(s);
581 } else {
582 s->usbsts_pending |= intr;
583 }
584 }
585
586 /*
587 * Commit pending interrupts (added via ehci_raise_irq),
588 * at the rate allowed by "Interrupt Threshold Control".
589 */
590 static inline void ehci_commit_irq(EHCIState *s)
591 {
592 uint32_t itc;
593
594 if (!s->usbsts_pending) {
595 return;
596 }
597 if (s->usbsts_frindex > s->frindex) {
598 return;
599 }
600
601 itc = (s->usbcmd >> 16) & 0xff;
602 s->usbsts |= s->usbsts_pending;
603 s->usbsts_pending = 0;
604 s->usbsts_frindex = s->frindex + itc;
605 ehci_update_irq(s);
606 }
607
608 static void ehci_update_halt(EHCIState *s)
609 {
610 if (s->usbcmd & USBCMD_RUNSTOP) {
611 ehci_clear_usbsts(s, USBSTS_HALT);
612 } else {
613 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) {
614 ehci_set_usbsts(s, USBSTS_HALT);
615 }
616 }
617 }
618
619 static void ehci_set_state(EHCIState *s, int async, int state)
620 {
621 if (async) {
622 trace_usb_ehci_state("async", state2str(state));
623 s->astate = state;
624 if (s->astate == EST_INACTIVE) {
625 ehci_clear_usbsts(s, USBSTS_ASS);
626 ehci_update_halt(s);
627 } else {
628 ehci_set_usbsts(s, USBSTS_ASS);
629 }
630 } else {
631 trace_usb_ehci_state("periodic", state2str(state));
632 s->pstate = state;
633 if (s->pstate == EST_INACTIVE) {
634 ehci_clear_usbsts(s, USBSTS_PSS);
635 ehci_update_halt(s);
636 } else {
637 ehci_set_usbsts(s, USBSTS_PSS);
638 }
639 }
640 }
641
642 static int ehci_get_state(EHCIState *s, int async)
643 {
644 return async ? s->astate : s->pstate;
645 }
646
647 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
648 {
649 if (async) {
650 s->a_fetch_addr = addr;
651 } else {
652 s->p_fetch_addr = addr;
653 }
654 }
655
656 static int ehci_get_fetch_addr(EHCIState *s, int async)
657 {
658 return async ? s->a_fetch_addr : s->p_fetch_addr;
659 }
660
661 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
662 {
663 /* need three here due to argument count limits */
664 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
665 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
666 trace_usb_ehci_qh_fields(addr,
667 get_field(qh->epchar, QH_EPCHAR_RL),
668 get_field(qh->epchar, QH_EPCHAR_MPLEN),
669 get_field(qh->epchar, QH_EPCHAR_EPS),
670 get_field(qh->epchar, QH_EPCHAR_EP),
671 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
672 trace_usb_ehci_qh_bits(addr,
673 (bool)(qh->epchar & QH_EPCHAR_C),
674 (bool)(qh->epchar & QH_EPCHAR_H),
675 (bool)(qh->epchar & QH_EPCHAR_DTC),
676 (bool)(qh->epchar & QH_EPCHAR_I));
677 }
678
679 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
680 {
681 /* need three here due to argument count limits */
682 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
683 trace_usb_ehci_qtd_fields(addr,
684 get_field(qtd->token, QTD_TOKEN_TBYTES),
685 get_field(qtd->token, QTD_TOKEN_CPAGE),
686 get_field(qtd->token, QTD_TOKEN_CERR),
687 get_field(qtd->token, QTD_TOKEN_PID));
688 trace_usb_ehci_qtd_bits(addr,
689 (bool)(qtd->token & QTD_TOKEN_IOC),
690 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
691 (bool)(qtd->token & QTD_TOKEN_HALT),
692 (bool)(qtd->token & QTD_TOKEN_BABBLE),
693 (bool)(qtd->token & QTD_TOKEN_XACTERR));
694 }
695
696 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
697 {
698 trace_usb_ehci_itd(addr, itd->next,
699 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
700 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
701 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
702 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
703 }
704
705 static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
706 EHCIsitd *sitd)
707 {
708 trace_usb_ehci_sitd(addr, sitd->next,
709 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
710 }
711
712 static inline bool ehci_enabled(EHCIState *s)
713 {
714 return s->usbcmd & USBCMD_RUNSTOP;
715 }
716
717 static inline bool ehci_async_enabled(EHCIState *s)
718 {
719 return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE);
720 }
721
722 static inline bool ehci_periodic_enabled(EHCIState *s)
723 {
724 return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE);
725 }
726
727 /* packet management */
728
729 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
730 {
731 EHCIPacket *p;
732
733 p = g_new0(EHCIPacket, 1);
734 p->queue = q;
735 usb_packet_init(&p->packet);
736 QTAILQ_INSERT_TAIL(&q->packets, p, next);
737 trace_usb_ehci_packet_action(p->queue, p, "alloc");
738 return p;
739 }
740
741 static void ehci_free_packet(EHCIPacket *p)
742 {
743 trace_usb_ehci_packet_action(p->queue, p, "free");
744 if (p->async == EHCI_ASYNC_INFLIGHT) {
745 usb_cancel_packet(&p->packet);
746 }
747 QTAILQ_REMOVE(&p->queue->packets, p, next);
748 usb_packet_cleanup(&p->packet);
749 g_free(p);
750 }
751
752 /* queue management */
753
754 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async)
755 {
756 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
757 EHCIQueue *q;
758
759 q = g_malloc0(sizeof(*q));
760 q->ehci = ehci;
761 q->qhaddr = addr;
762 q->async = async;
763 QTAILQ_INIT(&q->packets);
764 QTAILQ_INSERT_HEAD(head, q, next);
765 trace_usb_ehci_queue_action(q, "alloc");
766 return q;
767 }
768
769 static void ehci_free_queue(EHCIQueue *q)
770 {
771 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues;
772 EHCIPacket *p;
773
774 trace_usb_ehci_queue_action(q, "free");
775 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) {
776 ehci_free_packet(p);
777 }
778 QTAILQ_REMOVE(head, q, next);
779 g_free(q);
780 }
781
782 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
783 int async)
784 {
785 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
786 EHCIQueue *q;
787
788 QTAILQ_FOREACH(q, head, next) {
789 if (addr == q->qhaddr) {
790 return q;
791 }
792 }
793 return NULL;
794 }
795
796 static void ehci_queues_tag_unused_async(EHCIState *ehci)
797 {
798 EHCIQueue *q;
799
800 QTAILQ_FOREACH(q, &ehci->aqueues, next) {
801 if (!q->seen) {
802 q->revalidate = 1;
803 }
804 }
805 }
806
807 static void ehci_queues_rip_unused(EHCIState *ehci, int async)
808 {
809 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
810 uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4;
811 EHCIQueue *q, *tmp;
812
813 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
814 if (q->seen) {
815 q->seen = 0;
816 q->ts = ehci->last_run_ns;
817 continue;
818 }
819 if (ehci->last_run_ns < q->ts + maxage) {
820 continue;
821 }
822 ehci_free_queue(q);
823 }
824 }
825
826 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async)
827 {
828 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
829 EHCIQueue *q, *tmp;
830
831 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
832 if (q->dev != dev) {
833 continue;
834 }
835 ehci_free_queue(q);
836 }
837 }
838
839 static void ehci_queues_rip_all(EHCIState *ehci, int async)
840 {
841 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
842 EHCIQueue *q, *tmp;
843
844 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
845 ehci_free_queue(q);
846 }
847 }
848
849 /* Attach or detach a device on root hub */
850
851 static void ehci_attach(USBPort *port)
852 {
853 EHCIState *s = port->opaque;
854 uint32_t *portsc = &s->portsc[port->index];
855 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
856
857 trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc);
858
859 if (*portsc & PORTSC_POWNER) {
860 USBPort *companion = s->companion_ports[port->index];
861 companion->dev = port->dev;
862 companion->ops->attach(companion);
863 return;
864 }
865
866 *portsc |= PORTSC_CONNECT;
867 *portsc |= PORTSC_CSC;
868
869 ehci_raise_irq(s, USBSTS_PCD);
870 ehci_commit_irq(s);
871 }
872
873 static void ehci_detach(USBPort *port)
874 {
875 EHCIState *s = port->opaque;
876 uint32_t *portsc = &s->portsc[port->index];
877 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
878
879 trace_usb_ehci_port_detach(port->index, owner);
880
881 if (*portsc & PORTSC_POWNER) {
882 USBPort *companion = s->companion_ports[port->index];
883 companion->ops->detach(companion);
884 companion->dev = NULL;
885 /*
886 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
887 * the port ownership is returned immediately to the EHCI controller."
888 */
889 *portsc &= ~PORTSC_POWNER;
890 return;
891 }
892
893 ehci_queues_rip_device(s, port->dev, 0);
894 ehci_queues_rip_device(s, port->dev, 1);
895
896 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
897 *portsc |= PORTSC_CSC;
898
899 ehci_raise_irq(s, USBSTS_PCD);
900 ehci_commit_irq(s);
901 }
902
903 static void ehci_child_detach(USBPort *port, USBDevice *child)
904 {
905 EHCIState *s = port->opaque;
906 uint32_t portsc = s->portsc[port->index];
907
908 if (portsc & PORTSC_POWNER) {
909 USBPort *companion = s->companion_ports[port->index];
910 companion->ops->child_detach(companion, child);
911 return;
912 }
913
914 ehci_queues_rip_device(s, child, 0);
915 ehci_queues_rip_device(s, child, 1);
916 }
917
918 static void ehci_wakeup(USBPort *port)
919 {
920 EHCIState *s = port->opaque;
921 uint32_t portsc = s->portsc[port->index];
922
923 if (portsc & PORTSC_POWNER) {
924 USBPort *companion = s->companion_ports[port->index];
925 if (companion->ops->wakeup) {
926 companion->ops->wakeup(companion);
927 }
928 return;
929 }
930
931 qemu_bh_schedule(s->async_bh);
932 }
933
934 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
935 uint32_t portcount, uint32_t firstport)
936 {
937 EHCIState *s = container_of(bus, EHCIState, bus);
938 uint32_t i;
939
940 if (firstport + portcount > NB_PORTS) {
941 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
942 "firstport on masterbus");
943 error_printf_unless_qmp(
944 "firstport value of %u makes companion take ports %u - %u, which "
945 "is outside of the valid range of 0 - %u\n", firstport, firstport,
946 firstport + portcount - 1, NB_PORTS - 1);
947 return -1;
948 }
949
950 for (i = 0; i < portcount; i++) {
951 if (s->companion_ports[firstport + i]) {
952 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
953 "an USB masterbus");
954 error_printf_unless_qmp(
955 "port %u on masterbus %s already has a companion assigned\n",
956 firstport + i, bus->qbus.name);
957 return -1;
958 }
959 }
960
961 for (i = 0; i < portcount; i++) {
962 s->companion_ports[firstport + i] = ports[i];
963 s->ports[firstport + i].speedmask |=
964 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
965 /* Ensure devs attached before the initial reset go to the companion */
966 s->portsc[firstport + i] = PORTSC_POWNER;
967 }
968
969 s->companion_count++;
970 s->mmio[0x05] = (s->companion_count << 4) | portcount;
971
972 return 0;
973 }
974
975 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
976 {
977 USBDevice *dev;
978 USBPort *port;
979 int i;
980
981 for (i = 0; i < NB_PORTS; i++) {
982 port = &ehci->ports[i];
983 if (!(ehci->portsc[i] & PORTSC_PED)) {
984 DPRINTF("Port %d not enabled\n", i);
985 continue;
986 }
987 dev = usb_find_device(port, addr);
988 if (dev != NULL) {
989 return dev;
990 }
991 }
992 return NULL;
993 }
994
995 /* 4.1 host controller initialization */
996 static void ehci_reset(void *opaque)
997 {
998 EHCIState *s = opaque;
999 int i;
1000 USBDevice *devs[NB_PORTS];
1001
1002 trace_usb_ehci_reset();
1003
1004 /*
1005 * Do the detach before touching portsc, so that it correctly gets send to
1006 * us or to our companion based on PORTSC_POWNER before the reset.
1007 */
1008 for(i = 0; i < NB_PORTS; i++) {
1009 devs[i] = s->ports[i].dev;
1010 if (devs[i] && devs[i]->attached) {
1011 usb_detach(&s->ports[i]);
1012 }
1013 }
1014
1015 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
1016
1017 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
1018 s->usbsts = USBSTS_HALT;
1019 s->usbsts_pending = 0;
1020 s->usbsts_frindex = 0;
1021
1022 s->astate = EST_INACTIVE;
1023 s->pstate = EST_INACTIVE;
1024
1025 for(i = 0; i < NB_PORTS; i++) {
1026 if (s->companion_ports[i]) {
1027 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
1028 } else {
1029 s->portsc[i] = PORTSC_PPOWER;
1030 }
1031 if (devs[i] && devs[i]->attached) {
1032 usb_attach(&s->ports[i]);
1033 usb_device_reset(devs[i]);
1034 }
1035 }
1036 ehci_queues_rip_all(s, 0);
1037 ehci_queues_rip_all(s, 1);
1038 qemu_del_timer(s->frame_timer);
1039 qemu_bh_cancel(s->async_bh);
1040 }
1041
1042 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
1043 {
1044 EHCIState *s = ptr;
1045 uint32_t val;
1046
1047 val = s->mmio[addr];
1048
1049 return val;
1050 }
1051
1052 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
1053 {
1054 EHCIState *s = ptr;
1055 uint32_t val;
1056
1057 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
1058
1059 return val;
1060 }
1061
1062 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
1063 {
1064 EHCIState *s = ptr;
1065 uint32_t val;
1066
1067 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
1068 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
1069
1070 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
1071 return val;
1072 }
1073
1074 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
1075 {
1076 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
1077 exit(1);
1078 }
1079
1080 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
1081 {
1082 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
1083 exit(1);
1084 }
1085
1086 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
1087 {
1088 USBDevice *dev = s->ports[port].dev;
1089 uint32_t *portsc = &s->portsc[port];
1090 uint32_t orig;
1091
1092 if (s->companion_ports[port] == NULL)
1093 return;
1094
1095 owner = owner & PORTSC_POWNER;
1096 orig = *portsc & PORTSC_POWNER;
1097
1098 if (!(owner ^ orig)) {
1099 return;
1100 }
1101
1102 if (dev && dev->attached) {
1103 usb_detach(&s->ports[port]);
1104 }
1105
1106 *portsc &= ~PORTSC_POWNER;
1107 *portsc |= owner;
1108
1109 if (dev && dev->attached) {
1110 usb_attach(&s->ports[port]);
1111 }
1112 }
1113
1114 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
1115 {
1116 uint32_t *portsc = &s->portsc[port];
1117 USBDevice *dev = s->ports[port].dev;
1118
1119 /* Clear rwc bits */
1120 *portsc &= ~(val & PORTSC_RWC_MASK);
1121 /* The guest may clear, but not set the PED bit */
1122 *portsc &= val | ~PORTSC_PED;
1123 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1124 handle_port_owner_write(s, port, val);
1125 /* And finally apply RO_MASK */
1126 val &= PORTSC_RO_MASK;
1127
1128 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
1129 trace_usb_ehci_port_reset(port, 1);
1130 }
1131
1132 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
1133 trace_usb_ehci_port_reset(port, 0);
1134 if (dev && dev->attached) {
1135 usb_port_reset(&s->ports[port]);
1136 *portsc &= ~PORTSC_CSC;
1137 }
1138
1139 /*
1140 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1141 * to SW that this port has a high speed device attached
1142 */
1143 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
1144 val |= PORTSC_PED;
1145 }
1146 }
1147
1148 *portsc &= ~PORTSC_RO_MASK;
1149 *portsc |= val;
1150 }
1151
1152 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
1153 {
1154 EHCIState *s = ptr;
1155 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
1156 uint32_t old = *mmio;
1157 int i;
1158
1159 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
1160
1161 /* Only aligned reads are allowed on OHCI */
1162 if (addr & 3) {
1163 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
1164 TARGET_FMT_plx "\n", addr);
1165 return;
1166 }
1167
1168 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
1169 handle_port_status_write(s, (addr-PORTSC)/4, val);
1170 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1171 return;
1172 }
1173
1174 if (addr < OPREGBASE) {
1175 fprintf(stderr, "usb-ehci: write attempt to read-only register"
1176 TARGET_FMT_plx "\n", addr);
1177 return;
1178 }
1179
1180
1181 /* Do any register specific pre-write processing here. */
1182 switch(addr) {
1183 case USBCMD:
1184 if (val & USBCMD_HCRESET) {
1185 ehci_reset(s);
1186 val = s->usbcmd;
1187 break;
1188 }
1189
1190 /* not supporting dynamic frame list size at the moment */
1191 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1192 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1193 val & USBCMD_FLS);
1194 val &= ~USBCMD_FLS;
1195 }
1196
1197 if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
1198 ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {
1199 if (s->pstate == EST_INACTIVE) {
1200 SET_LAST_RUN_CLOCK(s);
1201 }
1202 s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */
1203 ehci_update_halt(s);
1204 s->async_stepdown = 0;
1205 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
1206 }
1207 break;
1208
1209 case USBSTS:
1210 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
1211 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
1212 val = s->usbsts;
1213 ehci_update_irq(s);
1214 break;
1215
1216 case USBINTR:
1217 val &= USBINTR_MASK;
1218 break;
1219
1220 case FRINDEX:
1221 val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */
1222 break;
1223
1224 case CONFIGFLAG:
1225 val &= 0x1;
1226 if (val) {
1227 for(i = 0; i < NB_PORTS; i++)
1228 handle_port_owner_write(s, i, 0);
1229 }
1230 break;
1231
1232 case PERIODICLISTBASE:
1233 if (ehci_periodic_enabled(s)) {
1234 fprintf(stderr,
1235 "ehci: PERIODIC list base register set while periodic schedule\n"
1236 " is enabled and HC is enabled\n");
1237 }
1238 break;
1239
1240 case ASYNCLISTADDR:
1241 if (ehci_async_enabled(s)) {
1242 fprintf(stderr,
1243 "ehci: ASYNC list address register set while async schedule\n"
1244 " is enabled and HC is enabled\n");
1245 }
1246 break;
1247 }
1248
1249 *mmio = val;
1250 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1251 }
1252
1253
1254 // TODO : Put in common header file, duplication from usb-ohci.c
1255
1256 /* Get an array of dwords from main memory */
1257 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
1258 uint32_t *buf, int num)
1259 {
1260 int i;
1261
1262 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1263 pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf));
1264 *buf = le32_to_cpu(*buf);
1265 }
1266
1267 return 1;
1268 }
1269
1270 /* Put an array of dwords in to main memory */
1271 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
1272 uint32_t *buf, int num)
1273 {
1274 int i;
1275
1276 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1277 uint32_t tmp = cpu_to_le32(*buf);
1278 pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp));
1279 }
1280
1281 return 1;
1282 }
1283
1284 /*
1285 * Write the qh back to guest physical memory. This step isn't
1286 * in the EHCI spec but we need to do it since we don't share
1287 * physical memory with our guest VM.
1288 *
1289 * The first three dwords are read-only for the EHCI, so skip them
1290 * when writing back the qh.
1291 */
1292 static void ehci_flush_qh(EHCIQueue *q)
1293 {
1294 uint32_t *qh = (uint32_t *) &q->qh;
1295 uint32_t dwords = sizeof(EHCIqh) >> 2;
1296 uint32_t addr = NLPTR_GET(q->qhaddr);
1297
1298 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1299 }
1300
1301 // 4.10.2
1302
1303 static int ehci_qh_do_overlay(EHCIQueue *q)
1304 {
1305 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1306 int i;
1307 int dtoggle;
1308 int ping;
1309 int eps;
1310 int reload;
1311
1312 assert(p != NULL);
1313 assert(p->qtdaddr == q->qtdaddr);
1314
1315 // remember values in fields to preserve in qh after overlay
1316
1317 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1318 ping = q->qh.token & QTD_TOKEN_PING;
1319
1320 q->qh.current_qtd = p->qtdaddr;
1321 q->qh.next_qtd = p->qtd.next;
1322 q->qh.altnext_qtd = p->qtd.altnext;
1323 q->qh.token = p->qtd.token;
1324
1325
1326 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1327 if (eps == EHCI_QH_EPS_HIGH) {
1328 q->qh.token &= ~QTD_TOKEN_PING;
1329 q->qh.token |= ping;
1330 }
1331
1332 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1333 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1334
1335 for (i = 0; i < 5; i++) {
1336 q->qh.bufptr[i] = p->qtd.bufptr[i];
1337 }
1338
1339 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1340 // preserve QH DT bit
1341 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1342 q->qh.token |= dtoggle;
1343 }
1344
1345 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1346 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1347
1348 ehci_flush_qh(q);
1349
1350 return 0;
1351 }
1352
1353 static int ehci_init_transfer(EHCIPacket *p)
1354 {
1355 uint32_t cpage, offset, bytes, plen;
1356 dma_addr_t page;
1357
1358 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE);
1359 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES);
1360 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
1361 pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5);
1362
1363 while (bytes > 0) {
1364 if (cpage > 4) {
1365 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1366 return USB_RET_PROCERR;
1367 }
1368
1369 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK;
1370 page += offset;
1371 plen = bytes;
1372 if (plen > 4096 - offset) {
1373 plen = 4096 - offset;
1374 offset = 0;
1375 cpage++;
1376 }
1377
1378 qemu_sglist_add(&p->sgl, page, plen);
1379 bytes -= plen;
1380 }
1381 return 0;
1382 }
1383
1384 static void ehci_finish_transfer(EHCIQueue *q, int status)
1385 {
1386 uint32_t cpage, offset;
1387
1388 if (status > 0) {
1389 /* update cpage & offset */
1390 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1391 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1392
1393 offset += status;
1394 cpage += offset >> QTD_BUFPTR_SH;
1395 offset &= ~QTD_BUFPTR_MASK;
1396
1397 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1398 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1399 q->qh.bufptr[0] |= offset;
1400 }
1401 }
1402
1403 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1404 {
1405 EHCIPacket *p;
1406 EHCIState *s = port->opaque;
1407 uint32_t portsc = s->portsc[port->index];
1408
1409 if (portsc & PORTSC_POWNER) {
1410 USBPort *companion = s->companion_ports[port->index];
1411 companion->ops->complete(companion, packet);
1412 return;
1413 }
1414
1415 p = container_of(packet, EHCIPacket, packet);
1416 trace_usb_ehci_packet_action(p->queue, p, "wakeup");
1417 assert(p->async == EHCI_ASYNC_INFLIGHT);
1418 p->async = EHCI_ASYNC_FINISHED;
1419 p->usb_status = packet->result;
1420
1421 if (p->queue->async) {
1422 qemu_bh_schedule(p->queue->ehci->async_bh);
1423 }
1424 }
1425
1426 static void ehci_execute_complete(EHCIQueue *q)
1427 {
1428 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1429
1430 assert(p != NULL);
1431 assert(p->qtdaddr == q->qtdaddr);
1432 assert(p->async != EHCI_ASYNC_INFLIGHT);
1433 p->async = EHCI_ASYNC_NONE;
1434
1435 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1436 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1437
1438 if (p->usb_status < 0) {
1439 switch (p->usb_status) {
1440 case USB_RET_IOERROR:
1441 case USB_RET_NODEV:
1442 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1443 set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
1444 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1445 break;
1446 case USB_RET_STALL:
1447 q->qh.token |= QTD_TOKEN_HALT;
1448 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1449 break;
1450 case USB_RET_NAK:
1451 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
1452 return; /* We're not done yet with this transaction */
1453 case USB_RET_BABBLE:
1454 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1455 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1456 break;
1457 default:
1458 /* should not be triggerable */
1459 fprintf(stderr, "USB invalid response %d\n", p->usb_status);
1460 assert(0);
1461 break;
1462 }
1463 } else if ((p->usb_status > p->tbytes) && (p->pid == USB_TOKEN_IN)) {
1464 p->usb_status = USB_RET_BABBLE;
1465 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1466 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1467 } else {
1468 // TODO check 4.12 for splits
1469
1470 if (p->tbytes && p->pid == USB_TOKEN_IN) {
1471 p->tbytes -= p->usb_status;
1472 } else {
1473 p->tbytes = 0;
1474 }
1475
1476 DPRINTF("updating tbytes to %d\n", p->tbytes);
1477 set_field(&q->qh.token, p->tbytes, QTD_TOKEN_TBYTES);
1478 }
1479 ehci_finish_transfer(q, p->usb_status);
1480 usb_packet_unmap(&p->packet, &p->sgl);
1481 qemu_sglist_destroy(&p->sgl);
1482
1483 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1484 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1485
1486 if (q->qh.token & QTD_TOKEN_IOC) {
1487 ehci_raise_irq(q->ehci, USBSTS_INT);
1488 }
1489 }
1490
1491 // 4.10.3
1492
1493 static int ehci_execute(EHCIPacket *p, const char *action)
1494 {
1495 USBEndpoint *ep;
1496 int ret;
1497 int endp;
1498
1499 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
1500 fprintf(stderr, "Attempting to execute inactive qtd\n");
1501 return USB_RET_PROCERR;
1502 }
1503
1504 p->tbytes = (p->qtd.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1505 if (p->tbytes > BUFF_SIZE) {
1506 fprintf(stderr, "Request for more bytes than allowed\n");
1507 return USB_RET_PROCERR;
1508 }
1509
1510 p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1511 switch (p->pid) {
1512 case 0:
1513 p->pid = USB_TOKEN_OUT;
1514 break;
1515 case 1:
1516 p->pid = USB_TOKEN_IN;
1517 break;
1518 case 2:
1519 p->pid = USB_TOKEN_SETUP;
1520 break;
1521 default:
1522 fprintf(stderr, "bad token\n");
1523 break;
1524 }
1525
1526 if (ehci_init_transfer(p) != 0) {
1527 return USB_RET_PROCERR;
1528 }
1529
1530 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP);
1531 ep = usb_ep_get(p->queue->dev, p->pid, endp);
1532
1533 usb_packet_setup(&p->packet, p->pid, ep, p->qtdaddr);
1534 usb_packet_map(&p->packet, &p->sgl);
1535
1536 trace_usb_ehci_packet_action(p->queue, p, action);
1537 ret = usb_handle_packet(p->queue->dev, &p->packet);
1538 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1539 "(total %d) endp %x ret %d\n",
1540 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1541 q->packet.iov.size, q->tbytes, endp, ret);
1542
1543 if (ret > BUFF_SIZE) {
1544 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1545 return USB_RET_PROCERR;
1546 }
1547
1548 return ret;
1549 }
1550
1551 /* 4.7.2
1552 */
1553
1554 static int ehci_process_itd(EHCIState *ehci,
1555 EHCIitd *itd,
1556 uint32_t addr)
1557 {
1558 USBDevice *dev;
1559 USBEndpoint *ep;
1560 int ret;
1561 uint32_t i, len, pid, dir, devaddr, endp;
1562 uint32_t pg, off, ptr1, ptr2, max, mult;
1563
1564 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1565 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1566 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1567 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1568 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1569
1570 for(i = 0; i < 8; i++) {
1571 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1572 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1573 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1574 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1575 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1576 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1577
1578 if (len > max * mult) {
1579 len = max * mult;
1580 }
1581
1582 if (len > BUFF_SIZE) {
1583 return USB_RET_PROCERR;
1584 }
1585
1586 pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2);
1587 if (off + len > 4096) {
1588 /* transfer crosses page border */
1589 uint32_t len2 = off + len - 4096;
1590 uint32_t len1 = len - len2;
1591 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1592 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1593 } else {
1594 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1595 }
1596
1597 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1598
1599 dev = ehci_find_device(ehci, devaddr);
1600 ep = usb_ep_get(dev, pid, endp);
1601 if (ep->type == USB_ENDPOINT_XFER_ISOC) {
1602 usb_packet_setup(&ehci->ipacket, pid, ep, addr);
1603 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1604 ret = usb_handle_packet(dev, &ehci->ipacket);
1605 assert(ret != USB_RET_ASYNC);
1606 usb_packet_unmap(&ehci->ipacket, &ehci->isgl);
1607 } else {
1608 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1609 ret = USB_RET_NAK;
1610 }
1611 qemu_sglist_destroy(&ehci->isgl);
1612
1613 if (ret < 0) {
1614 switch (ret) {
1615 default:
1616 fprintf(stderr, "Unexpected iso usb result: %d\n", ret);
1617 /* Fall through */
1618 case USB_RET_IOERROR:
1619 case USB_RET_NODEV:
1620 /* 3.3.2: XACTERR is only allowed on IN transactions */
1621 if (dir) {
1622 itd->transact[i] |= ITD_XACT_XACTERR;
1623 ehci_raise_irq(ehci, USBSTS_ERRINT);
1624 }
1625 break;
1626 case USB_RET_BABBLE:
1627 itd->transact[i] |= ITD_XACT_BABBLE;
1628 ehci_raise_irq(ehci, USBSTS_ERRINT);
1629 break;
1630 case USB_RET_NAK:
1631 /* no data for us, so do a zero-length transfer */
1632 ret = 0;
1633 break;
1634 }
1635 }
1636 if (ret >= 0) {
1637 if (!dir) {
1638 /* OUT */
1639 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1640 } else {
1641 /* IN */
1642 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1643 }
1644 }
1645 if (itd->transact[i] & ITD_XACT_IOC) {
1646 ehci_raise_irq(ehci, USBSTS_INT);
1647 }
1648 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1649 }
1650 }
1651 return 0;
1652 }
1653
1654
1655 /* This state is the entry point for asynchronous schedule
1656 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1657 */
1658 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1659 {
1660 EHCIqh qh;
1661 int i = 0;
1662 int again = 0;
1663 uint32_t entry = ehci->asynclistaddr;
1664
1665 /* set reclamation flag at start event (4.8.6) */
1666 if (async) {
1667 ehci_set_usbsts(ehci, USBSTS_REC);
1668 }
1669
1670 ehci_queues_rip_unused(ehci, async);
1671
1672 /* Find the head of the list (4.9.1.1) */
1673 for(i = 0; i < MAX_QH; i++) {
1674 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1675 sizeof(EHCIqh) >> 2);
1676 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1677
1678 if (qh.epchar & QH_EPCHAR_H) {
1679 if (async) {
1680 entry |= (NLPTR_TYPE_QH << 1);
1681 }
1682
1683 ehci_set_fetch_addr(ehci, async, entry);
1684 ehci_set_state(ehci, async, EST_FETCHENTRY);
1685 again = 1;
1686 goto out;
1687 }
1688
1689 entry = qh.next;
1690 if (entry == ehci->asynclistaddr) {
1691 break;
1692 }
1693 }
1694
1695 /* no head found for list. */
1696
1697 ehci_set_state(ehci, async, EST_ACTIVE);
1698
1699 out:
1700 return again;
1701 }
1702
1703
1704 /* This state is the entry point for periodic schedule processing as
1705 * well as being a continuation state for async processing.
1706 */
1707 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1708 {
1709 int again = 0;
1710 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1711
1712 if (NLPTR_TBIT(entry)) {
1713 ehci_set_state(ehci, async, EST_ACTIVE);
1714 goto out;
1715 }
1716
1717 /* section 4.8, only QH in async schedule */
1718 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1719 fprintf(stderr, "non queue head request in async schedule\n");
1720 return -1;
1721 }
1722
1723 switch (NLPTR_TYPE_GET(entry)) {
1724 case NLPTR_TYPE_QH:
1725 ehci_set_state(ehci, async, EST_FETCHQH);
1726 again = 1;
1727 break;
1728
1729 case NLPTR_TYPE_ITD:
1730 ehci_set_state(ehci, async, EST_FETCHITD);
1731 again = 1;
1732 break;
1733
1734 case NLPTR_TYPE_STITD:
1735 ehci_set_state(ehci, async, EST_FETCHSITD);
1736 again = 1;
1737 break;
1738
1739 default:
1740 /* TODO: handle FSTN type */
1741 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1742 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1743 return -1;
1744 }
1745
1746 out:
1747 return again;
1748 }
1749
1750 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1751 {
1752 EHCIPacket *p;
1753 uint32_t entry, devaddr;
1754 EHCIQueue *q;
1755 EHCIqh qh;
1756
1757 entry = ehci_get_fetch_addr(ehci, async);
1758 q = ehci_find_queue_by_qh(ehci, entry, async);
1759 if (NULL == q) {
1760 q = ehci_alloc_queue(ehci, entry, async);
1761 }
1762 p = QTAILQ_FIRST(&q->packets);
1763
1764 q->seen++;
1765 if (q->seen > 1) {
1766 /* we are going in circles -- stop processing */
1767 ehci_set_state(ehci, async, EST_ACTIVE);
1768 q = NULL;
1769 goto out;
1770 }
1771
1772 get_dwords(ehci, NLPTR_GET(q->qhaddr),
1773 (uint32_t *) &qh, sizeof(EHCIqh) >> 2);
1774 if (q->revalidate && (q->qh.epchar != qh.epchar ||
1775 q->qh.epcap != qh.epcap ||
1776 q->qh.current_qtd != qh.current_qtd)) {
1777 ehci_free_queue(q);
1778 q = ehci_alloc_queue(ehci, entry, async);
1779 q->seen++;
1780 p = NULL;
1781 }
1782 q->qh = qh;
1783 q->revalidate = 0;
1784 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1785
1786 devaddr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1787 if (q->dev != NULL && q->dev->addr != devaddr) {
1788 if (!QTAILQ_EMPTY(&q->packets)) {
1789 /* should not happen (guest bug) */
1790 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) {
1791 ehci_free_packet(p);
1792 }
1793 }
1794 q->dev = NULL;
1795 }
1796 if (q->dev == NULL) {
1797 q->dev = ehci_find_device(q->ehci, devaddr);
1798 }
1799
1800 if (p && p->async == EHCI_ASYNC_INFLIGHT) {
1801 /* I/O still in progress -- skip queue */
1802 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1803 goto out;
1804 }
1805 if (p && p->async == EHCI_ASYNC_FINISHED) {
1806 /* I/O finished -- continue processing queue */
1807 trace_usb_ehci_packet_action(p->queue, p, "complete");
1808 ehci_set_state(ehci, async, EST_EXECUTING);
1809 goto out;
1810 }
1811
1812 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1813
1814 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1815 if (ehci->usbsts & USBSTS_REC) {
1816 ehci_clear_usbsts(ehci, USBSTS_REC);
1817 } else {
1818 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1819 " - done processing\n", q->qhaddr);
1820 ehci_set_state(ehci, async, EST_ACTIVE);
1821 q = NULL;
1822 goto out;
1823 }
1824 }
1825
1826 #if EHCI_DEBUG
1827 if (q->qhaddr != q->qh.next) {
1828 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1829 q->qhaddr,
1830 q->qh.epchar & QH_EPCHAR_H,
1831 q->qh.token & QTD_TOKEN_HALT,
1832 q->qh.token & QTD_TOKEN_ACTIVE,
1833 q->qh.next);
1834 }
1835 #endif
1836
1837 if (q->qh.token & QTD_TOKEN_HALT) {
1838 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1839
1840 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) &&
1841 (NLPTR_TBIT(q->qh.current_qtd) == 0)) {
1842 q->qtdaddr = q->qh.current_qtd;
1843 ehci_set_state(ehci, async, EST_FETCHQTD);
1844
1845 } else {
1846 /* EHCI spec version 1.0 Section 4.10.2 */
1847 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1848 }
1849
1850 out:
1851 return q;
1852 }
1853
1854 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1855 {
1856 uint32_t entry;
1857 EHCIitd itd;
1858
1859 assert(!async);
1860 entry = ehci_get_fetch_addr(ehci, async);
1861
1862 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1863 sizeof(EHCIitd) >> 2);
1864 ehci_trace_itd(ehci, entry, &itd);
1865
1866 if (ehci_process_itd(ehci, &itd, entry) != 0) {
1867 return -1;
1868 }
1869
1870 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1871 sizeof(EHCIitd) >> 2);
1872 ehci_set_fetch_addr(ehci, async, itd.next);
1873 ehci_set_state(ehci, async, EST_FETCHENTRY);
1874
1875 return 1;
1876 }
1877
1878 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1879 {
1880 uint32_t entry;
1881 EHCIsitd sitd;
1882
1883 assert(!async);
1884 entry = ehci_get_fetch_addr(ehci, async);
1885
1886 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1887 sizeof(EHCIsitd) >> 2);
1888 ehci_trace_sitd(ehci, entry, &sitd);
1889
1890 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1891 /* siTD is not active, nothing to do */;
1892 } else {
1893 /* TODO: split transfers are not implemented */
1894 fprintf(stderr, "WARNING: Skipping active siTD\n");
1895 }
1896
1897 ehci_set_fetch_addr(ehci, async, sitd.next);
1898 ehci_set_state(ehci, async, EST_FETCHENTRY);
1899 return 1;
1900 }
1901
1902 /* Section 4.10.2 - paragraph 3 */
1903 static int ehci_state_advqueue(EHCIQueue *q)
1904 {
1905 #if 0
1906 /* TO-DO: 4.10.2 - paragraph 2
1907 * if I-bit is set to 1 and QH is not active
1908 * go to horizontal QH
1909 */
1910 if (I-bit set) {
1911 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1912 goto out;
1913 }
1914 #endif
1915
1916 /*
1917 * want data and alt-next qTD is valid
1918 */
1919 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1920 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1921 q->qtdaddr = q->qh.altnext_qtd;
1922 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1923
1924 /*
1925 * next qTD is valid
1926 */
1927 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) {
1928 q->qtdaddr = q->qh.next_qtd;
1929 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1930
1931 /*
1932 * no valid qTD, try next QH
1933 */
1934 } else {
1935 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1936 }
1937
1938 return 1;
1939 }
1940
1941 /* Section 4.10.2 - paragraph 4 */
1942 static int ehci_state_fetchqtd(EHCIQueue *q)
1943 {
1944 EHCIqtd qtd;
1945 EHCIPacket *p;
1946 int again = 0;
1947
1948 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd,
1949 sizeof(EHCIqtd) >> 2);
1950 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd);
1951
1952 p = QTAILQ_FIRST(&q->packets);
1953 while (p != NULL && p->qtdaddr != q->qtdaddr) {
1954 /* should not happen (guest bug) */
1955 ehci_free_packet(p);
1956 p = QTAILQ_FIRST(&q->packets);
1957 }
1958 if (p != NULL) {
1959 ehci_qh_do_overlay(q);
1960 ehci_flush_qh(q);
1961 if (p->async == EHCI_ASYNC_INFLIGHT) {
1962 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1963 } else {
1964 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1965 }
1966 again = 1;
1967 } else if (qtd.token & QTD_TOKEN_ACTIVE) {
1968 p = ehci_alloc_packet(q);
1969 p->qtdaddr = q->qtdaddr;
1970 p->qtd = qtd;
1971 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1972 again = 1;
1973 } else {
1974 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1975 again = 1;
1976 }
1977
1978 return again;
1979 }
1980
1981 static int ehci_state_horizqh(EHCIQueue *q)
1982 {
1983 int again = 0;
1984
1985 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
1986 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next);
1987 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY);
1988 again = 1;
1989 } else {
1990 ehci_set_state(q->ehci, q->async, EST_ACTIVE);
1991 }
1992
1993 return again;
1994 }
1995
1996 static void ehci_fill_queue(EHCIPacket *p)
1997 {
1998 EHCIQueue *q = p->queue;
1999 EHCIqtd qtd = p->qtd;
2000 uint32_t qtdaddr;
2001
2002 for (;;) {
2003 if (NLPTR_TBIT(qtd.altnext) == 0) {
2004 break;
2005 }
2006 if (NLPTR_TBIT(qtd.next) != 0) {
2007 break;
2008 }
2009 qtdaddr = qtd.next;
2010 get_dwords(q->ehci, NLPTR_GET(qtdaddr),
2011 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2);
2012 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd);
2013 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
2014 break;
2015 }
2016 p = ehci_alloc_packet(q);
2017 p->qtdaddr = qtdaddr;
2018 p->qtd = qtd;
2019 p->usb_status = ehci_execute(p, "queue");
2020 assert(p->usb_status == USB_RET_ASYNC);
2021 p->async = EHCI_ASYNC_INFLIGHT;
2022 }
2023 }
2024
2025 static int ehci_state_execute(EHCIQueue *q)
2026 {
2027 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2028 int again = 0;
2029
2030 assert(p != NULL);
2031 assert(p->qtdaddr == q->qtdaddr);
2032
2033 if (ehci_qh_do_overlay(q) != 0) {
2034 return -1;
2035 }
2036
2037 // TODO verify enough time remains in the uframe as in 4.4.1.1
2038 // TODO write back ptr to async list when done or out of time
2039 // TODO Windows does not seem to ever set the MULT field
2040
2041 if (!q->async) {
2042 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
2043 if (!transactCtr) {
2044 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2045 again = 1;
2046 goto out;
2047 }
2048 }
2049
2050 if (q->async) {
2051 ehci_set_usbsts(q->ehci, USBSTS_REC);
2052 }
2053
2054 p->usb_status = ehci_execute(p, "process");
2055 if (p->usb_status == USB_RET_PROCERR) {
2056 again = -1;
2057 goto out;
2058 }
2059 if (p->usb_status == USB_RET_ASYNC) {
2060 ehci_flush_qh(q);
2061 trace_usb_ehci_packet_action(p->queue, p, "async");
2062 p->async = EHCI_ASYNC_INFLIGHT;
2063 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2064 again = 1;
2065 ehci_fill_queue(p);
2066 goto out;
2067 }
2068
2069 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
2070 again = 1;
2071
2072 out:
2073 return again;
2074 }
2075
2076 static int ehci_state_executing(EHCIQueue *q)
2077 {
2078 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2079 int again = 0;
2080
2081 assert(p != NULL);
2082 assert(p->qtdaddr == q->qtdaddr);
2083
2084 ehci_execute_complete(q);
2085 if (p->usb_status == USB_RET_ASYNC) {
2086 goto out;
2087 }
2088 if (p->usb_status == USB_RET_PROCERR) {
2089 again = -1;
2090 goto out;
2091 }
2092
2093 // 4.10.3
2094 if (!q->async) {
2095 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
2096 transactCtr--;
2097 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
2098 // 4.10.3, bottom of page 82, should exit this state when transaction
2099 // counter decrements to 0
2100 }
2101
2102 /* 4.10.5 */
2103 if (p->usb_status == USB_RET_NAK) {
2104 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2105 } else {
2106 ehci_set_state(q->ehci, q->async, EST_WRITEBACK);
2107 }
2108
2109 again = 1;
2110
2111 out:
2112 ehci_flush_qh(q);
2113 return again;
2114 }
2115
2116
2117 static int ehci_state_writeback(EHCIQueue *q)
2118 {
2119 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2120 uint32_t *qtd, addr;
2121 int again = 0;
2122
2123 /* Write back the QTD from the QH area */
2124 assert(p != NULL);
2125 assert(p->qtdaddr == q->qtdaddr);
2126
2127 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd);
2128 qtd = (uint32_t *) &q->qh.next_qtd;
2129 addr = NLPTR_GET(p->qtdaddr);
2130 put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2);
2131 ehci_free_packet(p);
2132
2133 /*
2134 * EHCI specs say go horizontal here.
2135 *
2136 * We can also advance the queue here for performance reasons. We
2137 * need to take care to only take that shortcut in case we've
2138 * processed the qtd just written back without errors, i.e. halt
2139 * bit is clear.
2140 */
2141 if (q->qh.token & QTD_TOKEN_HALT) {
2142 /*
2143 * We should not do any further processing on a halted queue!
2144 * This is esp. important for bulk endpoints with pipelining enabled
2145 * (redirection to a real USB device), where we must cancel all the
2146 * transfers after this one so that:
2147 * 1) If they've completed already, they are not processed further
2148 * causing more stalls, originating from the same failed transfer
2149 * 2) If still in flight, they are cancelled before the guest does
2150 * a clear stall, otherwise the guest and device can loose sync!
2151 */
2152 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) {
2153 ehci_free_packet(p);
2154 }
2155 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2156 again = 1;
2157 } else {
2158 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE);
2159 again = 1;
2160 }
2161 return again;
2162 }
2163
2164 /*
2165 * This is the state machine that is common to both async and periodic
2166 */
2167
2168 static void ehci_advance_state(EHCIState *ehci, int async)
2169 {
2170 EHCIQueue *q = NULL;
2171 int again;
2172
2173 do {
2174 switch(ehci_get_state(ehci, async)) {
2175 case EST_WAITLISTHEAD:
2176 again = ehci_state_waitlisthead(ehci, async);
2177 break;
2178
2179 case EST_FETCHENTRY:
2180 again = ehci_state_fetchentry(ehci, async);
2181 break;
2182
2183 case EST_FETCHQH:
2184 q = ehci_state_fetchqh(ehci, async);
2185 if (q != NULL) {
2186 assert(q->async == async);
2187 again = 1;
2188 } else {
2189 again = 0;
2190 }
2191 break;
2192
2193 case EST_FETCHITD:
2194 again = ehci_state_fetchitd(ehci, async);
2195 break;
2196
2197 case EST_FETCHSITD:
2198 again = ehci_state_fetchsitd(ehci, async);
2199 break;
2200
2201 case EST_ADVANCEQUEUE:
2202 again = ehci_state_advqueue(q);
2203 break;
2204
2205 case EST_FETCHQTD:
2206 again = ehci_state_fetchqtd(q);
2207 break;
2208
2209 case EST_HORIZONTALQH:
2210 again = ehci_state_horizqh(q);
2211 break;
2212
2213 case EST_EXECUTE:
2214 again = ehci_state_execute(q);
2215 if (async) {
2216 ehci->async_stepdown = 0;
2217 }
2218 break;
2219
2220 case EST_EXECUTING:
2221 assert(q != NULL);
2222 if (async) {
2223 ehci->async_stepdown = 0;
2224 }
2225 again = ehci_state_executing(q);
2226 break;
2227
2228 case EST_WRITEBACK:
2229 assert(q != NULL);
2230 again = ehci_state_writeback(q);
2231 break;
2232
2233 default:
2234 fprintf(stderr, "Bad state!\n");
2235 again = -1;
2236 assert(0);
2237 break;
2238 }
2239
2240 if (again < 0) {
2241 fprintf(stderr, "processing error - resetting ehci HC\n");
2242 ehci_reset(ehci);
2243 again = 0;
2244 }
2245 }
2246 while (again);
2247 }
2248
2249 static void ehci_advance_async_state(EHCIState *ehci)
2250 {
2251 const int async = 1;
2252
2253 switch(ehci_get_state(ehci, async)) {
2254 case EST_INACTIVE:
2255 if (!ehci_async_enabled(ehci)) {
2256 break;
2257 }
2258 ehci_set_state(ehci, async, EST_ACTIVE);
2259 // No break, fall through to ACTIVE
2260
2261 case EST_ACTIVE:
2262 if (!ehci_async_enabled(ehci)) {
2263 ehci_queues_rip_all(ehci, async);
2264 ehci_set_state(ehci, async, EST_INACTIVE);
2265 break;
2266 }
2267
2268 /* make sure guest has acknowledged the doorbell interrupt */
2269 /* TO-DO: is this really needed? */
2270 if (ehci->usbsts & USBSTS_IAA) {
2271 DPRINTF("IAA status bit still set.\n");
2272 break;
2273 }
2274
2275 /* check that address register has been set */
2276 if (ehci->asynclistaddr == 0) {
2277 break;
2278 }
2279
2280 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2281 ehci_advance_state(ehci, async);
2282
2283 /* If the doorbell is set, the guest wants to make a change to the
2284 * schedule. The host controller needs to release cached data.
2285 * (section 4.8.2)
2286 */
2287 if (ehci->usbcmd & USBCMD_IAAD) {
2288 /* Remove all unseen qhs from the async qhs queue */
2289 ehci_queues_tag_unused_async(ehci);
2290 DPRINTF("ASYNC: doorbell request acknowledged\n");
2291 ehci->usbcmd &= ~USBCMD_IAAD;
2292 ehci_raise_irq(ehci, USBSTS_IAA);
2293 }
2294 break;
2295
2296 default:
2297 /* this should only be due to a developer mistake */
2298 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2299 "Resetting to active\n", ehci->astate);
2300 assert(0);
2301 }
2302 }
2303
2304 static void ehci_advance_periodic_state(EHCIState *ehci)
2305 {
2306 uint32_t entry;
2307 uint32_t list;
2308 const int async = 0;
2309
2310 // 4.6
2311
2312 switch(ehci_get_state(ehci, async)) {
2313 case EST_INACTIVE:
2314 if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) {
2315 ehci_set_state(ehci, async, EST_ACTIVE);
2316 // No break, fall through to ACTIVE
2317 } else
2318 break;
2319
2320 case EST_ACTIVE:
2321 if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) {
2322 ehci_queues_rip_all(ehci, async);
2323 ehci_set_state(ehci, async, EST_INACTIVE);
2324 break;
2325 }
2326
2327 list = ehci->periodiclistbase & 0xfffff000;
2328 /* check that register has been set */
2329 if (list == 0) {
2330 break;
2331 }
2332 list |= ((ehci->frindex & 0x1ff8) >> 1);
2333
2334 pci_dma_read(&ehci->dev, list, &entry, sizeof entry);
2335 entry = le32_to_cpu(entry);
2336
2337 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2338 ehci->frindex / 8, list, entry);
2339 ehci_set_fetch_addr(ehci, async,entry);
2340 ehci_set_state(ehci, async, EST_FETCHENTRY);
2341 ehci_advance_state(ehci, async);
2342 ehci_queues_rip_unused(ehci, async);
2343 break;
2344
2345 default:
2346 /* this should only be due to a developer mistake */
2347 fprintf(stderr, "ehci: Bad periodic state %d. "
2348 "Resetting to active\n", ehci->pstate);
2349 assert(0);
2350 }
2351 }
2352
2353 static void ehci_update_frindex(EHCIState *ehci, int frames)
2354 {
2355 int i;
2356
2357 if (!ehci_enabled(ehci)) {
2358 return;
2359 }
2360
2361 for (i = 0; i < frames; i++) {
2362 ehci->frindex += 8;
2363
2364 if (ehci->frindex == 0x00002000) {
2365 ehci_raise_irq(ehci, USBSTS_FLR);
2366 }
2367
2368 if (ehci->frindex == 0x00004000) {
2369 ehci_raise_irq(ehci, USBSTS_FLR);
2370 ehci->frindex = 0;
2371 if (ehci->usbsts_frindex > 0x00004000) {
2372 ehci->usbsts_frindex -= 0x00004000;
2373 } else {
2374 ehci->usbsts_frindex = 0;
2375 }
2376 }
2377 }
2378 }
2379
2380 static void ehci_frame_timer(void *opaque)
2381 {
2382 EHCIState *ehci = opaque;
2383 int need_timer = 0;
2384 int64_t expire_time, t_now;
2385 uint64_t ns_elapsed;
2386 int frames, skipped_frames;
2387 int i;
2388
2389 t_now = qemu_get_clock_ns(vm_clock);
2390 ns_elapsed = t_now - ehci->last_run_ns;
2391 frames = ns_elapsed / FRAME_TIMER_NS;
2392
2393 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) {
2394 need_timer++;
2395 ehci->async_stepdown = 0;
2396
2397 if (frames > ehci->maxframes) {
2398 skipped_frames = frames - ehci->maxframes;
2399 ehci_update_frindex(ehci, skipped_frames);
2400 ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames;
2401 frames -= skipped_frames;
2402 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2403 }
2404
2405 for (i = 0; i < frames; i++) {
2406 ehci_update_frindex(ehci, 1);
2407 ehci_advance_periodic_state(ehci);
2408 ehci->last_run_ns += FRAME_TIMER_NS;
2409 }
2410 } else {
2411 if (ehci->async_stepdown < ehci->maxframes / 2) {
2412 ehci->async_stepdown++;
2413 }
2414 ehci_update_frindex(ehci, frames);
2415 ehci->last_run_ns += FRAME_TIMER_NS * frames;
2416 }
2417
2418 /* Async is not inside loop since it executes everything it can once
2419 * called
2420 */
2421 if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
2422 need_timer++;
2423 ehci_advance_async_state(ehci);
2424 }
2425
2426 ehci_commit_irq(ehci);
2427 if (ehci->usbsts_pending) {
2428 need_timer++;
2429 ehci->async_stepdown = 0;
2430 }
2431
2432 if (need_timer) {
2433 expire_time = t_now + (get_ticks_per_sec()
2434 * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ);
2435 qemu_mod_timer(ehci->frame_timer, expire_time);
2436 }
2437 }
2438
2439 static void ehci_async_bh(void *opaque)
2440 {
2441 EHCIState *ehci = opaque;
2442 ehci_advance_async_state(ehci);
2443 }
2444
2445 static const MemoryRegionOps ehci_mem_ops = {
2446 .old_mmio = {
2447 .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
2448 .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
2449 },
2450 .endianness = DEVICE_LITTLE_ENDIAN,
2451 };
2452
2453 static int usb_ehci_initfn(PCIDevice *dev);
2454
2455 static USBPortOps ehci_port_ops = {
2456 .attach = ehci_attach,
2457 .detach = ehci_detach,
2458 .child_detach = ehci_child_detach,
2459 .wakeup = ehci_wakeup,
2460 .complete = ehci_async_complete_packet,
2461 };
2462
2463 static USBBusOps ehci_bus_ops = {
2464 .register_companion = ehci_register_companion,
2465 };
2466
2467 static int usb_ehci_post_load(void *opaque, int version_id)
2468 {
2469 EHCIState *s = opaque;
2470 int i;
2471
2472 for (i = 0; i < NB_PORTS; i++) {
2473 USBPort *companion = s->companion_ports[i];
2474 if (companion == NULL) {
2475 continue;
2476 }
2477 if (s->portsc[i] & PORTSC_POWNER) {
2478 companion->dev = s->ports[i].dev;
2479 } else {
2480 companion->dev = NULL;
2481 }
2482 }
2483
2484 return 0;
2485 }
2486
2487 static const VMStateDescription vmstate_ehci = {
2488 .name = "ehci",
2489 .version_id = 2,
2490 .minimum_version_id = 1,
2491 .post_load = usb_ehci_post_load,
2492 .fields = (VMStateField[]) {
2493 VMSTATE_PCI_DEVICE(dev, EHCIState),
2494 /* mmio registers */
2495 VMSTATE_UINT32(usbcmd, EHCIState),
2496 VMSTATE_UINT32(usbsts, EHCIState),
2497 VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2),
2498 VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2),
2499 VMSTATE_UINT32(usbintr, EHCIState),
2500 VMSTATE_UINT32(frindex, EHCIState),
2501 VMSTATE_UINT32(ctrldssegment, EHCIState),
2502 VMSTATE_UINT32(periodiclistbase, EHCIState),
2503 VMSTATE_UINT32(asynclistaddr, EHCIState),
2504 VMSTATE_UINT32(configflag, EHCIState),
2505 VMSTATE_UINT32(portsc[0], EHCIState),
2506 VMSTATE_UINT32(portsc[1], EHCIState),
2507 VMSTATE_UINT32(portsc[2], EHCIState),
2508 VMSTATE_UINT32(portsc[3], EHCIState),
2509 VMSTATE_UINT32(portsc[4], EHCIState),
2510 VMSTATE_UINT32(portsc[5], EHCIState),
2511 /* frame timer */
2512 VMSTATE_TIMER(frame_timer, EHCIState),
2513 VMSTATE_UINT64(last_run_ns, EHCIState),
2514 VMSTATE_UINT32(async_stepdown, EHCIState),
2515 /* schedule state */
2516 VMSTATE_UINT32(astate, EHCIState),
2517 VMSTATE_UINT32(pstate, EHCIState),
2518 VMSTATE_UINT32(a_fetch_addr, EHCIState),
2519 VMSTATE_UINT32(p_fetch_addr, EHCIState),
2520 VMSTATE_END_OF_LIST()
2521 }
2522 };
2523
2524 static Property ehci_properties[] = {
2525 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128),
2526 DEFINE_PROP_END_OF_LIST(),
2527 };
2528
2529 static void ehci_class_init(ObjectClass *klass, void *data)
2530 {
2531 DeviceClass *dc = DEVICE_CLASS(klass);
2532 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2533
2534 k->init = usb_ehci_initfn;
2535 k->vendor_id = PCI_VENDOR_ID_INTEL;
2536 k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */
2537 k->revision = 0x10;
2538 k->class_id = PCI_CLASS_SERIAL_USB;
2539 dc->vmsd = &vmstate_ehci;
2540 dc->props = ehci_properties;
2541 }
2542
2543 static TypeInfo ehci_info = {
2544 .name = "usb-ehci",
2545 .parent = TYPE_PCI_DEVICE,
2546 .instance_size = sizeof(EHCIState),
2547 .class_init = ehci_class_init,
2548 };
2549
2550 static void ich9_ehci_class_init(ObjectClass *klass, void *data)
2551 {
2552 DeviceClass *dc = DEVICE_CLASS(klass);
2553 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2554
2555 k->init = usb_ehci_initfn;
2556 k->vendor_id = PCI_VENDOR_ID_INTEL;
2557 k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1;
2558 k->revision = 0x03;
2559 k->class_id = PCI_CLASS_SERIAL_USB;
2560 dc->vmsd = &vmstate_ehci;
2561 dc->props = ehci_properties;
2562 }
2563
2564 static TypeInfo ich9_ehci_info = {
2565 .name = "ich9-usb-ehci1",
2566 .parent = TYPE_PCI_DEVICE,
2567 .instance_size = sizeof(EHCIState),
2568 .class_init = ich9_ehci_class_init,
2569 };
2570
2571 static int usb_ehci_initfn(PCIDevice *dev)
2572 {
2573 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2574 uint8_t *pci_conf = s->dev.config;
2575 int i;
2576
2577 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2578
2579 /* capabilities pointer */
2580 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2581 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2582
2583 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */
2584 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2585 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2586
2587 // pci_conf[0x50] = 0x01; // power management caps
2588
2589 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
2590 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2591 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2592
2593 pci_conf[0x64] = 0x00;
2594 pci_conf[0x65] = 0x00;
2595 pci_conf[0x66] = 0x00;
2596 pci_conf[0x67] = 0x00;
2597 pci_conf[0x68] = 0x01;
2598 pci_conf[0x69] = 0x00;
2599 pci_conf[0x6a] = 0x00;
2600 pci_conf[0x6b] = 0x00; // USBLEGSUP
2601 pci_conf[0x6c] = 0x00;
2602 pci_conf[0x6d] = 0x00;
2603 pci_conf[0x6e] = 0x00;
2604 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2605
2606 // 2.2 host controller interface version
2607 s->mmio[0x00] = (uint8_t) OPREGBASE;
2608 s->mmio[0x01] = 0x00;
2609 s->mmio[0x02] = 0x00;
2610 s->mmio[0x03] = 0x01; // HC version
2611 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2612 s->mmio[0x05] = 0x00; // No companion ports at present
2613 s->mmio[0x06] = 0x00;
2614 s->mmio[0x07] = 0x00;
2615 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2616 s->mmio[0x09] = 0x68; // EECP
2617 s->mmio[0x0a] = 0x00;
2618 s->mmio[0x0b] = 0x00;
2619
2620 s->irq = s->dev.irq[3];
2621
2622 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2623 for(i = 0; i < NB_PORTS; i++) {
2624 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2625 USB_SPEED_MASK_HIGH);
2626 s->ports[i].dev = 0;
2627 }
2628
2629 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2630 s->async_bh = qemu_bh_new(ehci_async_bh, s);
2631 QTAILQ_INIT(&s->aqueues);
2632 QTAILQ_INIT(&s->pqueues);
2633 usb_packet_init(&s->ipacket);
2634
2635 qemu_register_reset(ehci_reset, s);
2636
2637 memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
2638 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
2639
2640 return 0;
2641 }
2642
2643 static void ehci_register_types(void)
2644 {
2645 type_register_static(&ehci_info);
2646 type_register_static(&ich9_ehci_info);
2647 }
2648
2649 type_init(ehci_register_types)
2650
2651 /*
2652 * vim: expandtab ts=4
2653 */
Qemu copy for testing