target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #if !defined(CONFIG_USER_ONLY)
  24 #include "hw/loader.h"
  25 #endif
  26 #include "sysemu/sysemu.h"
  27
  28 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  29 {
  30     /* Reset a single ARMCPRegInfo register */
  31     ARMCPRegInfo *ri = value;
  32     ARMCPU *cpu = opaque;
  33
  34     if (ri->type & ARM_CP_SPECIAL) {
  35         return;
  36     }
  37
  38     if (ri->resetfn) {
  39         ri->resetfn(&cpu->env, ri);
  40         return;
  41     }
  42
  43     /* A zero offset is never possible as it would be regs[0]
  44      * so we use it to indicate that reset is being handled elsewhere.
  45      * This is basically only used for fields in non-core coprocessors
  46      * (like the pxa2xx ones).
  47      */
  48     if (!ri->fieldoffset) {
  49         return;
  50     }
  51
  52     if (ri->type & ARM_CP_64BIT) {
  53         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  54     } else {
  55         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  56     }
  57 }
  58
  59 /* CPUClass::reset() */
  60 static void arm_cpu_reset(CPUState *s)
  61 {
  62     ARMCPU *cpu = ARM_CPU(s);
  63     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  64     CPUARMState *env = &cpu->env;
  65
  66     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
  67         qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
  68         log_cpu_state(env, 0);
  69     }
  70
  71     acc->parent_reset(s);
  72
  73     memset(env, 0, offsetof(CPUARMState, breakpoints));
  74     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  75     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  76     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  77     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  78
  79     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  80         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  81     }
  82
  83 #if defined(CONFIG_USER_ONLY)
  84     env->uncached_cpsr = ARM_CPU_MODE_USR;
  85     /* For user mode we must enable access to coprocessors */
  86     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
  87     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  88         env->cp15.c15_cpar = 3;
  89     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
  90         env->cp15.c15_cpar = 1;
  91     }
  92 #else
  93     /* SVC mode with interrupts disabled.  */
  94     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
  95     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
  96        clear at reset.  Initial SP and PC are loaded from ROM.  */
  97     if (IS_M(env)) {
  98         uint32_t pc;
  99         uint8_t *rom;
 100         env->uncached_cpsr &= ~CPSR_I;
 101         rom = rom_ptr(0);
 102         if (rom) {
 103             /* We should really use ldl_phys here, in case the guest
 104                modified flash and reset itself.  However images
 105                loaded via -kernel have not been copied yet, so load the
 106                values directly from there.  */
 107             env->regs[13] = ldl_p(rom);
 108             pc = ldl_p(rom + 4);
 109             env->thumb = pc & 1;
 110             env->regs[15] = pc & ~1;
 111         }
 112     }
 113     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 114 #endif
 115     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 116     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 117     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 118     set_float_detect_tininess(float_tininess_before_rounding,
 119                               &env->vfp.fp_status);
 120     set_float_detect_tininess(float_tininess_before_rounding,
 121                               &env->vfp.standard_fp_status);
 122     tlb_flush(env, 1);
 123     /* Reset is a state change for some CPUARMState fields which we
 124      * bake assumptions about into translated code, so we need to
 125      * tb_flush().
 126      */
 127     tb_flush(env);
 128 }
 129
 130 static inline void set_feature(CPUARMState *env, int feature)
 131 {
 132     env->features |= 1ULL << feature;
 133 }
 134
 135 static void arm_cpu_initfn(Object *obj)
 136 {
 137     ARMCPU *cpu = ARM_CPU(obj);
 138     static bool inited;
 139
 140     cpu_exec_init(&cpu->env);
 141     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 142                                          g_free, g_free);
 143
 144     if (tcg_enabled() && !inited) {
 145         inited = true;
 146         arm_translate_init();
 147     }
 148 }
 149
 150 static void arm_cpu_finalizefn(Object *obj)
 151 {
 152     ARMCPU *cpu = ARM_CPU(obj);
 153     g_hash_table_destroy(cpu->cp_regs);
 154 }
 155
 156 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 157 {
 158     ARMCPU *cpu = ARM_CPU(dev);
 159     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 160     CPUARMState *env = &cpu->env;
 161
 162     /* Some features automatically imply others: */
 163     if (arm_feature(env, ARM_FEATURE_V7)) {
 164         set_feature(env, ARM_FEATURE_VAPA);
 165         set_feature(env, ARM_FEATURE_THUMB2);
 166         set_feature(env, ARM_FEATURE_MPIDR);
 167         if (!arm_feature(env, ARM_FEATURE_M)) {
 168             set_feature(env, ARM_FEATURE_V6K);
 169         } else {
 170             set_feature(env, ARM_FEATURE_V6);
 171         }
 172     }
 173     if (arm_feature(env, ARM_FEATURE_V6K)) {
 174         set_feature(env, ARM_FEATURE_V6);
 175         set_feature(env, ARM_FEATURE_MVFR);
 176     }
 177     if (arm_feature(env, ARM_FEATURE_V6)) {
 178         set_feature(env, ARM_FEATURE_V5);
 179         if (!arm_feature(env, ARM_FEATURE_M)) {
 180             set_feature(env, ARM_FEATURE_AUXCR);
 181         }
 182     }
 183     if (arm_feature(env, ARM_FEATURE_V5)) {
 184         set_feature(env, ARM_FEATURE_V4T);
 185     }
 186     if (arm_feature(env, ARM_FEATURE_M)) {
 187         set_feature(env, ARM_FEATURE_THUMB_DIV);
 188     }
 189     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 190         set_feature(env, ARM_FEATURE_THUMB_DIV);
 191     }
 192     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 193         set_feature(env, ARM_FEATURE_VFP3);
 194     }
 195     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 196         set_feature(env, ARM_FEATURE_VFP);
 197     }
 198     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 199         set_feature(env, ARM_FEATURE_PXN);
 200     }
 201
 202     register_cp_regs_for_features(cpu);
 203     arm_cpu_register_gdb_regs_for_features(cpu);
 204
 205     cpu_reset(CPU(cpu));
 206     qemu_init_vcpu(env);
 207
 208     acc->parent_realize(dev, errp);
 209 }
 210
 211 /* CPU models */
 212
 213 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 214 {
 215     ObjectClass *oc;
 216     char *typename;
 217
 218     if (!cpu_model) {
 219         return NULL;
 220     }
 221
 222     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 223     oc = object_class_by_name(typename);
 224     g_free(typename);
 225     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 226         object_class_is_abstract(oc)) {
 227         return NULL;
 228     }
 229     return oc;
 230 }
 231
 232 static void arm926_initfn(Object *obj)
 233 {
 234     ARMCPU *cpu = ARM_CPU(obj);
 235     set_feature(&cpu->env, ARM_FEATURE_V5);
 236     set_feature(&cpu->env, ARM_FEATURE_VFP);
 237     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 238     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 239     cpu->midr = 0x41069265;
 240     cpu->reset_fpsid = 0x41011090;
 241     cpu->ctr = 0x1dd20d2;
 242     cpu->reset_sctlr = 0x00090078;
 243 }
 244
 245 static void arm946_initfn(Object *obj)
 246 {
 247     ARMCPU *cpu = ARM_CPU(obj);
 248     set_feature(&cpu->env, ARM_FEATURE_V5);
 249     set_feature(&cpu->env, ARM_FEATURE_MPU);
 250     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 251     cpu->midr = 0x41059461;
 252     cpu->ctr = 0x0f004006;
 253     cpu->reset_sctlr = 0x00000078;
 254 }
 255
 256 static void arm1026_initfn(Object *obj)
 257 {
 258     ARMCPU *cpu = ARM_CPU(obj);
 259     set_feature(&cpu->env, ARM_FEATURE_V5);
 260     set_feature(&cpu->env, ARM_FEATURE_VFP);
 261     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 262     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 263     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 264     cpu->midr = 0x4106a262;
 265     cpu->reset_fpsid = 0x410110a0;
 266     cpu->ctr = 0x1dd20d2;
 267     cpu->reset_sctlr = 0x00090078;
 268     cpu->reset_auxcr = 1;
 269     {
 270         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 271         ARMCPRegInfo ifar = {
 272             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 273             .access = PL1_RW,
 274             .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 275             .resetvalue = 0
 276         };
 277         define_one_arm_cp_reg(cpu, &ifar);
 278     }
 279 }
 280
 281 static void arm1136_r2_initfn(Object *obj)
 282 {
 283     ARMCPU *cpu = ARM_CPU(obj);
 284     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 285      * older core than plain "arm1136". In particular this does not
 286      * have the v6K features.
 287      * These ID register values are correct for 1136 but may be wrong
 288      * for 1136_r2 (in particular r0p2 does not actually implement most
 289      * of the ID registers).
 290      */
 291     set_feature(&cpu->env, ARM_FEATURE_V6);
 292     set_feature(&cpu->env, ARM_FEATURE_VFP);
 293     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 294     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 295     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 296     cpu->midr = 0x4107b362;
 297     cpu->reset_fpsid = 0x410120b4;
 298     cpu->mvfr0 = 0x11111111;
 299     cpu->mvfr1 = 0x00000000;
 300     cpu->ctr = 0x1dd20d2;
 301     cpu->reset_sctlr = 0x00050078;
 302     cpu->id_pfr0 = 0x111;
 303     cpu->id_pfr1 = 0x1;
 304     cpu->id_dfr0 = 0x2;
 305     cpu->id_afr0 = 0x3;
 306     cpu->id_mmfr0 = 0x01130003;
 307     cpu->id_mmfr1 = 0x10030302;
 308     cpu->id_mmfr2 = 0x01222110;
 309     cpu->id_isar0 = 0x00140011;
 310     cpu->id_isar1 = 0x12002111;
 311     cpu->id_isar2 = 0x11231111;
 312     cpu->id_isar3 = 0x01102131;
 313     cpu->id_isar4 = 0x141;
 314     cpu->reset_auxcr = 7;
 315 }
 316
 317 static void arm1136_initfn(Object *obj)
 318 {
 319     ARMCPU *cpu = ARM_CPU(obj);
 320     set_feature(&cpu->env, ARM_FEATURE_V6K);
 321     set_feature(&cpu->env, ARM_FEATURE_V6);
 322     set_feature(&cpu->env, ARM_FEATURE_VFP);
 323     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 324     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 325     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 326     cpu->midr = 0x4117b363;
 327     cpu->reset_fpsid = 0x410120b4;
 328     cpu->mvfr0 = 0x11111111;
 329     cpu->mvfr1 = 0x00000000;
 330     cpu->ctr = 0x1dd20d2;
 331     cpu->reset_sctlr = 0x00050078;
 332     cpu->id_pfr0 = 0x111;
 333     cpu->id_pfr1 = 0x1;
 334     cpu->id_dfr0 = 0x2;
 335     cpu->id_afr0 = 0x3;
 336     cpu->id_mmfr0 = 0x01130003;
 337     cpu->id_mmfr1 = 0x10030302;
 338     cpu->id_mmfr2 = 0x01222110;
 339     cpu->id_isar0 = 0x00140011;
 340     cpu->id_isar1 = 0x12002111;
 341     cpu->id_isar2 = 0x11231111;
 342     cpu->id_isar3 = 0x01102131;
 343     cpu->id_isar4 = 0x141;
 344     cpu->reset_auxcr = 7;
 345 }
 346
 347 static void arm1176_initfn(Object *obj)
 348 {
 349     ARMCPU *cpu = ARM_CPU(obj);
 350     set_feature(&cpu->env, ARM_FEATURE_V6K);
 351     set_feature(&cpu->env, ARM_FEATURE_VFP);
 352     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 353     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 354     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 355     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 356     cpu->midr = 0x410fb767;
 357     cpu->reset_fpsid = 0x410120b5;
 358     cpu->mvfr0 = 0x11111111;
 359     cpu->mvfr1 = 0x00000000;
 360     cpu->ctr = 0x1dd20d2;
 361     cpu->reset_sctlr = 0x00050078;
 362     cpu->id_pfr0 = 0x111;
 363     cpu->id_pfr1 = 0x11;
 364     cpu->id_dfr0 = 0x33;
 365     cpu->id_afr0 = 0;
 366     cpu->id_mmfr0 = 0x01130003;
 367     cpu->id_mmfr1 = 0x10030302;
 368     cpu->id_mmfr2 = 0x01222100;
 369     cpu->id_isar0 = 0x0140011;
 370     cpu->id_isar1 = 0x12002111;
 371     cpu->id_isar2 = 0x11231121;
 372     cpu->id_isar3 = 0x01102131;
 373     cpu->id_isar4 = 0x01141;
 374     cpu->reset_auxcr = 7;
 375 }
 376
 377 static void arm11mpcore_initfn(Object *obj)
 378 {
 379     ARMCPU *cpu = ARM_CPU(obj);
 380     set_feature(&cpu->env, ARM_FEATURE_V6K);
 381     set_feature(&cpu->env, ARM_FEATURE_VFP);
 382     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 383     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 384     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 385     cpu->midr = 0x410fb022;
 386     cpu->reset_fpsid = 0x410120b4;
 387     cpu->mvfr0 = 0x11111111;
 388     cpu->mvfr1 = 0x00000000;
 389     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 390     cpu->id_pfr0 = 0x111;
 391     cpu->id_pfr1 = 0x1;
 392     cpu->id_dfr0 = 0;
 393     cpu->id_afr0 = 0x2;
 394     cpu->id_mmfr0 = 0x01100103;
 395     cpu->id_mmfr1 = 0x10020302;
 396     cpu->id_mmfr2 = 0x01222000;
 397     cpu->id_isar0 = 0x00100011;
 398     cpu->id_isar1 = 0x12002111;
 399     cpu->id_isar2 = 0x11221011;
 400     cpu->id_isar3 = 0x01102131;
 401     cpu->id_isar4 = 0x141;
 402     cpu->reset_auxcr = 1;
 403 }
 404
 405 static void cortex_m3_initfn(Object *obj)
 406 {
 407     ARMCPU *cpu = ARM_CPU(obj);
 408     set_feature(&cpu->env, ARM_FEATURE_V7);
 409     set_feature(&cpu->env, ARM_FEATURE_M);
 410     cpu->midr = 0x410fc231;
 411 }
 412
 413 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 414     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 415       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 416     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 417       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 418     REGINFO_SENTINEL
 419 };
 420
 421 static void cortex_a8_initfn(Object *obj)
 422 {
 423     ARMCPU *cpu = ARM_CPU(obj);
 424     set_feature(&cpu->env, ARM_FEATURE_V7);
 425     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 426     set_feature(&cpu->env, ARM_FEATURE_NEON);
 427     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 428     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 429     cpu->midr = 0x410fc080;
 430     cpu->reset_fpsid = 0x410330c0;
 431     cpu->mvfr0 = 0x11110222;
 432     cpu->mvfr1 = 0x00011100;
 433     cpu->ctr = 0x82048004;
 434     cpu->reset_sctlr = 0x00c50078;
 435     cpu->id_pfr0 = 0x1031;
 436     cpu->id_pfr1 = 0x11;
 437     cpu->id_dfr0 = 0x400;
 438     cpu->id_afr0 = 0;
 439     cpu->id_mmfr0 = 0x31100003;
 440     cpu->id_mmfr1 = 0x20000000;
 441     cpu->id_mmfr2 = 0x01202000;
 442     cpu->id_mmfr3 = 0x11;
 443     cpu->id_isar0 = 0x00101111;
 444     cpu->id_isar1 = 0x12112111;
 445     cpu->id_isar2 = 0x21232031;
 446     cpu->id_isar3 = 0x11112131;
 447     cpu->id_isar4 = 0x00111142;
 448     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 449     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 450     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 451     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 452     cpu->reset_auxcr = 2;
 453     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 454 }
 455
 456 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 457     /* power_control should be set to maximum latency. Again,
 458      * default to 0 and set by private hook
 459      */
 460     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 461       .access = PL1_RW, .resetvalue = 0,
 462       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 463     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 464       .access = PL1_RW, .resetvalue = 0,
 465       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 466     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 467       .access = PL1_RW, .resetvalue = 0,
 468       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 469     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 470       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 471     /* TLB lockdown control */
 472     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 473       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 474     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 475       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 476     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 477       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 478     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 479       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 480     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 481       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 482     REGINFO_SENTINEL
 483 };
 484
 485 static void cortex_a9_initfn(Object *obj)
 486 {
 487     ARMCPU *cpu = ARM_CPU(obj);
 488     set_feature(&cpu->env, ARM_FEATURE_V7);
 489     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 490     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 491     set_feature(&cpu->env, ARM_FEATURE_NEON);
 492     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 493     /* Note that A9 supports the MP extensions even for
 494      * A9UP and single-core A9MP (which are both different
 495      * and valid configurations; we don't model A9UP).
 496      */
 497     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 498     cpu->midr = 0x410fc090;
 499     cpu->reset_fpsid = 0x41033090;
 500     cpu->mvfr0 = 0x11110222;
 501     cpu->mvfr1 = 0x01111111;
 502     cpu->ctr = 0x80038003;
 503     cpu->reset_sctlr = 0x00c50078;
 504     cpu->id_pfr0 = 0x1031;
 505     cpu->id_pfr1 = 0x11;
 506     cpu->id_dfr0 = 0x000;
 507     cpu->id_afr0 = 0;
 508     cpu->id_mmfr0 = 0x00100103;
 509     cpu->id_mmfr1 = 0x20000000;
 510     cpu->id_mmfr2 = 0x01230000;
 511     cpu->id_mmfr3 = 0x00002111;
 512     cpu->id_isar0 = 0x00101111;
 513     cpu->id_isar1 = 0x13112111;
 514     cpu->id_isar2 = 0x21232041;
 515     cpu->id_isar3 = 0x11112131;
 516     cpu->id_isar4 = 0x00111142;
 517     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 518     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 519     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 520     {
 521         ARMCPRegInfo cbar = {
 522             .name = "CBAR", .cp = 15, .crn = 15,  .crm = 0, .opc1 = 4,
 523             .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
 524             .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
 525         };
 526         define_one_arm_cp_reg(cpu, &cbar);
 527         define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 528     }
 529 }
 530
 531 #ifndef CONFIG_USER_ONLY
 532 static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
 533                            uint64_t *value)
 534 {
 535     /* Linux wants the number of processors from here.
 536      * Might as well set the interrupt-controller bit too.
 537      */
 538     *value = ((smp_cpus - 1) << 24) | (1 << 23);
 539     return 0;
 540 }
 541 #endif
 542
 543 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 544 #ifndef CONFIG_USER_ONLY
 545     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 546       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 547       .writefn = arm_cp_write_ignore, },
 548 #endif
 549     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 550       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 551     REGINFO_SENTINEL
 552 };
 553
 554 static void cortex_a15_initfn(Object *obj)
 555 {
 556     ARMCPU *cpu = ARM_CPU(obj);
 557     set_feature(&cpu->env, ARM_FEATURE_V7);
 558     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 559     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 560     set_feature(&cpu->env, ARM_FEATURE_NEON);
 561     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 562     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 563     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 564     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 565     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 566     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 567     cpu->midr = 0x412fc0f1;
 568     cpu->reset_fpsid = 0x410430f0;
 569     cpu->mvfr0 = 0x10110222;
 570     cpu->mvfr1 = 0x11111111;
 571     cpu->ctr = 0x8444c004;
 572     cpu->reset_sctlr = 0x00c50078;
 573     cpu->id_pfr0 = 0x00001131;
 574     cpu->id_pfr1 = 0x00011011;
 575     cpu->id_dfr0 = 0x02010555;
 576     cpu->id_afr0 = 0x00000000;
 577     cpu->id_mmfr0 = 0x10201105;
 578     cpu->id_mmfr1 = 0x20000000;
 579     cpu->id_mmfr2 = 0x01240000;
 580     cpu->id_mmfr3 = 0x02102211;
 581     cpu->id_isar0 = 0x02101110;
 582     cpu->id_isar1 = 0x13112111;
 583     cpu->id_isar2 = 0x21232041;
 584     cpu->id_isar3 = 0x11112131;
 585     cpu->id_isar4 = 0x10011142;
 586     cpu->clidr = 0x0a200023;
 587     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 588     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 589     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 590     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 591 }
 592
 593 static void ti925t_initfn(Object *obj)
 594 {
 595     ARMCPU *cpu = ARM_CPU(obj);
 596     set_feature(&cpu->env, ARM_FEATURE_V4T);
 597     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 598     cpu->midr = ARM_CPUID_TI925T;
 599     cpu->ctr = 0x5109149;
 600     cpu->reset_sctlr = 0x00000070;
 601 }
 602
 603 static void sa1100_initfn(Object *obj)
 604 {
 605     ARMCPU *cpu = ARM_CPU(obj);
 606     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 607     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 608     cpu->midr = 0x4401A11B;
 609     cpu->reset_sctlr = 0x00000070;
 610 }
 611
 612 static void sa1110_initfn(Object *obj)
 613 {
 614     ARMCPU *cpu = ARM_CPU(obj);
 615     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 616     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 617     cpu->midr = 0x6901B119;
 618     cpu->reset_sctlr = 0x00000070;
 619 }
 620
 621 static void pxa250_initfn(Object *obj)
 622 {
 623     ARMCPU *cpu = ARM_CPU(obj);
 624     set_feature(&cpu->env, ARM_FEATURE_V5);
 625     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 626     cpu->midr = 0x69052100;
 627     cpu->ctr = 0xd172172;
 628     cpu->reset_sctlr = 0x00000078;
 629 }
 630
 631 static void pxa255_initfn(Object *obj)
 632 {
 633     ARMCPU *cpu = ARM_CPU(obj);
 634     set_feature(&cpu->env, ARM_FEATURE_V5);
 635     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 636     cpu->midr = 0x69052d00;
 637     cpu->ctr = 0xd172172;
 638     cpu->reset_sctlr = 0x00000078;
 639 }
 640
 641 static void pxa260_initfn(Object *obj)
 642 {
 643     ARMCPU *cpu = ARM_CPU(obj);
 644     set_feature(&cpu->env, ARM_FEATURE_V5);
 645     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 646     cpu->midr = 0x69052903;
 647     cpu->ctr = 0xd172172;
 648     cpu->reset_sctlr = 0x00000078;
 649 }
 650
 651 static void pxa261_initfn(Object *obj)
 652 {
 653     ARMCPU *cpu = ARM_CPU(obj);
 654     set_feature(&cpu->env, ARM_FEATURE_V5);
 655     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 656     cpu->midr = 0x69052d05;
 657     cpu->ctr = 0xd172172;
 658     cpu->reset_sctlr = 0x00000078;
 659 }
 660
 661 static void pxa262_initfn(Object *obj)
 662 {
 663     ARMCPU *cpu = ARM_CPU(obj);
 664     set_feature(&cpu->env, ARM_FEATURE_V5);
 665     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 666     cpu->midr = 0x69052d06;
 667     cpu->ctr = 0xd172172;
 668     cpu->reset_sctlr = 0x00000078;
 669 }
 670
 671 static void pxa270a0_initfn(Object *obj)
 672 {
 673     ARMCPU *cpu = ARM_CPU(obj);
 674     set_feature(&cpu->env, ARM_FEATURE_V5);
 675     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 676     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 677     cpu->midr = 0x69054110;
 678     cpu->ctr = 0xd172172;
 679     cpu->reset_sctlr = 0x00000078;
 680 }
 681
 682 static void pxa270a1_initfn(Object *obj)
 683 {
 684     ARMCPU *cpu = ARM_CPU(obj);
 685     set_feature(&cpu->env, ARM_FEATURE_V5);
 686     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 687     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 688     cpu->midr = 0x69054111;
 689     cpu->ctr = 0xd172172;
 690     cpu->reset_sctlr = 0x00000078;
 691 }
 692
 693 static void pxa270b0_initfn(Object *obj)
 694 {
 695     ARMCPU *cpu = ARM_CPU(obj);
 696     set_feature(&cpu->env, ARM_FEATURE_V5);
 697     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 698     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 699     cpu->midr = 0x69054112;
 700     cpu->ctr = 0xd172172;
 701     cpu->reset_sctlr = 0x00000078;
 702 }
 703
 704 static void pxa270b1_initfn(Object *obj)
 705 {
 706     ARMCPU *cpu = ARM_CPU(obj);
 707     set_feature(&cpu->env, ARM_FEATURE_V5);
 708     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 709     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 710     cpu->midr = 0x69054113;
 711     cpu->ctr = 0xd172172;
 712     cpu->reset_sctlr = 0x00000078;
 713 }
 714
 715 static void pxa270c0_initfn(Object *obj)
 716 {
 717     ARMCPU *cpu = ARM_CPU(obj);
 718     set_feature(&cpu->env, ARM_FEATURE_V5);
 719     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 720     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 721     cpu->midr = 0x69054114;
 722     cpu->ctr = 0xd172172;
 723     cpu->reset_sctlr = 0x00000078;
 724 }
 725
 726 static void pxa270c5_initfn(Object *obj)
 727 {
 728     ARMCPU *cpu = ARM_CPU(obj);
 729     set_feature(&cpu->env, ARM_FEATURE_V5);
 730     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 731     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 732     cpu->midr = 0x69054117;
 733     cpu->ctr = 0xd172172;
 734     cpu->reset_sctlr = 0x00000078;
 735 }
 736
 737 static void arm_any_initfn(Object *obj)
 738 {
 739     ARMCPU *cpu = ARM_CPU(obj);
 740     set_feature(&cpu->env, ARM_FEATURE_V7);
 741     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 742     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 743     set_feature(&cpu->env, ARM_FEATURE_NEON);
 744     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 745     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 746     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 747     cpu->midr = 0xffffffff;
 748 }
 749
 750 typedef struct ARMCPUInfo {
 751     const char *name;
 752     void (*initfn)(Object *obj);
 753 } ARMCPUInfo;
 754
 755 static const ARMCPUInfo arm_cpus[] = {
 756     { .name = "arm926",      .initfn = arm926_initfn },
 757     { .name = "arm946",      .initfn = arm946_initfn },
 758     { .name = "arm1026",     .initfn = arm1026_initfn },
 759     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 760      * older core than plain "arm1136". In particular this does not
 761      * have the v6K features.
 762      */
 763     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 764     { .name = "arm1136",     .initfn = arm1136_initfn },
 765     { .name = "arm1176",     .initfn = arm1176_initfn },
 766     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 767     { .name = "cortex-m3",   .initfn = cortex_m3_initfn },
 768     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 769     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 770     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 771     { .name = "ti925t",      .initfn = ti925t_initfn },
 772     { .name = "sa1100",      .initfn = sa1100_initfn },
 773     { .name = "sa1110",      .initfn = sa1110_initfn },
 774     { .name = "pxa250",      .initfn = pxa250_initfn },
 775     { .name = "pxa255",      .initfn = pxa255_initfn },
 776     { .name = "pxa260",      .initfn = pxa260_initfn },
 777     { .name = "pxa261",      .initfn = pxa261_initfn },
 778     { .name = "pxa262",      .initfn = pxa262_initfn },
 779     /* "pxa270" is an alias for "pxa270-a0" */
 780     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 781     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 782     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 783     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 784     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 785     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 786     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 787     { .name = "any",         .initfn = arm_any_initfn },
 788 };
 789
 790 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 791 {
 792     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 793     CPUClass *cc = CPU_CLASS(acc);
 794     DeviceClass *dc = DEVICE_CLASS(oc);
 795
 796     acc->parent_realize = dc->realize;
 797     dc->realize = arm_cpu_realizefn;
 798
 799     acc->parent_reset = cc->reset;
 800     cc->reset = arm_cpu_reset;
 801
 802     cc->class_by_name = arm_cpu_class_by_name;
 803 }
 804
 805 static void cpu_register(const ARMCPUInfo *info)
 806 {
 807     TypeInfo type_info = {
 808         .parent = TYPE_ARM_CPU,
 809         .instance_size = sizeof(ARMCPU),
 810         .instance_init = info->initfn,
 811         .class_size = sizeof(ARMCPUClass),
 812     };
 813
 814     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 815     type_register(&type_info);
 816     g_free((void *)type_info.name);
 817 }
 818
 819 static const TypeInfo arm_cpu_type_info = {
 820     .name = TYPE_ARM_CPU,
 821     .parent = TYPE_CPU,
 822     .instance_size = sizeof(ARMCPU),
 823     .instance_init = arm_cpu_initfn,
 824     .instance_finalize = arm_cpu_finalizefn,
 825     .abstract = true,
 826     .class_size = sizeof(ARMCPUClass),
 827     .class_init = arm_cpu_class_init,
 828 };
 829
 830 static void arm_cpu_register_types(void)
 831 {
 832     int i;
 833
 834     type_register_static(&arm_cpu_type_info);
 835     for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
 836         cpu_register(&arm_cpus[i]);
 837     }
 838 }
 839
 840 type_init(arm_cpu_register_types)