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[qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi/visitor.h"
34 #include "sysemu/arch_init.h"
35
36 #include "hyperv.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #ifndef CONFIG_USER_ONLY
45 #include "hw/xen.h"
46 #include "hw/sysbus.h"
47 #include "hw/apic_internal.h"
48 #endif
49
50 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
51 uint32_t vendor2, uint32_t vendor3)
52 {
53 int i;
54 for (i = 0; i < 4; i++) {
55 dst[i] = vendor1 >> (8 * i);
56 dst[i + 4] = vendor2 >> (8 * i);
57 dst[i + 8] = vendor3 >> (8 * i);
58 }
59 dst[CPUID_VENDOR_SZ] = '\0';
60 }
61
62 /* feature flags taken from "Intel Processor Identification and the CPUID
63 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
64 * between feature naming conventions, aliases may be added.
65 */
66 static const char *feature_name[] = {
67 "fpu", "vme", "de", "pse",
68 "tsc", "msr", "pae", "mce",
69 "cx8", "apic", NULL, "sep",
70 "mtrr", "pge", "mca", "cmov",
71 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
72 NULL, "ds" /* Intel dts */, "acpi", "mmx",
73 "fxsr", "sse", "sse2", "ss",
74 "ht" /* Intel htt */, "tm", "ia64", "pbe",
75 };
76 static const char *ext_feature_name[] = {
77 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
78 "ds_cpl", "vmx", "smx", "est",
79 "tm2", "ssse3", "cid", NULL,
80 "fma", "cx16", "xtpr", "pdcm",
81 NULL, "pcid", "dca", "sse4.1|sse4_1",
82 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
83 "tsc-deadline", "aes", "xsave", "osxsave",
84 "avx", "f16c", "rdrand", "hypervisor",
85 };
86 /* Feature names that are already defined on feature_name[] but are set on
87 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
88 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
89 * if and only if CPU vendor is AMD.
90 */
91 static const char *ext2_feature_name[] = {
92 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
93 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
94 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
95 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
96 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
97 "nx|xd", NULL, "mmxext", NULL /* mmx */,
98 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
99 NULL, "lm|i64", "3dnowext", "3dnow",
100 };
101 static const char *ext3_feature_name[] = {
102 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
103 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
104 "3dnowprefetch", "osvw", "ibs", "xop",
105 "skinit", "wdt", NULL, "lwp",
106 "fma4", "tce", NULL, "nodeid_msr",
107 NULL, "tbm", "topoext", "perfctr_core",
108 "perfctr_nb", NULL, NULL, NULL,
109 NULL, NULL, NULL, NULL,
110 };
111
112 static const char *ext4_feature_name[] = {
113 NULL, NULL, "xstore", "xstore-en",
114 NULL, NULL, "xcrypt", "xcrypt-en",
115 "ace2", "ace2-en", "phe", "phe-en",
116 "pmm", "pmm-en", NULL, NULL,
117 NULL, NULL, NULL, NULL,
118 NULL, NULL, NULL, NULL,
119 NULL, NULL, NULL, NULL,
120 NULL, NULL, NULL, NULL,
121 };
122
123 static const char *kvm_feature_name[] = {
124 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
125 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
126 NULL, NULL, NULL, NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129 NULL, NULL, NULL, NULL,
130 NULL, NULL, NULL, NULL,
131 NULL, NULL, NULL, NULL,
132 };
133
134 static const char *svm_feature_name[] = {
135 "npt", "lbrv", "svm_lock", "nrip_save",
136 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
137 NULL, NULL, "pause_filter", NULL,
138 "pfthreshold", NULL, NULL, NULL,
139 NULL, NULL, NULL, NULL,
140 NULL, NULL, NULL, NULL,
141 NULL, NULL, NULL, NULL,
142 NULL, NULL, NULL, NULL,
143 };
144
145 static const char *cpuid_7_0_ebx_feature_name[] = {
146 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
147 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
148 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
149 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
150 };
151
152 typedef struct FeatureWordInfo {
153 const char **feat_names;
154 uint32_t cpuid_eax; /* Input EAX for CPUID */
155 int cpuid_reg; /* R_* register constant */
156 } FeatureWordInfo;
157
158 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
159 [FEAT_1_EDX] = {
160 .feat_names = feature_name,
161 .cpuid_eax = 1, .cpuid_reg = R_EDX,
162 },
163 [FEAT_1_ECX] = {
164 .feat_names = ext_feature_name,
165 .cpuid_eax = 1, .cpuid_reg = R_ECX,
166 },
167 [FEAT_8000_0001_EDX] = {
168 .feat_names = ext2_feature_name,
169 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
170 },
171 [FEAT_8000_0001_ECX] = {
172 .feat_names = ext3_feature_name,
173 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
174 },
175 [FEAT_C000_0001_EDX] = {
176 .feat_names = ext4_feature_name,
177 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
178 },
179 [FEAT_KVM] = {
180 .feat_names = kvm_feature_name,
181 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
182 },
183 [FEAT_SVM] = {
184 .feat_names = svm_feature_name,
185 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
186 },
187 [FEAT_7_0_EBX] = {
188 .feat_names = cpuid_7_0_ebx_feature_name,
189 .cpuid_eax = 7, .cpuid_reg = R_EBX,
190 },
191 };
192
193 const char *get_register_name_32(unsigned int reg)
194 {
195 static const char *reg_names[CPU_NB_REGS32] = {
196 [R_EAX] = "EAX",
197 [R_ECX] = "ECX",
198 [R_EDX] = "EDX",
199 [R_EBX] = "EBX",
200 [R_ESP] = "ESP",
201 [R_EBP] = "EBP",
202 [R_ESI] = "ESI",
203 [R_EDI] = "EDI",
204 };
205
206 if (reg > CPU_NB_REGS32) {
207 return NULL;
208 }
209 return reg_names[reg];
210 }
211
212 /* collects per-function cpuid data
213 */
214 typedef struct model_features_t {
215 uint32_t *guest_feat;
216 uint32_t *host_feat;
217 FeatureWord feat_word;
218 } model_features_t;
219
220 int check_cpuid = 0;
221 int enforce_cpuid = 0;
222
223 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
224 (1 << KVM_FEATURE_NOP_IO_DELAY) |
225 (1 << KVM_FEATURE_CLOCKSOURCE2) |
226 (1 << KVM_FEATURE_ASYNC_PF) |
227 (1 << KVM_FEATURE_STEAL_TIME) |
228 (1 << KVM_FEATURE_PV_EOI) |
229 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
230
231 void disable_kvm_pv_eoi(void)
232 {
233 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
234 }
235
236 void host_cpuid(uint32_t function, uint32_t count,
237 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
238 {
239 #if defined(CONFIG_KVM)
240 uint32_t vec[4];
241
242 #ifdef __x86_64__
243 asm volatile("cpuid"
244 : "=a"(vec[0]), "=b"(vec[1]),
245 "=c"(vec[2]), "=d"(vec[3])
246 : "0"(function), "c"(count) : "cc");
247 #else
248 asm volatile("pusha \n\t"
249 "cpuid \n\t"
250 "mov %%eax, 0(%2) \n\t"
251 "mov %%ebx, 4(%2) \n\t"
252 "mov %%ecx, 8(%2) \n\t"
253 "mov %%edx, 12(%2) \n\t"
254 "popa"
255 : : "a"(function), "c"(count), "S"(vec)
256 : "memory", "cc");
257 #endif
258
259 if (eax)
260 *eax = vec[0];
261 if (ebx)
262 *ebx = vec[1];
263 if (ecx)
264 *ecx = vec[2];
265 if (edx)
266 *edx = vec[3];
267 #endif
268 }
269
270 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
271
272 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
273 * a substring. ex if !NULL points to the first char after a substring,
274 * otherwise the string is assumed to sized by a terminating nul.
275 * Return lexical ordering of *s1:*s2.
276 */
277 static int sstrcmp(const char *s1, const char *e1, const char *s2,
278 const char *e2)
279 {
280 for (;;) {
281 if (!*s1 || !*s2 || *s1 != *s2)
282 return (*s1 - *s2);
283 ++s1, ++s2;
284 if (s1 == e1 && s2 == e2)
285 return (0);
286 else if (s1 == e1)
287 return (*s2);
288 else if (s2 == e2)
289 return (*s1);
290 }
291 }
292
293 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
294 * '|' delimited (possibly empty) strings in which case search for a match
295 * within the alternatives proceeds left to right. Return 0 for success,
296 * non-zero otherwise.
297 */
298 static int altcmp(const char *s, const char *e, const char *altstr)
299 {
300 const char *p, *q;
301
302 for (q = p = altstr; ; ) {
303 while (*p && *p != '|')
304 ++p;
305 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
306 return (0);
307 if (!*p)
308 return (1);
309 else
310 q = ++p;
311 }
312 }
313
314 /* search featureset for flag *[s..e), if found set corresponding bit in
315 * *pval and return true, otherwise return false
316 */
317 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
318 const char **featureset)
319 {
320 uint32_t mask;
321 const char **ppc;
322 bool found = false;
323
324 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
325 if (*ppc && !altcmp(s, e, *ppc)) {
326 *pval |= mask;
327 found = true;
328 }
329 }
330 return found;
331 }
332
333 static void add_flagname_to_bitmaps(const char *flagname,
334 FeatureWordArray words)
335 {
336 FeatureWord w;
337 for (w = 0; w < FEATURE_WORDS; w++) {
338 FeatureWordInfo *wi = &feature_word_info[w];
339 if (wi->feat_names &&
340 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
341 break;
342 }
343 }
344 if (w == FEATURE_WORDS) {
345 fprintf(stderr, "CPU feature %s not found\n", flagname);
346 }
347 }
348
349 typedef struct x86_def_t {
350 const char *name;
351 uint32_t level;
352 /* vendor is zero-terminated, 12 character ASCII string */
353 char vendor[CPUID_VENDOR_SZ + 1];
354 int family;
355 int model;
356 int stepping;
357 uint32_t features, ext_features, ext2_features, ext3_features;
358 uint32_t kvm_features, svm_features;
359 uint32_t xlevel;
360 char model_id[48];
361 /* Store the results of Centaur's CPUID instructions */
362 uint32_t ext4_features;
363 uint32_t xlevel2;
364 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
365 uint32_t cpuid_7_0_ebx_features;
366 } x86_def_t;
367
368 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
369 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
370 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
371 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
372 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
373 CPUID_PSE36 | CPUID_FXSR)
374 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
375 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
376 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
377 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
378 CPUID_PAE | CPUID_SEP | CPUID_APIC)
379
380 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
381 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
382 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
383 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
384 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
385 /* partly implemented:
386 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
387 CPUID_PSE36 (needed for Solaris) */
388 /* missing:
389 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
390 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
391 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
392 CPUID_EXT_HYPERVISOR)
393 /* missing:
394 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
395 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
396 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
397 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
398 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
399 /* missing:
400 CPUID_EXT2_PDPE1GB */
401 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
402 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
403 #define TCG_SVM_FEATURES 0
404 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
405
406 /* built-in CPU model definitions
407 */
408 static x86_def_t builtin_x86_defs[] = {
409 {
410 .name = "qemu64",
411 .level = 4,
412 .vendor = CPUID_VENDOR_AMD,
413 .family = 6,
414 .model = 2,
415 .stepping = 3,
416 .features = PPRO_FEATURES |
417 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
418 CPUID_PSE36,
419 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
420 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
421 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
422 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
423 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
424 .xlevel = 0x8000000A,
425 },
426 {
427 .name = "phenom",
428 .level = 5,
429 .vendor = CPUID_VENDOR_AMD,
430 .family = 16,
431 .model = 2,
432 .stepping = 3,
433 .features = PPRO_FEATURES |
434 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
435 CPUID_PSE36 | CPUID_VME | CPUID_HT,
436 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
437 CPUID_EXT_POPCNT,
438 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
439 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
440 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
441 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
442 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
443 CPUID_EXT3_CR8LEG,
444 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
445 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
446 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
447 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
448 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
449 .xlevel = 0x8000001A,
450 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
451 },
452 {
453 .name = "core2duo",
454 .level = 10,
455 .vendor = CPUID_VENDOR_INTEL,
456 .family = 6,
457 .model = 15,
458 .stepping = 11,
459 .features = PPRO_FEATURES |
460 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
461 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
462 CPUID_HT | CPUID_TM | CPUID_PBE,
463 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
464 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
465 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
466 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
467 .ext3_features = CPUID_EXT3_LAHF_LM,
468 .xlevel = 0x80000008,
469 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
470 },
471 {
472 .name = "kvm64",
473 .level = 5,
474 .vendor = CPUID_VENDOR_INTEL,
475 .family = 15,
476 .model = 6,
477 .stepping = 1,
478 /* Missing: CPUID_VME, CPUID_HT */
479 .features = PPRO_FEATURES |
480 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
481 CPUID_PSE36,
482 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
483 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
484 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
485 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
486 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
487 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
488 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
489 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
490 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
491 .ext3_features = 0,
492 .xlevel = 0x80000008,
493 .model_id = "Common KVM processor"
494 },
495 {
496 .name = "qemu32",
497 .level = 4,
498 .vendor = CPUID_VENDOR_INTEL,
499 .family = 6,
500 .model = 3,
501 .stepping = 3,
502 .features = PPRO_FEATURES,
503 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
504 .xlevel = 0x80000004,
505 },
506 {
507 .name = "kvm32",
508 .level = 5,
509 .vendor = CPUID_VENDOR_INTEL,
510 .family = 15,
511 .model = 6,
512 .stepping = 1,
513 .features = PPRO_FEATURES |
514 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
515 .ext_features = CPUID_EXT_SSE3,
516 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
517 .ext3_features = 0,
518 .xlevel = 0x80000008,
519 .model_id = "Common 32-bit KVM processor"
520 },
521 {
522 .name = "coreduo",
523 .level = 10,
524 .vendor = CPUID_VENDOR_INTEL,
525 .family = 6,
526 .model = 14,
527 .stepping = 8,
528 .features = PPRO_FEATURES | CPUID_VME |
529 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
530 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
531 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
532 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
533 .ext2_features = CPUID_EXT2_NX,
534 .xlevel = 0x80000008,
535 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
536 },
537 {
538 .name = "486",
539 .level = 1,
540 .vendor = CPUID_VENDOR_INTEL,
541 .family = 4,
542 .model = 0,
543 .stepping = 0,
544 .features = I486_FEATURES,
545 .xlevel = 0,
546 },
547 {
548 .name = "pentium",
549 .level = 1,
550 .vendor = CPUID_VENDOR_INTEL,
551 .family = 5,
552 .model = 4,
553 .stepping = 3,
554 .features = PENTIUM_FEATURES,
555 .xlevel = 0,
556 },
557 {
558 .name = "pentium2",
559 .level = 2,
560 .vendor = CPUID_VENDOR_INTEL,
561 .family = 6,
562 .model = 5,
563 .stepping = 2,
564 .features = PENTIUM2_FEATURES,
565 .xlevel = 0,
566 },
567 {
568 .name = "pentium3",
569 .level = 2,
570 .vendor = CPUID_VENDOR_INTEL,
571 .family = 6,
572 .model = 7,
573 .stepping = 3,
574 .features = PENTIUM3_FEATURES,
575 .xlevel = 0,
576 },
577 {
578 .name = "athlon",
579 .level = 2,
580 .vendor = CPUID_VENDOR_AMD,
581 .family = 6,
582 .model = 2,
583 .stepping = 3,
584 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
585 CPUID_MCA,
586 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
587 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
588 .xlevel = 0x80000008,
589 },
590 {
591 .name = "n270",
592 /* original is on level 10 */
593 .level = 5,
594 .vendor = CPUID_VENDOR_INTEL,
595 .family = 6,
596 .model = 28,
597 .stepping = 2,
598 .features = PPRO_FEATURES |
599 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
600 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
601 /* Some CPUs got no CPUID_SEP */
602 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
603 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
604 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
605 CPUID_EXT2_NX,
606 .ext3_features = CPUID_EXT3_LAHF_LM,
607 .xlevel = 0x8000000A,
608 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
609 },
610 {
611 .name = "Conroe",
612 .level = 2,
613 .vendor = CPUID_VENDOR_INTEL,
614 .family = 6,
615 .model = 2,
616 .stepping = 3,
617 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
618 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
619 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
620 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
621 CPUID_DE | CPUID_FP87,
622 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
623 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
624 .ext3_features = CPUID_EXT3_LAHF_LM,
625 .xlevel = 0x8000000A,
626 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
627 },
628 {
629 .name = "Penryn",
630 .level = 2,
631 .vendor = CPUID_VENDOR_INTEL,
632 .family = 6,
633 .model = 2,
634 .stepping = 3,
635 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
636 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
637 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
638 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
639 CPUID_DE | CPUID_FP87,
640 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
641 CPUID_EXT_SSE3,
642 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
643 .ext3_features = CPUID_EXT3_LAHF_LM,
644 .xlevel = 0x8000000A,
645 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
646 },
647 {
648 .name = "Nehalem",
649 .level = 2,
650 .vendor = CPUID_VENDOR_INTEL,
651 .family = 6,
652 .model = 2,
653 .stepping = 3,
654 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
655 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
656 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
657 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
658 CPUID_DE | CPUID_FP87,
659 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
660 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
661 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
662 .ext3_features = CPUID_EXT3_LAHF_LM,
663 .xlevel = 0x8000000A,
664 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
665 },
666 {
667 .name = "Westmere",
668 .level = 11,
669 .vendor = CPUID_VENDOR_INTEL,
670 .family = 6,
671 .model = 44,
672 .stepping = 1,
673 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
674 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
675 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
676 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
677 CPUID_DE | CPUID_FP87,
678 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
679 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
680 CPUID_EXT_SSE3,
681 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
682 .ext3_features = CPUID_EXT3_LAHF_LM,
683 .xlevel = 0x8000000A,
684 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
685 },
686 {
687 .name = "SandyBridge",
688 .level = 0xd,
689 .vendor = CPUID_VENDOR_INTEL,
690 .family = 6,
691 .model = 42,
692 .stepping = 1,
693 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
694 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
695 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
696 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
697 CPUID_DE | CPUID_FP87,
698 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
699 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
700 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
701 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
702 CPUID_EXT_SSE3,
703 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
704 CPUID_EXT2_SYSCALL,
705 .ext3_features = CPUID_EXT3_LAHF_LM,
706 .xlevel = 0x8000000A,
707 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
708 },
709 {
710 .name = "Haswell",
711 .level = 0xd,
712 .vendor = CPUID_VENDOR_INTEL,
713 .family = 6,
714 .model = 60,
715 .stepping = 1,
716 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
717 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
718 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
719 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
720 CPUID_DE | CPUID_FP87,
721 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
722 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
723 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
724 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
725 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
726 CPUID_EXT_PCID,
727 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
728 CPUID_EXT2_SYSCALL,
729 .ext3_features = CPUID_EXT3_LAHF_LM,
730 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
731 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
732 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
733 CPUID_7_0_EBX_RTM,
734 .xlevel = 0x8000000A,
735 .model_id = "Intel Core Processor (Haswell)",
736 },
737 {
738 .name = "Opteron_G1",
739 .level = 5,
740 .vendor = CPUID_VENDOR_AMD,
741 .family = 15,
742 .model = 6,
743 .stepping = 1,
744 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
745 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
746 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
747 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
748 CPUID_DE | CPUID_FP87,
749 .ext_features = CPUID_EXT_SSE3,
750 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
751 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
752 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
753 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
754 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
755 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
756 .xlevel = 0x80000008,
757 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
758 },
759 {
760 .name = "Opteron_G2",
761 .level = 5,
762 .vendor = CPUID_VENDOR_AMD,
763 .family = 15,
764 .model = 6,
765 .stepping = 1,
766 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
767 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
768 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
769 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
770 CPUID_DE | CPUID_FP87,
771 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
772 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
773 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
774 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
775 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
776 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
777 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
778 CPUID_EXT2_DE | CPUID_EXT2_FPU,
779 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
780 .xlevel = 0x80000008,
781 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
782 },
783 {
784 .name = "Opteron_G3",
785 .level = 5,
786 .vendor = CPUID_VENDOR_AMD,
787 .family = 15,
788 .model = 6,
789 .stepping = 1,
790 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
791 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
792 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
793 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
794 CPUID_DE | CPUID_FP87,
795 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
796 CPUID_EXT_SSE3,
797 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
798 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
799 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
800 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
801 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
802 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
803 CPUID_EXT2_DE | CPUID_EXT2_FPU,
804 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
805 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
806 .xlevel = 0x80000008,
807 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
808 },
809 {
810 .name = "Opteron_G4",
811 .level = 0xd,
812 .vendor = CPUID_VENDOR_AMD,
813 .family = 21,
814 .model = 1,
815 .stepping = 2,
816 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
817 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
818 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
819 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
820 CPUID_DE | CPUID_FP87,
821 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
822 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
823 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
824 CPUID_EXT_SSE3,
825 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
826 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
827 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
828 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
829 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
830 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
831 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
832 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
833 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
834 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
835 CPUID_EXT3_LAHF_LM,
836 .xlevel = 0x8000001A,
837 .model_id = "AMD Opteron 62xx class CPU",
838 },
839 {
840 .name = "Opteron_G5",
841 .level = 0xd,
842 .vendor = CPUID_VENDOR_AMD,
843 .family = 21,
844 .model = 2,
845 .stepping = 0,
846 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
847 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
848 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
849 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
850 CPUID_DE | CPUID_FP87,
851 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
852 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
853 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
854 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
855 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
856 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
857 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
858 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
859 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
860 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
861 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
862 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
863 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
864 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
865 CPUID_EXT3_LAHF_LM,
866 .xlevel = 0x8000001A,
867 .model_id = "AMD Opteron 63xx class CPU",
868 },
869 };
870
871 #ifdef CONFIG_KVM
872 static int cpu_x86_fill_model_id(char *str)
873 {
874 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
875 int i;
876
877 for (i = 0; i < 3; i++) {
878 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
879 memcpy(str + i * 16 + 0, &eax, 4);
880 memcpy(str + i * 16 + 4, &ebx, 4);
881 memcpy(str + i * 16 + 8, &ecx, 4);
882 memcpy(str + i * 16 + 12, &edx, 4);
883 }
884 return 0;
885 }
886 #endif
887
888 /* Fill a x86_def_t struct with information about the host CPU, and
889 * the CPU features supported by the host hardware + host kernel
890 *
891 * This function may be called only if KVM is enabled.
892 */
893 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
894 {
895 #ifdef CONFIG_KVM
896 KVMState *s = kvm_state;
897 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
898
899 assert(kvm_enabled());
900
901 x86_cpu_def->name = "host";
902 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
903 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
904
905 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
906 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
907 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
908 x86_cpu_def->stepping = eax & 0x0F;
909
910 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
911 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
912 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
913
914 if (x86_cpu_def->level >= 7) {
915 x86_cpu_def->cpuid_7_0_ebx_features =
916 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
917 } else {
918 x86_cpu_def->cpuid_7_0_ebx_features = 0;
919 }
920
921 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
922 x86_cpu_def->ext2_features =
923 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
924 x86_cpu_def->ext3_features =
925 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
926
927 cpu_x86_fill_model_id(x86_cpu_def->model_id);
928
929 /* Call Centaur's CPUID instruction. */
930 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
931 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
932 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
933 if (eax >= 0xC0000001) {
934 /* Support VIA max extended level */
935 x86_cpu_def->xlevel2 = eax;
936 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
937 x86_cpu_def->ext4_features =
938 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
939 }
940 }
941
942 /* Other KVM-specific feature fields: */
943 x86_cpu_def->svm_features =
944 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
945 x86_cpu_def->kvm_features =
946 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
947
948 #endif /* CONFIG_KVM */
949 }
950
951 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
952 {
953 int i;
954
955 for (i = 0; i < 32; ++i)
956 if (1 << i & mask) {
957 const char *reg = get_register_name_32(f->cpuid_reg);
958 assert(reg);
959 fprintf(stderr, "warning: host doesn't support requested feature: "
960 "CPUID.%02XH:%s%s%s [bit %d]\n",
961 f->cpuid_eax, reg,
962 f->feat_names[i] ? "." : "",
963 f->feat_names[i] ? f->feat_names[i] : "", i);
964 break;
965 }
966 return 0;
967 }
968
969 /* Check if all requested cpu flags are making their way to the guest
970 *
971 * Returns 0 if all flags are supported by the host, non-zero otherwise.
972 *
973 * This function may be called only if KVM is enabled.
974 */
975 static int kvm_check_features_against_host(X86CPU *cpu)
976 {
977 CPUX86State *env = &cpu->env;
978 x86_def_t host_def;
979 uint32_t mask;
980 int rv, i;
981 struct model_features_t ft[] = {
982 {&env->cpuid_features, &host_def.features,
983 FEAT_1_EDX },
984 {&env->cpuid_ext_features, &host_def.ext_features,
985 FEAT_1_ECX },
986 {&env->cpuid_ext2_features, &host_def.ext2_features,
987 FEAT_8000_0001_EDX },
988 {&env->cpuid_ext3_features, &host_def.ext3_features,
989 FEAT_8000_0001_ECX },
990 {&env->cpuid_ext4_features, &host_def.ext4_features,
991 FEAT_C000_0001_EDX },
992 {&env->cpuid_7_0_ebx_features, &host_def.cpuid_7_0_ebx_features,
993 FEAT_7_0_EBX },
994 {&env->cpuid_svm_features, &host_def.svm_features,
995 FEAT_SVM },
996 {&env->cpuid_kvm_features, &host_def.kvm_features,
997 FEAT_KVM },
998 };
999
1000 assert(kvm_enabled());
1001
1002 kvm_cpu_fill_host(&host_def);
1003 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1004 FeatureWord w = ft[i].feat_word;
1005 FeatureWordInfo *wi = &feature_word_info[w];
1006 for (mask = 1; mask; mask <<= 1) {
1007 if (*ft[i].guest_feat & mask &&
1008 !(*ft[i].host_feat & mask)) {
1009 unavailable_host_feature(wi, mask);
1010 rv = 1;
1011 }
1012 }
1013 }
1014 return rv;
1015 }
1016
1017 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1018 const char *name, Error **errp)
1019 {
1020 X86CPU *cpu = X86_CPU(obj);
1021 CPUX86State *env = &cpu->env;
1022 int64_t value;
1023
1024 value = (env->cpuid_version >> 8) & 0xf;
1025 if (value == 0xf) {
1026 value += (env->cpuid_version >> 20) & 0xff;
1027 }
1028 visit_type_int(v, &value, name, errp);
1029 }
1030
1031 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1032 const char *name, Error **errp)
1033 {
1034 X86CPU *cpu = X86_CPU(obj);
1035 CPUX86State *env = &cpu->env;
1036 const int64_t min = 0;
1037 const int64_t max = 0xff + 0xf;
1038 int64_t value;
1039
1040 visit_type_int(v, &value, name, errp);
1041 if (error_is_set(errp)) {
1042 return;
1043 }
1044 if (value < min || value > max) {
1045 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1046 name ? name : "null", value, min, max);
1047 return;
1048 }
1049
1050 env->cpuid_version &= ~0xff00f00;
1051 if (value > 0x0f) {
1052 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1053 } else {
1054 env->cpuid_version |= value << 8;
1055 }
1056 }
1057
1058 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1059 const char *name, Error **errp)
1060 {
1061 X86CPU *cpu = X86_CPU(obj);
1062 CPUX86State *env = &cpu->env;
1063 int64_t value;
1064
1065 value = (env->cpuid_version >> 4) & 0xf;
1066 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1067 visit_type_int(v, &value, name, errp);
1068 }
1069
1070 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1071 const char *name, Error **errp)
1072 {
1073 X86CPU *cpu = X86_CPU(obj);
1074 CPUX86State *env = &cpu->env;
1075 const int64_t min = 0;
1076 const int64_t max = 0xff;
1077 int64_t value;
1078
1079 visit_type_int(v, &value, name, errp);
1080 if (error_is_set(errp)) {
1081 return;
1082 }
1083 if (value < min || value > max) {
1084 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1085 name ? name : "null", value, min, max);
1086 return;
1087 }
1088
1089 env->cpuid_version &= ~0xf00f0;
1090 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1091 }
1092
1093 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1094 void *opaque, const char *name,
1095 Error **errp)
1096 {
1097 X86CPU *cpu = X86_CPU(obj);
1098 CPUX86State *env = &cpu->env;
1099 int64_t value;
1100
1101 value = env->cpuid_version & 0xf;
1102 visit_type_int(v, &value, name, errp);
1103 }
1104
1105 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1106 void *opaque, const char *name,
1107 Error **errp)
1108 {
1109 X86CPU *cpu = X86_CPU(obj);
1110 CPUX86State *env = &cpu->env;
1111 const int64_t min = 0;
1112 const int64_t max = 0xf;
1113 int64_t value;
1114
1115 visit_type_int(v, &value, name, errp);
1116 if (error_is_set(errp)) {
1117 return;
1118 }
1119 if (value < min || value > max) {
1120 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1121 name ? name : "null", value, min, max);
1122 return;
1123 }
1124
1125 env->cpuid_version &= ~0xf;
1126 env->cpuid_version |= value & 0xf;
1127 }
1128
1129 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1130 const char *name, Error **errp)
1131 {
1132 X86CPU *cpu = X86_CPU(obj);
1133
1134 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1135 }
1136
1137 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1138 const char *name, Error **errp)
1139 {
1140 X86CPU *cpu = X86_CPU(obj);
1141
1142 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1143 }
1144
1145 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1146 const char *name, Error **errp)
1147 {
1148 X86CPU *cpu = X86_CPU(obj);
1149
1150 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1151 }
1152
1153 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1154 const char *name, Error **errp)
1155 {
1156 X86CPU *cpu = X86_CPU(obj);
1157
1158 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1159 }
1160
1161 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1162 {
1163 X86CPU *cpu = X86_CPU(obj);
1164 CPUX86State *env = &cpu->env;
1165 char *value;
1166
1167 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1168 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1169 env->cpuid_vendor3);
1170 return value;
1171 }
1172
1173 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1174 Error **errp)
1175 {
1176 X86CPU *cpu = X86_CPU(obj);
1177 CPUX86State *env = &cpu->env;
1178 int i;
1179
1180 if (strlen(value) != CPUID_VENDOR_SZ) {
1181 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1182 "vendor", value);
1183 return;
1184 }
1185
1186 env->cpuid_vendor1 = 0;
1187 env->cpuid_vendor2 = 0;
1188 env->cpuid_vendor3 = 0;
1189 for (i = 0; i < 4; i++) {
1190 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1191 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1192 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1193 }
1194 }
1195
1196 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1197 {
1198 X86CPU *cpu = X86_CPU(obj);
1199 CPUX86State *env = &cpu->env;
1200 char *value;
1201 int i;
1202
1203 value = g_malloc(48 + 1);
1204 for (i = 0; i < 48; i++) {
1205 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1206 }
1207 value[48] = '\0';
1208 return value;
1209 }
1210
1211 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1212 Error **errp)
1213 {
1214 X86CPU *cpu = X86_CPU(obj);
1215 CPUX86State *env = &cpu->env;
1216 int c, len, i;
1217
1218 if (model_id == NULL) {
1219 model_id = "";
1220 }
1221 len = strlen(model_id);
1222 memset(env->cpuid_model, 0, 48);
1223 for (i = 0; i < 48; i++) {
1224 if (i >= len) {
1225 c = '\0';
1226 } else {
1227 c = (uint8_t)model_id[i];
1228 }
1229 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1230 }
1231 }
1232
1233 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1234 const char *name, Error **errp)
1235 {
1236 X86CPU *cpu = X86_CPU(obj);
1237 int64_t value;
1238
1239 value = cpu->env.tsc_khz * 1000;
1240 visit_type_int(v, &value, name, errp);
1241 }
1242
1243 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1244 const char *name, Error **errp)
1245 {
1246 X86CPU *cpu = X86_CPU(obj);
1247 const int64_t min = 0;
1248 const int64_t max = INT64_MAX;
1249 int64_t value;
1250
1251 visit_type_int(v, &value, name, errp);
1252 if (error_is_set(errp)) {
1253 return;
1254 }
1255 if (value < min || value > max) {
1256 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1257 name ? name : "null", value, min, max);
1258 return;
1259 }
1260
1261 cpu->env.tsc_khz = value / 1000;
1262 }
1263
1264 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1265 {
1266 x86_def_t *def;
1267 int i;
1268
1269 if (name == NULL) {
1270 return -1;
1271 }
1272 if (kvm_enabled() && strcmp(name, "host") == 0) {
1273 kvm_cpu_fill_host(x86_cpu_def);
1274 return 0;
1275 }
1276
1277 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1278 def = &builtin_x86_defs[i];
1279 if (strcmp(name, def->name) == 0) {
1280 memcpy(x86_cpu_def, def, sizeof(*def));
1281 /* sysenter isn't supported in compatibility mode on AMD,
1282 * syscall isn't supported in compatibility mode on Intel.
1283 * Normally we advertise the actual CPU vendor, but you can
1284 * override this using the 'vendor' property if you want to use
1285 * KVM's sysenter/syscall emulation in compatibility mode and
1286 * when doing cross vendor migration
1287 */
1288 if (kvm_enabled()) {
1289 uint32_t ebx = 0, ecx = 0, edx = 0;
1290 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1291 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1292 }
1293 return 0;
1294 }
1295 }
1296
1297 return -1;
1298 }
1299
1300 /* Parse "+feature,-feature,feature=foo" CPU feature string
1301 */
1302 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1303 {
1304 char *featurestr; /* Single 'key=value" string being parsed */
1305 /* Features to be added */
1306 FeatureWordArray plus_features = { 0 };
1307 /* Features to be removed */
1308 FeatureWordArray minus_features = { 0 };
1309 uint32_t numvalue;
1310 CPUX86State *env = &cpu->env;
1311
1312 featurestr = features ? strtok(features, ",") : NULL;
1313
1314 while (featurestr) {
1315 char *val;
1316 if (featurestr[0] == '+') {
1317 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1318 } else if (featurestr[0] == '-') {
1319 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1320 } else if ((val = strchr(featurestr, '='))) {
1321 *val = 0; val++;
1322 if (!strcmp(featurestr, "family")) {
1323 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1324 } else if (!strcmp(featurestr, "model")) {
1325 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1326 } else if (!strcmp(featurestr, "stepping")) {
1327 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1328 } else if (!strcmp(featurestr, "level")) {
1329 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1330 } else if (!strcmp(featurestr, "xlevel")) {
1331 char *err;
1332 char num[32];
1333
1334 numvalue = strtoul(val, &err, 0);
1335 if (!*val || *err) {
1336 error_setg(errp, "bad numerical value %s", val);
1337 goto out;
1338 }
1339 if (numvalue < 0x80000000) {
1340 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1341 ", fixup will be removed in future versions\n");
1342 numvalue += 0x80000000;
1343 }
1344 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1345 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1346 } else if (!strcmp(featurestr, "vendor")) {
1347 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1348 } else if (!strcmp(featurestr, "model_id")) {
1349 object_property_parse(OBJECT(cpu), val, "model-id", errp);
1350 } else if (!strcmp(featurestr, "tsc_freq")) {
1351 int64_t tsc_freq;
1352 char *err;
1353 char num[32];
1354
1355 tsc_freq = strtosz_suffix_unit(val, &err,
1356 STRTOSZ_DEFSUFFIX_B, 1000);
1357 if (tsc_freq < 0 || *err) {
1358 error_setg(errp, "bad numerical value %s", val);
1359 goto out;
1360 }
1361 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1362 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1363 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1364 char *err;
1365 numvalue = strtoul(val, &err, 0);
1366 if (!*val || *err) {
1367 error_setg(errp, "bad numerical value %s", val);
1368 goto out;
1369 }
1370 hyperv_set_spinlock_retries(numvalue);
1371 } else {
1372 error_setg(errp, "unrecognized feature %s", featurestr);
1373 goto out;
1374 }
1375 } else if (!strcmp(featurestr, "check")) {
1376 check_cpuid = 1;
1377 } else if (!strcmp(featurestr, "enforce")) {
1378 check_cpuid = enforce_cpuid = 1;
1379 } else if (!strcmp(featurestr, "hv_relaxed")) {
1380 hyperv_enable_relaxed_timing(true);
1381 } else if (!strcmp(featurestr, "hv_vapic")) {
1382 hyperv_enable_vapic_recommended(true);
1383 } else {
1384 error_setg(errp, "feature string `%s' not in format (+feature|"
1385 "-feature|feature=xyz)", featurestr);
1386 goto out;
1387 }
1388 if (error_is_set(errp)) {
1389 goto out;
1390 }
1391 featurestr = strtok(NULL, ",");
1392 }
1393 env->cpuid_features |= plus_features[FEAT_1_EDX];
1394 env->cpuid_ext_features |= plus_features[FEAT_1_ECX];
1395 env->cpuid_ext2_features |= plus_features[FEAT_8000_0001_EDX];
1396 env->cpuid_ext3_features |= plus_features[FEAT_8000_0001_ECX];
1397 env->cpuid_ext4_features |= plus_features[FEAT_C000_0001_EDX];
1398 env->cpuid_kvm_features |= plus_features[FEAT_KVM];
1399 env->cpuid_svm_features |= plus_features[FEAT_SVM];
1400 env->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1401 env->cpuid_features &= ~minus_features[FEAT_1_EDX];
1402 env->cpuid_ext_features &= ~minus_features[FEAT_1_ECX];
1403 env->cpuid_ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1404 env->cpuid_ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
1405 env->cpuid_ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
1406 env->cpuid_kvm_features &= ~minus_features[FEAT_KVM];
1407 env->cpuid_svm_features &= ~minus_features[FEAT_SVM];
1408 env->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
1409
1410 out:
1411 return;
1412 }
1413
1414 /* generate a composite string into buf of all cpuid names in featureset
1415 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1416 * if flags, suppress names undefined in featureset.
1417 */
1418 static void listflags(char *buf, int bufsize, uint32_t fbits,
1419 const char **featureset, uint32_t flags)
1420 {
1421 const char **p = &featureset[31];
1422 char *q, *b, bit;
1423 int nc;
1424
1425 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1426 *buf = '\0';
1427 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1428 if (fbits & 1 << bit && (*p || !flags)) {
1429 if (*p)
1430 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1431 else
1432 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1433 if (bufsize <= nc) {
1434 if (b) {
1435 memcpy(b, "...", sizeof("..."));
1436 }
1437 return;
1438 }
1439 q += nc;
1440 bufsize -= nc;
1441 }
1442 }
1443
1444 /* generate CPU information. */
1445 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1446 {
1447 x86_def_t *def;
1448 char buf[256];
1449 int i;
1450
1451 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1452 def = &builtin_x86_defs[i];
1453 snprintf(buf, sizeof(buf), "%s", def->name);
1454 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1455 }
1456 if (kvm_enabled()) {
1457 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1458 }
1459 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1460 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1461 (*cpu_fprintf)(f, " %s\n", buf);
1462 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1463 (*cpu_fprintf)(f, " %s\n", buf);
1464 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1465 (*cpu_fprintf)(f, " %s\n", buf);
1466 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1467 (*cpu_fprintf)(f, " %s\n", buf);
1468 }
1469
1470 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1471 {
1472 CpuDefinitionInfoList *cpu_list = NULL;
1473 x86_def_t *def;
1474 int i;
1475
1476 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1477 CpuDefinitionInfoList *entry;
1478 CpuDefinitionInfo *info;
1479
1480 def = &builtin_x86_defs[i];
1481 info = g_malloc0(sizeof(*info));
1482 info->name = g_strdup(def->name);
1483
1484 entry = g_malloc0(sizeof(*entry));
1485 entry->value = info;
1486 entry->next = cpu_list;
1487 cpu_list = entry;
1488 }
1489
1490 return cpu_list;
1491 }
1492
1493 #ifdef CONFIG_KVM
1494 static void filter_features_for_kvm(X86CPU *cpu)
1495 {
1496 CPUX86State *env = &cpu->env;
1497 KVMState *s = kvm_state;
1498
1499 env->cpuid_features &=
1500 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1501 env->cpuid_ext_features &=
1502 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1503 env->cpuid_ext2_features &=
1504 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1505 env->cpuid_ext3_features &=
1506 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1507 env->cpuid_svm_features &=
1508 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1509 env->cpuid_7_0_ebx_features &=
1510 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1511 env->cpuid_kvm_features &=
1512 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1513 env->cpuid_ext4_features &=
1514 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1515
1516 }
1517 #endif
1518
1519 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1520 {
1521 CPUX86State *env = &cpu->env;
1522 x86_def_t def1, *def = &def1;
1523 Error *error = NULL;
1524 char *name, *features;
1525 gchar **model_pieces;
1526
1527 memset(def, 0, sizeof(*def));
1528
1529 model_pieces = g_strsplit(cpu_model, ",", 2);
1530 if (!model_pieces[0]) {
1531 error_setg(&error, "Invalid/empty CPU model name");
1532 goto out;
1533 }
1534 name = model_pieces[0];
1535 features = model_pieces[1];
1536
1537 if (cpu_x86_find_by_name(def, name) < 0) {
1538 error_setg(&error, "Unable to find CPU definition: %s", name);
1539 goto out;
1540 }
1541
1542 if (kvm_enabled()) {
1543 def->kvm_features |= kvm_default_features;
1544 }
1545 def->ext_features |= CPUID_EXT_HYPERVISOR;
1546
1547 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", &error);
1548 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1549 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1550 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1551 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1552 env->cpuid_features = def->features;
1553 env->cpuid_ext_features = def->ext_features;
1554 env->cpuid_ext2_features = def->ext2_features;
1555 env->cpuid_ext3_features = def->ext3_features;
1556 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1557 env->cpuid_kvm_features = def->kvm_features;
1558 env->cpuid_svm_features = def->svm_features;
1559 env->cpuid_ext4_features = def->ext4_features;
1560 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1561 env->cpuid_xlevel2 = def->xlevel2;
1562
1563 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1564 if (error) {
1565 goto out;
1566 }
1567
1568 cpu_x86_parse_featurestr(cpu, features, &error);
1569 out:
1570 g_strfreev(model_pieces);
1571 if (error) {
1572 fprintf(stderr, "%s\n", error_get_pretty(error));
1573 error_free(error);
1574 return -1;
1575 }
1576 return 0;
1577 }
1578
1579 #if !defined(CONFIG_USER_ONLY)
1580
1581 void cpu_clear_apic_feature(CPUX86State *env)
1582 {
1583 env->cpuid_features &= ~CPUID_APIC;
1584 }
1585
1586 #endif /* !CONFIG_USER_ONLY */
1587
1588 /* Initialize list of CPU models, filling some non-static fields if necessary
1589 */
1590 void x86_cpudef_setup(void)
1591 {
1592 int i, j;
1593 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1594
1595 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1596 x86_def_t *def = &builtin_x86_defs[i];
1597
1598 /* Look for specific "cpudef" models that */
1599 /* have the QEMU version in .model_id */
1600 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1601 if (strcmp(model_with_versions[j], def->name) == 0) {
1602 pstrcpy(def->model_id, sizeof(def->model_id),
1603 "QEMU Virtual CPU version ");
1604 pstrcat(def->model_id, sizeof(def->model_id),
1605 qemu_get_version());
1606 break;
1607 }
1608 }
1609 }
1610 }
1611
1612 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1613 uint32_t *ecx, uint32_t *edx)
1614 {
1615 *ebx = env->cpuid_vendor1;
1616 *edx = env->cpuid_vendor2;
1617 *ecx = env->cpuid_vendor3;
1618 }
1619
1620 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1621 uint32_t *eax, uint32_t *ebx,
1622 uint32_t *ecx, uint32_t *edx)
1623 {
1624 X86CPU *cpu = x86_env_get_cpu(env);
1625 CPUState *cs = CPU(cpu);
1626
1627 /* test if maximum index reached */
1628 if (index & 0x80000000) {
1629 if (index > env->cpuid_xlevel) {
1630 if (env->cpuid_xlevel2 > 0) {
1631 /* Handle the Centaur's CPUID instruction. */
1632 if (index > env->cpuid_xlevel2) {
1633 index = env->cpuid_xlevel2;
1634 } else if (index < 0xC0000000) {
1635 index = env->cpuid_xlevel;
1636 }
1637 } else {
1638 /* Intel documentation states that invalid EAX input will
1639 * return the same information as EAX=cpuid_level
1640 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1641 */
1642 index = env->cpuid_level;
1643 }
1644 }
1645 } else {
1646 if (index > env->cpuid_level)
1647 index = env->cpuid_level;
1648 }
1649
1650 switch(index) {
1651 case 0:
1652 *eax = env->cpuid_level;
1653 get_cpuid_vendor(env, ebx, ecx, edx);
1654 break;
1655 case 1:
1656 *eax = env->cpuid_version;
1657 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1658 *ecx = env->cpuid_ext_features;
1659 *edx = env->cpuid_features;
1660 if (cs->nr_cores * cs->nr_threads > 1) {
1661 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1662 *edx |= 1 << 28; /* HTT bit */
1663 }
1664 break;
1665 case 2:
1666 /* cache info: needed for Pentium Pro compatibility */
1667 *eax = 1;
1668 *ebx = 0;
1669 *ecx = 0;
1670 *edx = 0x2c307d;
1671 break;
1672 case 4:
1673 /* cache info: needed for Core compatibility */
1674 if (cs->nr_cores > 1) {
1675 *eax = (cs->nr_cores - 1) << 26;
1676 } else {
1677 *eax = 0;
1678 }
1679 switch (count) {
1680 case 0: /* L1 dcache info */
1681 *eax |= 0x0000121;
1682 *ebx = 0x1c0003f;
1683 *ecx = 0x000003f;
1684 *edx = 0x0000001;
1685 break;
1686 case 1: /* L1 icache info */
1687 *eax |= 0x0000122;
1688 *ebx = 0x1c0003f;
1689 *ecx = 0x000003f;
1690 *edx = 0x0000001;
1691 break;
1692 case 2: /* L2 cache info */
1693 *eax |= 0x0000143;
1694 if (cs->nr_threads > 1) {
1695 *eax |= (cs->nr_threads - 1) << 14;
1696 }
1697 *ebx = 0x3c0003f;
1698 *ecx = 0x0000fff;
1699 *edx = 0x0000001;
1700 break;
1701 default: /* end of info */
1702 *eax = 0;
1703 *ebx = 0;
1704 *ecx = 0;
1705 *edx = 0;
1706 break;
1707 }
1708 break;
1709 case 5:
1710 /* mwait info: needed for Core compatibility */
1711 *eax = 0; /* Smallest monitor-line size in bytes */
1712 *ebx = 0; /* Largest monitor-line size in bytes */
1713 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1714 *edx = 0;
1715 break;
1716 case 6:
1717 /* Thermal and Power Leaf */
1718 *eax = 0;
1719 *ebx = 0;
1720 *ecx = 0;
1721 *edx = 0;
1722 break;
1723 case 7:
1724 /* Structured Extended Feature Flags Enumeration Leaf */
1725 if (count == 0) {
1726 *eax = 0; /* Maximum ECX value for sub-leaves */
1727 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1728 *ecx = 0; /* Reserved */
1729 *edx = 0; /* Reserved */
1730 } else {
1731 *eax = 0;
1732 *ebx = 0;
1733 *ecx = 0;
1734 *edx = 0;
1735 }
1736 break;
1737 case 9:
1738 /* Direct Cache Access Information Leaf */
1739 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1740 *ebx = 0;
1741 *ecx = 0;
1742 *edx = 0;
1743 break;
1744 case 0xA:
1745 /* Architectural Performance Monitoring Leaf */
1746 if (kvm_enabled()) {
1747 KVMState *s = cs->kvm_state;
1748
1749 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1750 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1751 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1752 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1753 } else {
1754 *eax = 0;
1755 *ebx = 0;
1756 *ecx = 0;
1757 *edx = 0;
1758 }
1759 break;
1760 case 0xD:
1761 /* Processor Extended State */
1762 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1763 *eax = 0;
1764 *ebx = 0;
1765 *ecx = 0;
1766 *edx = 0;
1767 break;
1768 }
1769 if (kvm_enabled()) {
1770 KVMState *s = cs->kvm_state;
1771
1772 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1773 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1774 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1775 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1776 } else {
1777 *eax = 0;
1778 *ebx = 0;
1779 *ecx = 0;
1780 *edx = 0;
1781 }
1782 break;
1783 case 0x80000000:
1784 *eax = env->cpuid_xlevel;
1785 *ebx = env->cpuid_vendor1;
1786 *edx = env->cpuid_vendor2;
1787 *ecx = env->cpuid_vendor3;
1788 break;
1789 case 0x80000001:
1790 *eax = env->cpuid_version;
1791 *ebx = 0;
1792 *ecx = env->cpuid_ext3_features;
1793 *edx = env->cpuid_ext2_features;
1794
1795 /* The Linux kernel checks for the CMPLegacy bit and
1796 * discards multiple thread information if it is set.
1797 * So dont set it here for Intel to make Linux guests happy.
1798 */
1799 if (cs->nr_cores * cs->nr_threads > 1) {
1800 uint32_t tebx, tecx, tedx;
1801 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1802 if (tebx != CPUID_VENDOR_INTEL_1 ||
1803 tedx != CPUID_VENDOR_INTEL_2 ||
1804 tecx != CPUID_VENDOR_INTEL_3) {
1805 *ecx |= 1 << 1; /* CmpLegacy bit */
1806 }
1807 }
1808 break;
1809 case 0x80000002:
1810 case 0x80000003:
1811 case 0x80000004:
1812 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1813 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1814 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1815 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1816 break;
1817 case 0x80000005:
1818 /* cache info (L1 cache) */
1819 *eax = 0x01ff01ff;
1820 *ebx = 0x01ff01ff;
1821 *ecx = 0x40020140;
1822 *edx = 0x40020140;
1823 break;
1824 case 0x80000006:
1825 /* cache info (L2 cache) */
1826 *eax = 0;
1827 *ebx = 0x42004200;
1828 *ecx = 0x02008140;
1829 *edx = 0;
1830 break;
1831 case 0x80000008:
1832 /* virtual & phys address size in low 2 bytes. */
1833 /* XXX: This value must match the one used in the MMU code. */
1834 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1835 /* 64 bit processor */
1836 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1837 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1838 } else {
1839 if (env->cpuid_features & CPUID_PSE36)
1840 *eax = 0x00000024; /* 36 bits physical */
1841 else
1842 *eax = 0x00000020; /* 32 bits physical */
1843 }
1844 *ebx = 0;
1845 *ecx = 0;
1846 *edx = 0;
1847 if (cs->nr_cores * cs->nr_threads > 1) {
1848 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
1849 }
1850 break;
1851 case 0x8000000A:
1852 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1853 *eax = 0x00000001; /* SVM Revision */
1854 *ebx = 0x00000010; /* nr of ASIDs */
1855 *ecx = 0;
1856 *edx = env->cpuid_svm_features; /* optional features */
1857 } else {
1858 *eax = 0;
1859 *ebx = 0;
1860 *ecx = 0;
1861 *edx = 0;
1862 }
1863 break;
1864 case 0xC0000000:
1865 *eax = env->cpuid_xlevel2;
1866 *ebx = 0;
1867 *ecx = 0;
1868 *edx = 0;
1869 break;
1870 case 0xC0000001:
1871 /* Support for VIA CPU's CPUID instruction */
1872 *eax = env->cpuid_version;
1873 *ebx = 0;
1874 *ecx = 0;
1875 *edx = env->cpuid_ext4_features;
1876 break;
1877 case 0xC0000002:
1878 case 0xC0000003:
1879 case 0xC0000004:
1880 /* Reserved for the future, and now filled with zero */
1881 *eax = 0;
1882 *ebx = 0;
1883 *ecx = 0;
1884 *edx = 0;
1885 break;
1886 default:
1887 /* reserved values: zero */
1888 *eax = 0;
1889 *ebx = 0;
1890 *ecx = 0;
1891 *edx = 0;
1892 break;
1893 }
1894 }
1895
1896 /* CPUClass::reset() */
1897 static void x86_cpu_reset(CPUState *s)
1898 {
1899 X86CPU *cpu = X86_CPU(s);
1900 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1901 CPUX86State *env = &cpu->env;
1902 int i;
1903
1904 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1905 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
1906 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1907 }
1908
1909 xcc->parent_reset(s);
1910
1911
1912 memset(env, 0, offsetof(CPUX86State, breakpoints));
1913
1914 tlb_flush(env, 1);
1915
1916 env->old_exception = -1;
1917
1918 /* init to reset state */
1919
1920 #ifdef CONFIG_SOFTMMU
1921 env->hflags |= HF_SOFTMMU_MASK;
1922 #endif
1923 env->hflags2 |= HF2_GIF_MASK;
1924
1925 cpu_x86_update_cr0(env, 0x60000010);
1926 env->a20_mask = ~0x0;
1927 env->smbase = 0x30000;
1928
1929 env->idt.limit = 0xffff;
1930 env->gdt.limit = 0xffff;
1931 env->ldt.limit = 0xffff;
1932 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1933 env->tr.limit = 0xffff;
1934 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1935
1936 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1937 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1938 DESC_R_MASK | DESC_A_MASK);
1939 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1940 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1941 DESC_A_MASK);
1942 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1943 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1944 DESC_A_MASK);
1945 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1946 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1947 DESC_A_MASK);
1948 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1949 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1950 DESC_A_MASK);
1951 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1952 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1953 DESC_A_MASK);
1954
1955 env->eip = 0xfff0;
1956 env->regs[R_EDX] = env->cpuid_version;
1957
1958 env->eflags = 0x2;
1959
1960 /* FPU init */
1961 for (i = 0; i < 8; i++) {
1962 env->fptags[i] = 1;
1963 }
1964 env->fpuc = 0x37f;
1965
1966 env->mxcsr = 0x1f80;
1967
1968 env->pat = 0x0007040600070406ULL;
1969 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1970
1971 memset(env->dr, 0, sizeof(env->dr));
1972 env->dr[6] = DR6_FIXED_1;
1973 env->dr[7] = DR7_FIXED_1;
1974 cpu_breakpoint_remove_all(env, BP_CPU);
1975 cpu_watchpoint_remove_all(env, BP_CPU);
1976
1977 #if !defined(CONFIG_USER_ONLY)
1978 /* We hard-wire the BSP to the first CPU. */
1979 if (s->cpu_index == 0) {
1980 apic_designate_bsp(env->apic_state);
1981 }
1982
1983 env->halted = !cpu_is_bsp(cpu);
1984 #endif
1985 }
1986
1987 #ifndef CONFIG_USER_ONLY
1988 bool cpu_is_bsp(X86CPU *cpu)
1989 {
1990 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
1991 }
1992
1993 /* TODO: remove me, when reset over QOM tree is implemented */
1994 static void x86_cpu_machine_reset_cb(void *opaque)
1995 {
1996 X86CPU *cpu = opaque;
1997 cpu_reset(CPU(cpu));
1998 }
1999 #endif
2000
2001 static void mce_init(X86CPU *cpu)
2002 {
2003 CPUX86State *cenv = &cpu->env;
2004 unsigned int bank;
2005
2006 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2007 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2008 (CPUID_MCE | CPUID_MCA)) {
2009 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2010 cenv->mcg_ctl = ~(uint64_t)0;
2011 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2012 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2013 }
2014 }
2015 }
2016
2017 #define MSI_ADDR_BASE 0xfee00000
2018
2019 #ifndef CONFIG_USER_ONLY
2020 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2021 {
2022 static int apic_mapped;
2023 CPUX86State *env = &cpu->env;
2024 APICCommonState *apic;
2025 const char *apic_type = "apic";
2026
2027 if (kvm_irqchip_in_kernel()) {
2028 apic_type = "kvm-apic";
2029 } else if (xen_enabled()) {
2030 apic_type = "xen-apic";
2031 }
2032
2033 env->apic_state = qdev_try_create(NULL, apic_type);
2034 if (env->apic_state == NULL) {
2035 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2036 return;
2037 }
2038
2039 object_property_add_child(OBJECT(cpu), "apic",
2040 OBJECT(env->apic_state), NULL);
2041 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2042 /* TODO: convert to link<> */
2043 apic = APIC_COMMON(env->apic_state);
2044 apic->cpu = cpu;
2045
2046 if (qdev_init(env->apic_state)) {
2047 error_setg(errp, "APIC device '%s' could not be initialized",
2048 object_get_typename(OBJECT(env->apic_state)));
2049 return;
2050 }
2051
2052 /* XXX: mapping more APICs at the same memory location */
2053 if (apic_mapped == 0) {
2054 /* NOTE: the APIC is directly connected to the CPU - it is not
2055 on the global memory bus. */
2056 /* XXX: what if the base changes? */
2057 sysbus_mmio_map(SYS_BUS_DEVICE(env->apic_state), 0, MSI_ADDR_BASE);
2058 apic_mapped = 1;
2059 }
2060 }
2061 #endif
2062
2063 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2064 {
2065 X86CPU *cpu = X86_CPU(dev);
2066 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2067 CPUX86State *env = &cpu->env;
2068 #ifndef CONFIG_USER_ONLY
2069 Error *local_err = NULL;
2070 #endif
2071
2072 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2073 env->cpuid_level = 7;
2074 }
2075
2076 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2077 * CPUID[1].EDX.
2078 */
2079 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2080 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2081 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2082 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2083 env->cpuid_ext2_features |= (env->cpuid_features
2084 & CPUID_EXT2_AMD_ALIASES);
2085 }
2086
2087 if (!kvm_enabled()) {
2088 env->cpuid_features &= TCG_FEATURES;
2089 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2090 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2091 #ifdef TARGET_X86_64
2092 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2093 #endif
2094 );
2095 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2096 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2097 } else {
2098 #ifdef CONFIG_KVM
2099 filter_features_for_kvm(cpu);
2100 #endif
2101 if (check_cpuid && kvm_check_features_against_host(cpu)
2102 && enforce_cpuid) {
2103 error_setg(errp, "Host's CPU doesn't support requested features");
2104 return;
2105 }
2106 }
2107
2108 #ifndef CONFIG_USER_ONLY
2109 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2110
2111 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2112 x86_cpu_apic_init(cpu, &local_err);
2113 if (local_err != NULL) {
2114 error_propagate(errp, local_err);
2115 return;
2116 }
2117 }
2118 #endif
2119
2120 mce_init(cpu);
2121 qemu_init_vcpu(&cpu->env);
2122 cpu_reset(CPU(cpu));
2123
2124 xcc->parent_realize(dev, errp);
2125 }
2126
2127 /* Enables contiguous-apic-ID mode, for compatibility */
2128 static bool compat_apic_id_mode;
2129
2130 void enable_compat_apic_id_mode(void)
2131 {
2132 compat_apic_id_mode = true;
2133 }
2134
2135 /* Calculates initial APIC ID for a specific CPU index
2136 *
2137 * Currently we need to be able to calculate the APIC ID from the CPU index
2138 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2139 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2140 * all CPUs up to max_cpus.
2141 */
2142 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2143 {
2144 uint32_t correct_id;
2145 static bool warned;
2146
2147 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2148 if (compat_apic_id_mode) {
2149 if (cpu_index != correct_id && !warned) {
2150 error_report("APIC IDs set in compatibility mode, "
2151 "CPU topology won't match the configuration");
2152 warned = true;
2153 }
2154 return cpu_index;
2155 } else {
2156 return correct_id;
2157 }
2158 }
2159
2160 static void x86_cpu_initfn(Object *obj)
2161 {
2162 CPUState *cs = CPU(obj);
2163 X86CPU *cpu = X86_CPU(obj);
2164 CPUX86State *env = &cpu->env;
2165 static int inited;
2166
2167 cpu_exec_init(env);
2168
2169 object_property_add(obj, "family", "int",
2170 x86_cpuid_version_get_family,
2171 x86_cpuid_version_set_family, NULL, NULL, NULL);
2172 object_property_add(obj, "model", "int",
2173 x86_cpuid_version_get_model,
2174 x86_cpuid_version_set_model, NULL, NULL, NULL);
2175 object_property_add(obj, "stepping", "int",
2176 x86_cpuid_version_get_stepping,
2177 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2178 object_property_add(obj, "level", "int",
2179 x86_cpuid_get_level,
2180 x86_cpuid_set_level, NULL, NULL, NULL);
2181 object_property_add(obj, "xlevel", "int",
2182 x86_cpuid_get_xlevel,
2183 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2184 object_property_add_str(obj, "vendor",
2185 x86_cpuid_get_vendor,
2186 x86_cpuid_set_vendor, NULL);
2187 object_property_add_str(obj, "model-id",
2188 x86_cpuid_get_model_id,
2189 x86_cpuid_set_model_id, NULL);
2190 object_property_add(obj, "tsc-frequency", "int",
2191 x86_cpuid_get_tsc_freq,
2192 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2193
2194 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2195
2196 /* init various static tables used in TCG mode */
2197 if (tcg_enabled() && !inited) {
2198 inited = 1;
2199 optimize_flags_init();
2200 #ifndef CONFIG_USER_ONLY
2201 cpu_set_debug_excp_handler(breakpoint_handler);
2202 #endif
2203 }
2204 }
2205
2206 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2207 {
2208 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2209 CPUClass *cc = CPU_CLASS(oc);
2210 DeviceClass *dc = DEVICE_CLASS(oc);
2211
2212 xcc->parent_realize = dc->realize;
2213 dc->realize = x86_cpu_realizefn;
2214
2215 xcc->parent_reset = cc->reset;
2216 cc->reset = x86_cpu_reset;
2217 }
2218
2219 static const TypeInfo x86_cpu_type_info = {
2220 .name = TYPE_X86_CPU,
2221 .parent = TYPE_CPU,
2222 .instance_size = sizeof(X86CPU),
2223 .instance_init = x86_cpu_initfn,
2224 .abstract = false,
2225 .class_size = sizeof(X86CPUClass),
2226 .class_init = x86_cpu_common_class_init,
2227 };
2228
2229 static void x86_cpu_register_types(void)
2230 {
2231 type_register_static(&x86_cpu_type_info);
2232 }
2233
2234 type_init(x86_cpu_register_types)
Qemu copy for testing