target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_I386_H
  21 #define CPU_I386_H
  22
  23 #include "cpu-defs.h"
  24
  25 #define R_EAX 0
  26 #define R_ECX 1
  27 #define R_EDX 2
  28 #define R_EBX 3
  29 #define R_ESP 4
  30 #define R_EBP 5
  31 #define R_ESI 6
  32 #define R_EDI 7
  33
  34 #define R_AL 0
  35 #define R_CL 1
  36 #define R_DL 2
  37 #define R_BL 3
  38 #define R_AH 4
  39 #define R_CH 5
  40 #define R_DH 6
  41 #define R_BH 7
  42
  43 #define R_ES 0
  44 #define R_CS 1
  45 #define R_SS 2
  46 #define R_DS 3
  47 #define R_FS 4
  48 #define R_GS 5
  49
  50 /* segment descriptor fields */
  51 #define DESC_G_MASK     (1 << 23)
  52 #define DESC_B_SHIFT    22
  53 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  54 #define DESC_AVL_MASK   (1 << 20)
  55 #define DESC_P_MASK     (1 << 15)
  56 #define DESC_DPL_SHIFT  13
  57 #define DESC_S_MASK     (1 << 12)
  58 #define DESC_TYPE_SHIFT 8
  59 #define DESC_A_MASK     (1 << 8)
  60
  61 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  62 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  63 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  64
  65 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  66 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  67
  68 #define DESC_TSS_BUSY_MASK (1 << 9)
  69
  70 /* eflags masks */
  71 #define CC_C    0x0001
  72 #define CC_P    0x0004
  73 #define CC_A    0x0010
  74 #define CC_Z    0x0040
  75 #define CC_S    0x0080
  76 #define CC_O    0x0800
  77
  78 #define TF_SHIFT   8
  79 #define IOPL_SHIFT 12
  80 #define VM_SHIFT   17
  81
  82 #define TF_MASK                 0x00000100
  83 #define IF_MASK                 0x00000200
  84 #define DF_MASK                 0x00000400
  85 #define IOPL_MASK               0x00003000
  86 #define NT_MASK                 0x00004000
  87 #define RF_MASK                 0x00010000
  88 #define VM_MASK                 0x00020000
  89 #define AC_MASK                 0x00040000
  90 #define VIF_MASK                0x00080000
  91 #define VIP_MASK                0x00100000
  92 #define ID_MASK                 0x00200000
  93
  94 /* hidden flags - used internally by qemu to represent additionnal cpu
  95    states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
  96    using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
  97    with eflags. */
  98 /* current cpl */
  99 #define HF_CPL_SHIFT         0
 100 /* true if soft mmu is being used */
 101 #define HF_SOFTMMU_SHIFT     2
 102 /* true if hardware interrupts must be disabled for next instruction */
 103 #define HF_INHIBIT_IRQ_SHIFT 3
 104 /* 16 or 32 segments */
 105 #define HF_CS32_SHIFT        4
 106 #define HF_SS32_SHIFT        5
 107 /* zero base for DS, ES and SS */
 108 #define HF_ADDSEG_SHIFT      6
 109
 110 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 111 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 112 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 113 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 114 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 115 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 116
 117 #define CR0_PE_MASK  (1 << 0)
 118 #define CR0_TS_MASK  (1 << 3)
 119 #define CR0_WP_MASK  (1 << 16)
 120 #define CR0_AM_MASK  (1 << 18)
 121 #define CR0_PG_MASK  (1 << 31)
 122
 123 #define CR4_VME_MASK  (1 << 0)
 124 #define CR4_PVI_MASK  (1 << 1)
 125 #define CR4_TSD_MASK  (1 << 2)
 126 #define CR4_DE_MASK   (1 << 3)
 127 #define CR4_PSE_MASK  (1 << 4)
 128
 129 #define PG_PRESENT_BIT  0
 130 #define PG_RW_BIT       1
 131 #define PG_USER_BIT     2
 132 #define PG_PWT_BIT      3
 133 #define PG_PCD_BIT      4
 134 #define PG_ACCESSED_BIT 5
 135 #define PG_DIRTY_BIT    6
 136 #define PG_PSE_BIT      7
 137 #define PG_GLOBAL_BIT   8
 138
 139 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 140 #define PG_RW_MASK       (1 << PG_RW_BIT)
 141 #define PG_USER_MASK     (1 << PG_USER_BIT)
 142 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 143 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 144 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 145 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 146 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 147 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 148
 149 #define PG_ERROR_W_BIT     1
 150
 151 #define PG_ERROR_P_MASK    0x01
 152 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 153 #define PG_ERROR_U_MASK    0x04
 154 #define PG_ERROR_RSVD_MASK 0x08
 155
 156 #define MSR_IA32_APICBASE               0x1b
 157 #define MSR_IA32_APICBASE_BSP           (1<<8)
 158 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 159 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 160
 161 #define MSR_IA32_SYSENTER_CS            0x174
 162 #define MSR_IA32_SYSENTER_ESP           0x175
 163 #define MSR_IA32_SYSENTER_EIP           0x176
 164
 165 #define EXCP00_DIVZ     0
 166 #define EXCP01_SSTP     1
 167 #define EXCP02_NMI      2
 168 #define EXCP03_INT3     3
 169 #define EXCP04_INTO     4
 170 #define EXCP05_BOUND    5
 171 #define EXCP06_ILLOP    6
 172 #define EXCP07_PREX     7
 173 #define EXCP08_DBLE     8
 174 #define EXCP09_XERR     9
 175 #define EXCP0A_TSS      10
 176 #define EXCP0B_NOSEG    11
 177 #define EXCP0C_STACK    12
 178 #define EXCP0D_GPF      13
 179 #define EXCP0E_PAGE     14
 180 #define EXCP10_COPR     16
 181 #define EXCP11_ALGN     17
 182 #define EXCP12_MCHK     18
 183
 184 enum {
 185     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 186     CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */
 187     CC_OP_MUL, /* modify all flags, C, O = (CC_SRC != 0) */
 188
 189     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 190     CC_OP_ADDW,
 191     CC_OP_ADDL,
 192
 193     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 194     CC_OP_ADCW,
 195     CC_OP_ADCL,
 196
 197     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 198     CC_OP_SUBW,
 199     CC_OP_SUBL,
 200
 201     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 202     CC_OP_SBBW,
 203     CC_OP_SBBL,
 204
 205     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 206     CC_OP_LOGICW,
 207     CC_OP_LOGICL,
 208
 209     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 210     CC_OP_INCW,
 211     CC_OP_INCL,
 212
 213     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 214     CC_OP_DECW,
 215     CC_OP_DECL,
 216
 217     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 218     CC_OP_SHLW,
 219     CC_OP_SHLL,
 220
 221     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 222     CC_OP_SARW,
 223     CC_OP_SARL,
 224
 225     CC_OP_NB,
 226 };
 227
 228 #ifdef __i386__
 229 #define USE_X86LDOUBLE
 230 #endif
 231
 232 #ifdef USE_X86LDOUBLE
 233 typedef long double CPU86_LDouble;
 234 #else
 235 typedef double CPU86_LDouble;
 236 #endif
 237
 238 typedef struct SegmentCache {
 239     uint32_t selector;
 240     uint8_t *base;
 241     uint32_t limit;
 242     uint32_t flags;
 243 } SegmentCache;
 244
 245 typedef struct CPUX86State {
 246     /* standard registers */
 247     uint32_t regs[8];
 248     uint32_t eip;
 249     uint32_t eflags; /* eflags register. During CPU emulation, CC
 250                         flags and DF are set to zero because they are
 251                         stored elsewhere */
 252
 253     /* emulator internal eflags handling */
 254     uint32_t cc_src;
 255     uint32_t cc_dst;
 256     uint32_t cc_op;
 257     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 258     uint32_t hflags; /* hidden flags, see HF_xxx constants */
 259
 260     /* FPU state */
 261     unsigned int fpstt; /* top of stack index */
 262     unsigned int fpus;
 263     unsigned int fpuc;
 264     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 265     CPU86_LDouble fpregs[8];
 266
 267     /* emulator internal variables */
 268     CPU86_LDouble ft0;
 269     union {
 270         float f;
 271         double d;
 272         int i32;
 273         int64_t i64;
 274     } fp_convert;
 275
 276     /* segments */
 277     SegmentCache segs[6]; /* selector values */
 278     SegmentCache ldt;
 279     SegmentCache tr;
 280     SegmentCache gdt; /* only base and limit are used */
 281     SegmentCache idt; /* only base and limit are used */
 282
 283     /* sysenter registers */
 284     uint32_t sysenter_cs;
 285     uint32_t sysenter_esp;
 286     uint32_t sysenter_eip;
 287
 288     /* exception/interrupt handling */
 289     jmp_buf jmp_env;
 290     int exception_index;
 291     int error_code;
 292     int exception_is_int;
 293     int exception_next_eip;
 294     struct TranslationBlock *current_tb; /* currently executing TB */
 295     uint32_t cr[5]; /* NOTE: cr1 is unused */
 296     uint32_t dr[8]; /* debug registers */
 297     int interrupt_request;
 298     int user_mode_only; /* user mode only simulation */
 299
 300     /* soft mmu support */
 301     /* 0 = kernel, 1 = user */
 302     CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
 303     CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
 304
 305     /* ice debug support */
 306     uint32_t breakpoints[MAX_BREAKPOINTS];
 307     int nb_breakpoints;
 308     int singlestep_enabled;
 309
 310     /* user data */
 311     void *opaque;
 312 } CPUX86State;
 313
 314 #ifndef IN_OP_I386
 315 void cpu_x86_outb(CPUX86State *env, int addr, int val);
 316 void cpu_x86_outw(CPUX86State *env, int addr, int val);
 317 void cpu_x86_outl(CPUX86State *env, int addr, int val);
 318 int cpu_x86_inb(CPUX86State *env, int addr);
 319 int cpu_x86_inw(CPUX86State *env, int addr);
 320 int cpu_x86_inl(CPUX86State *env, int addr);
 321 #endif
 322
 323 CPUX86State *cpu_x86_init(void);
 324 int cpu_x86_exec(CPUX86State *s);
 325 void cpu_x86_close(CPUX86State *s);
 326 int cpu_x86_get_pic_interrupt(CPUX86State *s);
 327
 328 /* this function must always be used to load data in the segment
 329    cache: it synchronizes the hflags with the segment cache values */
 330 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 331                                           int seg_reg, unsigned int selector,
 332                                           uint8_t *base, unsigned int limit,
 333                                           unsigned int flags)
 334 {
 335     SegmentCache *sc;
 336     unsigned int new_hflags;
 337
 338     sc = &env->segs[seg_reg];
 339     sc->selector = selector;
 340     sc->base = base;
 341     sc->limit = limit;
 342     sc->flags = flags;
 343
 344     /* update the hidden flags */
 345     new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 346         >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 347     new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK)
 348         >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 349     if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 350         /* XXX: try to avoid this test. The problem comes from the
 351            fact that is real mode or vm86 mode we only modify the
 352            'base' and 'selector' fields of the segment cache to go
 353            faster. A solution may be to force addseg to one in
 354            translate-i386.c. */
 355         new_hflags |= HF_ADDSEG_MASK;
 356     } else {
 357         new_hflags |= (((unsigned long)env->segs[R_DS].base |
 358                         (unsigned long)env->segs[R_ES].base |
 359                         (unsigned long)env->segs[R_SS].base) != 0) <<
 360             HF_ADDSEG_SHIFT;
 361     }
 362     env->hflags = (env->hflags &
 363                    ~(HF_CS32_MASK | HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 364 }
 365
 366 /* wrapper, just in case memory mappings must be changed */
 367 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 368 {
 369 #if HF_CPL_MASK == 3
 370     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
 371 #else
 372 #error HF_CPL_MASK is hardcoded
 373 #endif
 374 }
 375
 376 /* the following helpers are only usable in user mode simulation as
 377    they can trigger unexpected exceptions */
 378 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
 379 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
 380 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
 381
 382 /* you can call this signal handler from your SIGBUS and SIGSEGV
 383    signal handlers to inform the virtual CPU of exceptions. non zero
 384    is returned if the signal was handled by the virtual CPU.  */
 385 struct siginfo;
 386 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
 387                            void *puc);
 388
 389 /* MMU defines */
 390 void cpu_x86_init_mmu(CPUX86State *env);
 391 extern int phys_ram_size;
 392 extern int phys_ram_fd;
 393 extern uint8_t *phys_ram_base;
 394 extern int a20_enabled;
 395
 396 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
 397
 398 /* used to debug */
 399 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 400 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
 401 void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags);
 402
 403 #define TARGET_PAGE_BITS 12
 404 #include "cpu-all.h"
 405
 406 #endif /* CPU_I386_H */