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[qemu.git] / target-i386 / seg_helper.c
1 /*
2 * x86 segmentation related helpers:
3 * TSS, interrupts, system calls, jumps and call/task gates, descriptors
4 *
5 * Copyright (c) 2003 Fabrice Bellard
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "qemu/log.h"
23 #include "helper.h"
24
25 //#define DEBUG_PCALL
26
27 #if !defined(CONFIG_USER_ONLY)
28 #include "exec/softmmu_exec.h"
29 #endif /* !defined(CONFIG_USER_ONLY) */
30
31 #ifdef DEBUG_PCALL
32 # define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__)
33 # define LOG_PCALL_STATE(env) \
34 log_cpu_state_mask(CPU_LOG_PCALL, (env), CPU_DUMP_CCOP)
35 #else
36 # define LOG_PCALL(...) do { } while (0)
37 # define LOG_PCALL_STATE(env) do { } while (0)
38 #endif
39
40 /* return non zero if error */
41 static inline int load_segment(CPUX86State *env, uint32_t *e1_ptr,
42 uint32_t *e2_ptr, int selector)
43 {
44 SegmentCache *dt;
45 int index;
46 target_ulong ptr;
47
48 if (selector & 0x4) {
49 dt = &env->ldt;
50 } else {
51 dt = &env->gdt;
52 }
53 index = selector & ~7;
54 if ((index + 7) > dt->limit) {
55 return -1;
56 }
57 ptr = dt->base + index;
58 *e1_ptr = cpu_ldl_kernel(env, ptr);
59 *e2_ptr = cpu_ldl_kernel(env, ptr + 4);
60 return 0;
61 }
62
63 static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
64 {
65 unsigned int limit;
66
67 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
68 if (e2 & DESC_G_MASK) {
69 limit = (limit << 12) | 0xfff;
70 }
71 return limit;
72 }
73
74 static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
75 {
76 return (e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000);
77 }
78
79 static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1,
80 uint32_t e2)
81 {
82 sc->base = get_seg_base(e1, e2);
83 sc->limit = get_seg_limit(e1, e2);
84 sc->flags = e2;
85 }
86
87 /* init the segment cache in vm86 mode. */
88 static inline void load_seg_vm(CPUX86State *env, int seg, int selector)
89 {
90 selector &= 0xffff;
91 cpu_x86_load_seg_cache(env, seg, selector,
92 (selector << 4), 0xffff, 0);
93 }
94
95 static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
96 uint32_t *esp_ptr, int dpl)
97 {
98 int type, index, shift;
99
100 #if 0
101 {
102 int i;
103 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
104 for (i = 0; i < env->tr.limit; i++) {
105 printf("%02x ", env->tr.base[i]);
106 if ((i & 7) == 7) {
107 printf("\n");
108 }
109 }
110 printf("\n");
111 }
112 #endif
113
114 if (!(env->tr.flags & DESC_P_MASK)) {
115 cpu_abort(env, "invalid tss");
116 }
117 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
118 if ((type & 7) != 1) {
119 cpu_abort(env, "invalid tss type");
120 }
121 shift = type >> 3;
122 index = (dpl * 4 + 2) << shift;
123 if (index + (4 << shift) - 1 > env->tr.limit) {
124 raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
125 }
126 if (shift == 0) {
127 *esp_ptr = cpu_lduw_kernel(env, env->tr.base + index);
128 *ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 2);
129 } else {
130 *esp_ptr = cpu_ldl_kernel(env, env->tr.base + index);
131 *ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 4);
132 }
133 }
134
135 /* XXX: merge with load_seg() */
136 static void tss_load_seg(CPUX86State *env, int seg_reg, int selector)
137 {
138 uint32_t e1, e2;
139 int rpl, dpl, cpl;
140
141 if ((selector & 0xfffc) != 0) {
142 if (load_segment(env, &e1, &e2, selector) != 0) {
143 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
144 }
145 if (!(e2 & DESC_S_MASK)) {
146 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
147 }
148 rpl = selector & 3;
149 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
150 cpl = env->hflags & HF_CPL_MASK;
151 if (seg_reg == R_CS) {
152 if (!(e2 & DESC_CS_MASK)) {
153 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
154 }
155 /* XXX: is it correct? */
156 if (dpl != rpl) {
157 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
158 }
159 if ((e2 & DESC_C_MASK) && dpl > rpl) {
160 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
161 }
162 } else if (seg_reg == R_SS) {
163 /* SS must be writable data */
164 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
165 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
166 }
167 if (dpl != cpl || dpl != rpl) {
168 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
169 }
170 } else {
171 /* not readable code */
172 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK)) {
173 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
174 }
175 /* if data or non conforming code, checks the rights */
176 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
177 if (dpl < cpl || dpl < rpl) {
178 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
179 }
180 }
181 }
182 if (!(e2 & DESC_P_MASK)) {
183 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
184 }
185 cpu_x86_load_seg_cache(env, seg_reg, selector,
186 get_seg_base(e1, e2),
187 get_seg_limit(e1, e2),
188 e2);
189 } else {
190 if (seg_reg == R_SS || seg_reg == R_CS) {
191 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
192 }
193 }
194 }
195
196 #define SWITCH_TSS_JMP 0
197 #define SWITCH_TSS_IRET 1
198 #define SWITCH_TSS_CALL 2
199
200 /* XXX: restore CPU state in registers (PowerPC case) */
201 static void switch_tss(CPUX86State *env, int tss_selector,
202 uint32_t e1, uint32_t e2, int source,
203 uint32_t next_eip)
204 {
205 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
206 target_ulong tss_base;
207 uint32_t new_regs[8], new_segs[6];
208 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
209 uint32_t old_eflags, eflags_mask;
210 SegmentCache *dt;
211 int index;
212 target_ulong ptr;
213
214 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
215 LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type,
216 source);
217
218 /* if task gate, we read the TSS segment and we load it */
219 if (type == 5) {
220 if (!(e2 & DESC_P_MASK)) {
221 raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
222 }
223 tss_selector = e1 >> 16;
224 if (tss_selector & 4) {
225 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
226 }
227 if (load_segment(env, &e1, &e2, tss_selector) != 0) {
228 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
229 }
230 if (e2 & DESC_S_MASK) {
231 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
232 }
233 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
234 if ((type & 7) != 1) {
235 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
236 }
237 }
238
239 if (!(e2 & DESC_P_MASK)) {
240 raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
241 }
242
243 if (type & 8) {
244 tss_limit_max = 103;
245 } else {
246 tss_limit_max = 43;
247 }
248 tss_limit = get_seg_limit(e1, e2);
249 tss_base = get_seg_base(e1, e2);
250 if ((tss_selector & 4) != 0 ||
251 tss_limit < tss_limit_max) {
252 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
253 }
254 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
255 if (old_type & 8) {
256 old_tss_limit_max = 103;
257 } else {
258 old_tss_limit_max = 43;
259 }
260
261 /* read all the registers from the new TSS */
262 if (type & 8) {
263 /* 32 bit */
264 new_cr3 = cpu_ldl_kernel(env, tss_base + 0x1c);
265 new_eip = cpu_ldl_kernel(env, tss_base + 0x20);
266 new_eflags = cpu_ldl_kernel(env, tss_base + 0x24);
267 for (i = 0; i < 8; i++) {
268 new_regs[i] = cpu_ldl_kernel(env, tss_base + (0x28 + i * 4));
269 }
270 for (i = 0; i < 6; i++) {
271 new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x48 + i * 4));
272 }
273 new_ldt = cpu_lduw_kernel(env, tss_base + 0x60);
274 new_trap = cpu_ldl_kernel(env, tss_base + 0x64);
275 } else {
276 /* 16 bit */
277 new_cr3 = 0;
278 new_eip = cpu_lduw_kernel(env, tss_base + 0x0e);
279 new_eflags = cpu_lduw_kernel(env, tss_base + 0x10);
280 for (i = 0; i < 8; i++) {
281 new_regs[i] = cpu_lduw_kernel(env, tss_base + (0x12 + i * 2)) |
282 0xffff0000;
283 }
284 for (i = 0; i < 4; i++) {
285 new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x22 + i * 4));
286 }
287 new_ldt = cpu_lduw_kernel(env, tss_base + 0x2a);
288 new_segs[R_FS] = 0;
289 new_segs[R_GS] = 0;
290 new_trap = 0;
291 }
292 /* XXX: avoid a compiler warning, see
293 http://support.amd.com/us/Processor_TechDocs/24593.pdf
294 chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */
295 (void)new_trap;
296
297 /* NOTE: we must avoid memory exceptions during the task switch,
298 so we make dummy accesses before */
299 /* XXX: it can still fail in some cases, so a bigger hack is
300 necessary to valid the TLB after having done the accesses */
301
302 v1 = cpu_ldub_kernel(env, env->tr.base);
303 v2 = cpu_ldub_kernel(env, env->tr.base + old_tss_limit_max);
304 cpu_stb_kernel(env, env->tr.base, v1);
305 cpu_stb_kernel(env, env->tr.base + old_tss_limit_max, v2);
306
307 /* clear busy bit (it is restartable) */
308 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
309 target_ulong ptr;
310 uint32_t e2;
311
312 ptr = env->gdt.base + (env->tr.selector & ~7);
313 e2 = cpu_ldl_kernel(env, ptr + 4);
314 e2 &= ~DESC_TSS_BUSY_MASK;
315 cpu_stl_kernel(env, ptr + 4, e2);
316 }
317 old_eflags = cpu_compute_eflags(env);
318 if (source == SWITCH_TSS_IRET) {
319 old_eflags &= ~NT_MASK;
320 }
321
322 /* save the current state in the old TSS */
323 if (type & 8) {
324 /* 32 bit */
325 cpu_stl_kernel(env, env->tr.base + 0x20, next_eip);
326 cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags);
327 cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), EAX);
328 cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), ECX);
329 cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), EDX);
330 cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), EBX);
331 cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), ESP);
332 cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), EBP);
333 cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), ESI);
334 cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), EDI);
335 for (i = 0; i < 6; i++) {
336 cpu_stw_kernel(env, env->tr.base + (0x48 + i * 4),
337 env->segs[i].selector);
338 }
339 } else {
340 /* 16 bit */
341 cpu_stw_kernel(env, env->tr.base + 0x0e, next_eip);
342 cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags);
343 cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), EAX);
344 cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), ECX);
345 cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), EDX);
346 cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), EBX);
347 cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), ESP);
348 cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), EBP);
349 cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), ESI);
350 cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), EDI);
351 for (i = 0; i < 4; i++) {
352 cpu_stw_kernel(env, env->tr.base + (0x22 + i * 4),
353 env->segs[i].selector);
354 }
355 }
356
357 /* now if an exception occurs, it will occurs in the next task
358 context */
359
360 if (source == SWITCH_TSS_CALL) {
361 cpu_stw_kernel(env, tss_base, env->tr.selector);
362 new_eflags |= NT_MASK;
363 }
364
365 /* set busy bit */
366 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
367 target_ulong ptr;
368 uint32_t e2;
369
370 ptr = env->gdt.base + (tss_selector & ~7);
371 e2 = cpu_ldl_kernel(env, ptr + 4);
372 e2 |= DESC_TSS_BUSY_MASK;
373 cpu_stl_kernel(env, ptr + 4, e2);
374 }
375
376 /* set the new CPU state */
377 /* from this point, any exception which occurs can give problems */
378 env->cr[0] |= CR0_TS_MASK;
379 env->hflags |= HF_TS_MASK;
380 env->tr.selector = tss_selector;
381 env->tr.base = tss_base;
382 env->tr.limit = tss_limit;
383 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
384
385 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
386 cpu_x86_update_cr3(env, new_cr3);
387 }
388
389 /* load all registers without an exception, then reload them with
390 possible exception */
391 env->eip = new_eip;
392 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
393 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
394 if (!(type & 8)) {
395 eflags_mask &= 0xffff;
396 }
397 cpu_load_eflags(env, new_eflags, eflags_mask);
398 /* XXX: what to do in 16 bit case? */
399 EAX = new_regs[0];
400 ECX = new_regs[1];
401 EDX = new_regs[2];
402 EBX = new_regs[3];
403 ESP = new_regs[4];
404 EBP = new_regs[5];
405 ESI = new_regs[6];
406 EDI = new_regs[7];
407 if (new_eflags & VM_MASK) {
408 for (i = 0; i < 6; i++) {
409 load_seg_vm(env, i, new_segs[i]);
410 }
411 /* in vm86, CPL is always 3 */
412 cpu_x86_set_cpl(env, 3);
413 } else {
414 /* CPL is set the RPL of CS */
415 cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
416 /* first just selectors as the rest may trigger exceptions */
417 for (i = 0; i < 6; i++) {
418 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
419 }
420 }
421
422 env->ldt.selector = new_ldt & ~4;
423 env->ldt.base = 0;
424 env->ldt.limit = 0;
425 env->ldt.flags = 0;
426
427 /* load the LDT */
428 if (new_ldt & 4) {
429 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
430 }
431
432 if ((new_ldt & 0xfffc) != 0) {
433 dt = &env->gdt;
434 index = new_ldt & ~7;
435 if ((index + 7) > dt->limit) {
436 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
437 }
438 ptr = dt->base + index;
439 e1 = cpu_ldl_kernel(env, ptr);
440 e2 = cpu_ldl_kernel(env, ptr + 4);
441 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
442 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
443 }
444 if (!(e2 & DESC_P_MASK)) {
445 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
446 }
447 load_seg_cache_raw_dt(&env->ldt, e1, e2);
448 }
449
450 /* load the segments */
451 if (!(new_eflags & VM_MASK)) {
452 tss_load_seg(env, R_CS, new_segs[R_CS]);
453 tss_load_seg(env, R_SS, new_segs[R_SS]);
454 tss_load_seg(env, R_ES, new_segs[R_ES]);
455 tss_load_seg(env, R_DS, new_segs[R_DS]);
456 tss_load_seg(env, R_FS, new_segs[R_FS]);
457 tss_load_seg(env, R_GS, new_segs[R_GS]);
458 }
459
460 /* check that EIP is in the CS segment limits */
461 if (new_eip > env->segs[R_CS].limit) {
462 /* XXX: different exception if CALL? */
463 raise_exception_err(env, EXCP0D_GPF, 0);
464 }
465
466 #ifndef CONFIG_USER_ONLY
467 /* reset local breakpoints */
468 if (env->dr[7] & DR7_LOCAL_BP_MASK) {
469 for (i = 0; i < DR7_MAX_BP; i++) {
470 if (hw_local_breakpoint_enabled(env->dr[7], i) &&
471 !hw_global_breakpoint_enabled(env->dr[7], i)) {
472 hw_breakpoint_remove(env, i);
473 }
474 }
475 env->dr[7] &= ~DR7_LOCAL_BP_MASK;
476 }
477 #endif
478 }
479
480 static inline unsigned int get_sp_mask(unsigned int e2)
481 {
482 if (e2 & DESC_B_MASK) {
483 return 0xffffffff;
484 } else {
485 return 0xffff;
486 }
487 }
488
489 static int exception_has_error_code(int intno)
490 {
491 switch (intno) {
492 case 8:
493 case 10:
494 case 11:
495 case 12:
496 case 13:
497 case 14:
498 case 17:
499 return 1;
500 }
501 return 0;
502 }
503
504 #ifdef TARGET_X86_64
505 #define SET_ESP(val, sp_mask) \
506 do { \
507 if ((sp_mask) == 0xffff) { \
508 ESP = (ESP & ~0xffff) | ((val) & 0xffff); \
509 } else if ((sp_mask) == 0xffffffffLL) { \
510 ESP = (uint32_t)(val); \
511 } else { \
512 ESP = (val); \
513 } \
514 } while (0)
515 #else
516 #define SET_ESP(val, sp_mask) \
517 do { \
518 ESP = (ESP & ~(sp_mask)) | ((val) & (sp_mask)); \
519 } while (0)
520 #endif
521
522 /* in 64-bit machines, this can overflow. So this segment addition macro
523 * can be used to trim the value to 32-bit whenever needed */
524 #define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))
525
526 /* XXX: add a is_user flag to have proper security support */
527 #define PUSHW(ssp, sp, sp_mask, val) \
528 { \
529 sp -= 2; \
530 cpu_stw_kernel(env, (ssp) + (sp & (sp_mask)), (val)); \
531 }
532
533 #define PUSHL(ssp, sp, sp_mask, val) \
534 { \
535 sp -= 4; \
536 cpu_stl_kernel(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val)); \
537 }
538
539 #define POPW(ssp, sp, sp_mask, val) \
540 { \
541 val = cpu_lduw_kernel(env, (ssp) + (sp & (sp_mask))); \
542 sp += 2; \
543 }
544
545 #define POPL(ssp, sp, sp_mask, val) \
546 { \
547 val = (uint32_t)cpu_ldl_kernel(env, SEG_ADDL(ssp, sp, sp_mask)); \
548 sp += 4; \
549 }
550
551 /* protected mode interrupt */
552 static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
553 int error_code, unsigned int next_eip,
554 int is_hw)
555 {
556 SegmentCache *dt;
557 target_ulong ptr, ssp;
558 int type, dpl, selector, ss_dpl, cpl;
559 int has_error_code, new_stack, shift;
560 uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0;
561 uint32_t old_eip, sp_mask;
562
563 has_error_code = 0;
564 if (!is_int && !is_hw) {
565 has_error_code = exception_has_error_code(intno);
566 }
567 if (is_int) {
568 old_eip = next_eip;
569 } else {
570 old_eip = env->eip;
571 }
572
573 dt = &env->idt;
574 if (intno * 8 + 7 > dt->limit) {
575 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
576 }
577 ptr = dt->base + intno * 8;
578 e1 = cpu_ldl_kernel(env, ptr);
579 e2 = cpu_ldl_kernel(env, ptr + 4);
580 /* check gate type */
581 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
582 switch (type) {
583 case 5: /* task gate */
584 /* must do that check here to return the correct error code */
585 if (!(e2 & DESC_P_MASK)) {
586 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
587 }
588 switch_tss(env, intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
589 if (has_error_code) {
590 int type;
591 uint32_t mask;
592
593 /* push the error code */
594 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
595 shift = type >> 3;
596 if (env->segs[R_SS].flags & DESC_B_MASK) {
597 mask = 0xffffffff;
598 } else {
599 mask = 0xffff;
600 }
601 esp = (ESP - (2 << shift)) & mask;
602 ssp = env->segs[R_SS].base + esp;
603 if (shift) {
604 cpu_stl_kernel(env, ssp, error_code);
605 } else {
606 cpu_stw_kernel(env, ssp, error_code);
607 }
608 SET_ESP(esp, mask);
609 }
610 return;
611 case 6: /* 286 interrupt gate */
612 case 7: /* 286 trap gate */
613 case 14: /* 386 interrupt gate */
614 case 15: /* 386 trap gate */
615 break;
616 default:
617 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
618 break;
619 }
620 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
621 cpl = env->hflags & HF_CPL_MASK;
622 /* check privilege if software int */
623 if (is_int && dpl < cpl) {
624 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
625 }
626 /* check valid bit */
627 if (!(e2 & DESC_P_MASK)) {
628 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
629 }
630 selector = e1 >> 16;
631 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
632 if ((selector & 0xfffc) == 0) {
633 raise_exception_err(env, EXCP0D_GPF, 0);
634 }
635 if (load_segment(env, &e1, &e2, selector) != 0) {
636 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
637 }
638 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
639 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
640 }
641 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
642 if (dpl > cpl) {
643 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
644 }
645 if (!(e2 & DESC_P_MASK)) {
646 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
647 }
648 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
649 /* to inner privilege */
650 get_ss_esp_from_tss(env, &ss, &esp, dpl);
651 if ((ss & 0xfffc) == 0) {
652 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
653 }
654 if ((ss & 3) != dpl) {
655 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
656 }
657 if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) {
658 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
659 }
660 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
661 if (ss_dpl != dpl) {
662 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
663 }
664 if (!(ss_e2 & DESC_S_MASK) ||
665 (ss_e2 & DESC_CS_MASK) ||
666 !(ss_e2 & DESC_W_MASK)) {
667 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
668 }
669 if (!(ss_e2 & DESC_P_MASK)) {
670 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
671 }
672 new_stack = 1;
673 sp_mask = get_sp_mask(ss_e2);
674 ssp = get_seg_base(ss_e1, ss_e2);
675 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
676 /* to same privilege */
677 if (env->eflags & VM_MASK) {
678 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
679 }
680 new_stack = 0;
681 sp_mask = get_sp_mask(env->segs[R_SS].flags);
682 ssp = env->segs[R_SS].base;
683 esp = ESP;
684 dpl = cpl;
685 } else {
686 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
687 new_stack = 0; /* avoid warning */
688 sp_mask = 0; /* avoid warning */
689 ssp = 0; /* avoid warning */
690 esp = 0; /* avoid warning */
691 }
692
693 shift = type >> 3;
694
695 #if 0
696 /* XXX: check that enough room is available */
697 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
698 if (env->eflags & VM_MASK) {
699 push_size += 8;
700 }
701 push_size <<= shift;
702 #endif
703 if (shift == 1) {
704 if (new_stack) {
705 if (env->eflags & VM_MASK) {
706 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
707 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
708 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
709 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
710 }
711 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
712 PUSHL(ssp, esp, sp_mask, ESP);
713 }
714 PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env));
715 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
716 PUSHL(ssp, esp, sp_mask, old_eip);
717 if (has_error_code) {
718 PUSHL(ssp, esp, sp_mask, error_code);
719 }
720 } else {
721 if (new_stack) {
722 if (env->eflags & VM_MASK) {
723 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
724 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
725 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
726 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
727 }
728 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
729 PUSHW(ssp, esp, sp_mask, ESP);
730 }
731 PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env));
732 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
733 PUSHW(ssp, esp, sp_mask, old_eip);
734 if (has_error_code) {
735 PUSHW(ssp, esp, sp_mask, error_code);
736 }
737 }
738
739 if (new_stack) {
740 if (env->eflags & VM_MASK) {
741 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
742 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
743 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
744 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
745 }
746 ss = (ss & ~3) | dpl;
747 cpu_x86_load_seg_cache(env, R_SS, ss,
748 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
749 }
750 SET_ESP(esp, sp_mask);
751
752 selector = (selector & ~3) | dpl;
753 cpu_x86_load_seg_cache(env, R_CS, selector,
754 get_seg_base(e1, e2),
755 get_seg_limit(e1, e2),
756 e2);
757 cpu_x86_set_cpl(env, dpl);
758 env->eip = offset;
759
760 /* interrupt gate clear IF mask */
761 if ((type & 1) == 0) {
762 env->eflags &= ~IF_MASK;
763 }
764 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
765 }
766
767 #ifdef TARGET_X86_64
768
769 #define PUSHQ(sp, val) \
770 { \
771 sp -= 8; \
772 cpu_stq_kernel(env, sp, (val)); \
773 }
774
775 #define POPQ(sp, val) \
776 { \
777 val = cpu_ldq_kernel(env, sp); \
778 sp += 8; \
779 }
780
781 static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
782 {
783 int index;
784
785 #if 0
786 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
787 env->tr.base, env->tr.limit);
788 #endif
789
790 if (!(env->tr.flags & DESC_P_MASK)) {
791 cpu_abort(env, "invalid tss");
792 }
793 index = 8 * level + 4;
794 if ((index + 7) > env->tr.limit) {
795 raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
796 }
797 return cpu_ldq_kernel(env, env->tr.base + index);
798 }
799
800 /* 64 bit interrupt */
801 static void do_interrupt64(CPUX86State *env, int intno, int is_int,
802 int error_code, target_ulong next_eip, int is_hw)
803 {
804 SegmentCache *dt;
805 target_ulong ptr;
806 int type, dpl, selector, cpl, ist;
807 int has_error_code, new_stack;
808 uint32_t e1, e2, e3, ss;
809 target_ulong old_eip, esp, offset;
810
811 has_error_code = 0;
812 if (!is_int && !is_hw) {
813 has_error_code = exception_has_error_code(intno);
814 }
815 if (is_int) {
816 old_eip = next_eip;
817 } else {
818 old_eip = env->eip;
819 }
820
821 dt = &env->idt;
822 if (intno * 16 + 15 > dt->limit) {
823 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
824 }
825 ptr = dt->base + intno * 16;
826 e1 = cpu_ldl_kernel(env, ptr);
827 e2 = cpu_ldl_kernel(env, ptr + 4);
828 e3 = cpu_ldl_kernel(env, ptr + 8);
829 /* check gate type */
830 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
831 switch (type) {
832 case 14: /* 386 interrupt gate */
833 case 15: /* 386 trap gate */
834 break;
835 default:
836 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
837 break;
838 }
839 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
840 cpl = env->hflags & HF_CPL_MASK;
841 /* check privilege if software int */
842 if (is_int && dpl < cpl) {
843 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
844 }
845 /* check valid bit */
846 if (!(e2 & DESC_P_MASK)) {
847 raise_exception_err(env, EXCP0B_NOSEG, intno * 16 + 2);
848 }
849 selector = e1 >> 16;
850 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
851 ist = e2 & 7;
852 if ((selector & 0xfffc) == 0) {
853 raise_exception_err(env, EXCP0D_GPF, 0);
854 }
855
856 if (load_segment(env, &e1, &e2, selector) != 0) {
857 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
858 }
859 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
860 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
861 }
862 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
863 if (dpl > cpl) {
864 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
865 }
866 if (!(e2 & DESC_P_MASK)) {
867 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
868 }
869 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) {
870 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
871 }
872 if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
873 /* to inner privilege */
874 if (ist != 0) {
875 esp = get_rsp_from_tss(env, ist + 3);
876 } else {
877 esp = get_rsp_from_tss(env, dpl);
878 }
879 esp &= ~0xfLL; /* align stack */
880 ss = 0;
881 new_stack = 1;
882 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
883 /* to same privilege */
884 if (env->eflags & VM_MASK) {
885 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
886 }
887 new_stack = 0;
888 if (ist != 0) {
889 esp = get_rsp_from_tss(env, ist + 3);
890 } else {
891 esp = ESP;
892 }
893 esp &= ~0xfLL; /* align stack */
894 dpl = cpl;
895 } else {
896 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
897 new_stack = 0; /* avoid warning */
898 esp = 0; /* avoid warning */
899 }
900
901 PUSHQ(esp, env->segs[R_SS].selector);
902 PUSHQ(esp, ESP);
903 PUSHQ(esp, cpu_compute_eflags(env));
904 PUSHQ(esp, env->segs[R_CS].selector);
905 PUSHQ(esp, old_eip);
906 if (has_error_code) {
907 PUSHQ(esp, error_code);
908 }
909
910 if (new_stack) {
911 ss = 0 | dpl;
912 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
913 }
914 ESP = esp;
915
916 selector = (selector & ~3) | dpl;
917 cpu_x86_load_seg_cache(env, R_CS, selector,
918 get_seg_base(e1, e2),
919 get_seg_limit(e1, e2),
920 e2);
921 cpu_x86_set_cpl(env, dpl);
922 env->eip = offset;
923
924 /* interrupt gate clear IF mask */
925 if ((type & 1) == 0) {
926 env->eflags &= ~IF_MASK;
927 }
928 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
929 }
930 #endif
931
932 #ifdef TARGET_X86_64
933 #if defined(CONFIG_USER_ONLY)
934 void helper_syscall(CPUX86State *env, int next_eip_addend)
935 {
936 env->exception_index = EXCP_SYSCALL;
937 env->exception_next_eip = env->eip + next_eip_addend;
938 cpu_loop_exit(env);
939 }
940 #else
941 void helper_syscall(CPUX86State *env, int next_eip_addend)
942 {
943 int selector;
944
945 if (!(env->efer & MSR_EFER_SCE)) {
946 raise_exception_err(env, EXCP06_ILLOP, 0);
947 }
948 selector = (env->star >> 32) & 0xffff;
949 if (env->hflags & HF_LMA_MASK) {
950 int code64;
951
952 ECX = env->eip + next_eip_addend;
953 env->regs[11] = cpu_compute_eflags(env);
954
955 code64 = env->hflags & HF_CS64_MASK;
956
957 cpu_x86_set_cpl(env, 0);
958 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
959 0, 0xffffffff,
960 DESC_G_MASK | DESC_P_MASK |
961 DESC_S_MASK |
962 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
963 DESC_L_MASK);
964 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
965 0, 0xffffffff,
966 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
967 DESC_S_MASK |
968 DESC_W_MASK | DESC_A_MASK);
969 env->eflags &= ~env->fmask;
970 cpu_load_eflags(env, env->eflags, 0);
971 if (code64) {
972 env->eip = env->lstar;
973 } else {
974 env->eip = env->cstar;
975 }
976 } else {
977 ECX = (uint32_t)(env->eip + next_eip_addend);
978
979 cpu_x86_set_cpl(env, 0);
980 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
981 0, 0xffffffff,
982 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
983 DESC_S_MASK |
984 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
985 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
986 0, 0xffffffff,
987 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
988 DESC_S_MASK |
989 DESC_W_MASK | DESC_A_MASK);
990 env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
991 env->eip = (uint32_t)env->star;
992 }
993 }
994 #endif
995 #endif
996
997 #ifdef TARGET_X86_64
998 void helper_sysret(CPUX86State *env, int dflag)
999 {
1000 int cpl, selector;
1001
1002 if (!(env->efer & MSR_EFER_SCE)) {
1003 raise_exception_err(env, EXCP06_ILLOP, 0);
1004 }
1005 cpl = env->hflags & HF_CPL_MASK;
1006 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
1007 raise_exception_err(env, EXCP0D_GPF, 0);
1008 }
1009 selector = (env->star >> 48) & 0xffff;
1010 if (env->hflags & HF_LMA_MASK) {
1011 if (dflag == 2) {
1012 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1013 0, 0xffffffff,
1014 DESC_G_MASK | DESC_P_MASK |
1015 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1016 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1017 DESC_L_MASK);
1018 env->eip = ECX;
1019 } else {
1020 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1021 0, 0xffffffff,
1022 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1023 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1024 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1025 env->eip = (uint32_t)ECX;
1026 }
1027 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1028 0, 0xffffffff,
1029 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1030 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1031 DESC_W_MASK | DESC_A_MASK);
1032 cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK
1033 | ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK |
1034 NT_MASK);
1035 cpu_x86_set_cpl(env, 3);
1036 } else {
1037 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1038 0, 0xffffffff,
1039 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1040 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1041 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1042 env->eip = (uint32_t)ECX;
1043 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1044 0, 0xffffffff,
1045 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1046 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1047 DESC_W_MASK | DESC_A_MASK);
1048 env->eflags |= IF_MASK;
1049 cpu_x86_set_cpl(env, 3);
1050 }
1051 }
1052 #endif
1053
1054 /* real mode interrupt */
1055 static void do_interrupt_real(CPUX86State *env, int intno, int is_int,
1056 int error_code, unsigned int next_eip)
1057 {
1058 SegmentCache *dt;
1059 target_ulong ptr, ssp;
1060 int selector;
1061 uint32_t offset, esp;
1062 uint32_t old_cs, old_eip;
1063
1064 /* real mode (simpler!) */
1065 dt = &env->idt;
1066 if (intno * 4 + 3 > dt->limit) {
1067 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
1068 }
1069 ptr = dt->base + intno * 4;
1070 offset = cpu_lduw_kernel(env, ptr);
1071 selector = cpu_lduw_kernel(env, ptr + 2);
1072 esp = ESP;
1073 ssp = env->segs[R_SS].base;
1074 if (is_int) {
1075 old_eip = next_eip;
1076 } else {
1077 old_eip = env->eip;
1078 }
1079 old_cs = env->segs[R_CS].selector;
1080 /* XXX: use SS segment size? */
1081 PUSHW(ssp, esp, 0xffff, cpu_compute_eflags(env));
1082 PUSHW(ssp, esp, 0xffff, old_cs);
1083 PUSHW(ssp, esp, 0xffff, old_eip);
1084
1085 /* update processor state */
1086 ESP = (ESP & ~0xffff) | (esp & 0xffff);
1087 env->eip = offset;
1088 env->segs[R_CS].selector = selector;
1089 env->segs[R_CS].base = (selector << 4);
1090 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1091 }
1092
1093 #if defined(CONFIG_USER_ONLY)
1094 /* fake user mode interrupt */
1095 static void do_interrupt_user(CPUX86State *env, int intno, int is_int,
1096 int error_code, target_ulong next_eip)
1097 {
1098 SegmentCache *dt;
1099 target_ulong ptr;
1100 int dpl, cpl, shift;
1101 uint32_t e2;
1102
1103 dt = &env->idt;
1104 if (env->hflags & HF_LMA_MASK) {
1105 shift = 4;
1106 } else {
1107 shift = 3;
1108 }
1109 ptr = dt->base + (intno << shift);
1110 e2 = cpu_ldl_kernel(env, ptr + 4);
1111
1112 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1113 cpl = env->hflags & HF_CPL_MASK;
1114 /* check privilege if software int */
1115 if (is_int && dpl < cpl) {
1116 raise_exception_err(env, EXCP0D_GPF, (intno << shift) + 2);
1117 }
1118
1119 /* Since we emulate only user space, we cannot do more than
1120 exiting the emulation with the suitable exception and error
1121 code */
1122 if (is_int) {
1123 EIP = next_eip;
1124 }
1125 }
1126
1127 #else
1128
1129 static void handle_even_inj(CPUX86State *env, int intno, int is_int,
1130 int error_code, int is_hw, int rm)
1131 {
1132 uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
1133 control.event_inj));
1134
1135 if (!(event_inj & SVM_EVTINJ_VALID)) {
1136 int type;
1137
1138 if (is_int) {
1139 type = SVM_EVTINJ_TYPE_SOFT;
1140 } else {
1141 type = SVM_EVTINJ_TYPE_EXEPT;
1142 }
1143 event_inj = intno | type | SVM_EVTINJ_VALID;
1144 if (!rm && exception_has_error_code(intno)) {
1145 event_inj |= SVM_EVTINJ_VALID_ERR;
1146 stl_phys(env->vm_vmcb + offsetof(struct vmcb,
1147 control.event_inj_err),
1148 error_code);
1149 }
1150 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
1151 event_inj);
1152 }
1153 }
1154 #endif
1155
1156 /*
1157 * Begin execution of an interruption. is_int is TRUE if coming from
1158 * the int instruction. next_eip is the EIP value AFTER the interrupt
1159 * instruction. It is only relevant if is_int is TRUE.
1160 */
1161 static void do_interrupt_all(CPUX86State *env, int intno, int is_int,
1162 int error_code, target_ulong next_eip, int is_hw)
1163 {
1164 if (qemu_loglevel_mask(CPU_LOG_INT)) {
1165 if ((env->cr[0] & CR0_PE_MASK)) {
1166 static int count;
1167
1168 qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx
1169 " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1170 count, intno, error_code, is_int,
1171 env->hflags & HF_CPL_MASK,
1172 env->segs[R_CS].selector, EIP,
1173 (int)env->segs[R_CS].base + EIP,
1174 env->segs[R_SS].selector, ESP);
1175 if (intno == 0x0e) {
1176 qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);
1177 } else {
1178 qemu_log(" EAX=" TARGET_FMT_lx, EAX);
1179 }
1180 qemu_log("\n");
1181 log_cpu_state(env, CPU_DUMP_CCOP);
1182 #if 0
1183 {
1184 int i;
1185 target_ulong ptr;
1186
1187 qemu_log(" code=");
1188 ptr = env->segs[R_CS].base + env->eip;
1189 for (i = 0; i < 16; i++) {
1190 qemu_log(" %02x", ldub(ptr + i));
1191 }
1192 qemu_log("\n");
1193 }
1194 #endif
1195 count++;
1196 }
1197 }
1198 if (env->cr[0] & CR0_PE_MASK) {
1199 #if !defined(CONFIG_USER_ONLY)
1200 if (env->hflags & HF_SVMI_MASK) {
1201 handle_even_inj(env, intno, is_int, error_code, is_hw, 0);
1202 }
1203 #endif
1204 #ifdef TARGET_X86_64
1205 if (env->hflags & HF_LMA_MASK) {
1206 do_interrupt64(env, intno, is_int, error_code, next_eip, is_hw);
1207 } else
1208 #endif
1209 {
1210 do_interrupt_protected(env, intno, is_int, error_code, next_eip,
1211 is_hw);
1212 }
1213 } else {
1214 #if !defined(CONFIG_USER_ONLY)
1215 if (env->hflags & HF_SVMI_MASK) {
1216 handle_even_inj(env, intno, is_int, error_code, is_hw, 1);
1217 }
1218 #endif
1219 do_interrupt_real(env, intno, is_int, error_code, next_eip);
1220 }
1221
1222 #if !defined(CONFIG_USER_ONLY)
1223 if (env->hflags & HF_SVMI_MASK) {
1224 uint32_t event_inj = ldl_phys(env->vm_vmcb +
1225 offsetof(struct vmcb,
1226 control.event_inj));
1227
1228 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
1229 event_inj & ~SVM_EVTINJ_VALID);
1230 }
1231 #endif
1232 }
1233
1234 void do_interrupt(CPUX86State *env)
1235 {
1236 #if defined(CONFIG_USER_ONLY)
1237 /* if user mode only, we simulate a fake exception
1238 which will be handled outside the cpu execution
1239 loop */
1240 do_interrupt_user(env, env->exception_index,
1241 env->exception_is_int,
1242 env->error_code,
1243 env->exception_next_eip);
1244 /* successfully delivered */
1245 env->old_exception = -1;
1246 #else
1247 /* simulate a real cpu exception. On i386, it can
1248 trigger new exceptions, but we do not handle
1249 double or triple faults yet. */
1250 do_interrupt_all(env, env->exception_index,
1251 env->exception_is_int,
1252 env->error_code,
1253 env->exception_next_eip, 0);
1254 /* successfully delivered */
1255 env->old_exception = -1;
1256 #endif
1257 }
1258
1259 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw)
1260 {
1261 do_interrupt_all(env, intno, 0, 0, 0, is_hw);
1262 }
1263
1264 void helper_enter_level(CPUX86State *env, int level, int data32,
1265 target_ulong t1)
1266 {
1267 target_ulong ssp;
1268 uint32_t esp_mask, esp, ebp;
1269
1270 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1271 ssp = env->segs[R_SS].base;
1272 ebp = EBP;
1273 esp = ESP;
1274 if (data32) {
1275 /* 32 bit */
1276 esp -= 4;
1277 while (--level) {
1278 esp -= 4;
1279 ebp -= 4;
1280 cpu_stl_data(env, ssp + (esp & esp_mask),
1281 cpu_ldl_data(env, ssp + (ebp & esp_mask)));
1282 }
1283 esp -= 4;
1284 cpu_stl_data(env, ssp + (esp & esp_mask), t1);
1285 } else {
1286 /* 16 bit */
1287 esp -= 2;
1288 while (--level) {
1289 esp -= 2;
1290 ebp -= 2;
1291 cpu_stw_data(env, ssp + (esp & esp_mask),
1292 cpu_lduw_data(env, ssp + (ebp & esp_mask)));
1293 }
1294 esp -= 2;
1295 cpu_stw_data(env, ssp + (esp & esp_mask), t1);
1296 }
1297 }
1298
1299 #ifdef TARGET_X86_64
1300 void helper_enter64_level(CPUX86State *env, int level, int data64,
1301 target_ulong t1)
1302 {
1303 target_ulong esp, ebp;
1304
1305 ebp = EBP;
1306 esp = ESP;
1307
1308 if (data64) {
1309 /* 64 bit */
1310 esp -= 8;
1311 while (--level) {
1312 esp -= 8;
1313 ebp -= 8;
1314 cpu_stq_data(env, esp, cpu_ldq_data(env, ebp));
1315 }
1316 esp -= 8;
1317 cpu_stq_data(env, esp, t1);
1318 } else {
1319 /* 16 bit */
1320 esp -= 2;
1321 while (--level) {
1322 esp -= 2;
1323 ebp -= 2;
1324 cpu_stw_data(env, esp, cpu_lduw_data(env, ebp));
1325 }
1326 esp -= 2;
1327 cpu_stw_data(env, esp, t1);
1328 }
1329 }
1330 #endif
1331
1332 void helper_lldt(CPUX86State *env, int selector)
1333 {
1334 SegmentCache *dt;
1335 uint32_t e1, e2;
1336 int index, entry_limit;
1337 target_ulong ptr;
1338
1339 selector &= 0xffff;
1340 if ((selector & 0xfffc) == 0) {
1341 /* XXX: NULL selector case: invalid LDT */
1342 env->ldt.base = 0;
1343 env->ldt.limit = 0;
1344 } else {
1345 if (selector & 0x4) {
1346 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1347 }
1348 dt = &env->gdt;
1349 index = selector & ~7;
1350 #ifdef TARGET_X86_64
1351 if (env->hflags & HF_LMA_MASK) {
1352 entry_limit = 15;
1353 } else
1354 #endif
1355 {
1356 entry_limit = 7;
1357 }
1358 if ((index + entry_limit) > dt->limit) {
1359 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1360 }
1361 ptr = dt->base + index;
1362 e1 = cpu_ldl_kernel(env, ptr);
1363 e2 = cpu_ldl_kernel(env, ptr + 4);
1364 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
1365 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1366 }
1367 if (!(e2 & DESC_P_MASK)) {
1368 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1369 }
1370 #ifdef TARGET_X86_64
1371 if (env->hflags & HF_LMA_MASK) {
1372 uint32_t e3;
1373
1374 e3 = cpu_ldl_kernel(env, ptr + 8);
1375 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1376 env->ldt.base |= (target_ulong)e3 << 32;
1377 } else
1378 #endif
1379 {
1380 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1381 }
1382 }
1383 env->ldt.selector = selector;
1384 }
1385
1386 void helper_ltr(CPUX86State *env, int selector)
1387 {
1388 SegmentCache *dt;
1389 uint32_t e1, e2;
1390 int index, type, entry_limit;
1391 target_ulong ptr;
1392
1393 selector &= 0xffff;
1394 if ((selector & 0xfffc) == 0) {
1395 /* NULL selector case: invalid TR */
1396 env->tr.base = 0;
1397 env->tr.limit = 0;
1398 env->tr.flags = 0;
1399 } else {
1400 if (selector & 0x4) {
1401 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1402 }
1403 dt = &env->gdt;
1404 index = selector & ~7;
1405 #ifdef TARGET_X86_64
1406 if (env->hflags & HF_LMA_MASK) {
1407 entry_limit = 15;
1408 } else
1409 #endif
1410 {
1411 entry_limit = 7;
1412 }
1413 if ((index + entry_limit) > dt->limit) {
1414 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1415 }
1416 ptr = dt->base + index;
1417 e1 = cpu_ldl_kernel(env, ptr);
1418 e2 = cpu_ldl_kernel(env, ptr + 4);
1419 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1420 if ((e2 & DESC_S_MASK) ||
1421 (type != 1 && type != 9)) {
1422 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1423 }
1424 if (!(e2 & DESC_P_MASK)) {
1425 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1426 }
1427 #ifdef TARGET_X86_64
1428 if (env->hflags & HF_LMA_MASK) {
1429 uint32_t e3, e4;
1430
1431 e3 = cpu_ldl_kernel(env, ptr + 8);
1432 e4 = cpu_ldl_kernel(env, ptr + 12);
1433 if ((e4 >> DESC_TYPE_SHIFT) & 0xf) {
1434 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1435 }
1436 load_seg_cache_raw_dt(&env->tr, e1, e2);
1437 env->tr.base |= (target_ulong)e3 << 32;
1438 } else
1439 #endif
1440 {
1441 load_seg_cache_raw_dt(&env->tr, e1, e2);
1442 }
1443 e2 |= DESC_TSS_BUSY_MASK;
1444 cpu_stl_kernel(env, ptr + 4, e2);
1445 }
1446 env->tr.selector = selector;
1447 }
1448
1449 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
1450 void helper_load_seg(CPUX86State *env, int seg_reg, int selector)
1451 {
1452 uint32_t e1, e2;
1453 int cpl, dpl, rpl;
1454 SegmentCache *dt;
1455 int index;
1456 target_ulong ptr;
1457
1458 selector &= 0xffff;
1459 cpl = env->hflags & HF_CPL_MASK;
1460 if ((selector & 0xfffc) == 0) {
1461 /* null selector case */
1462 if (seg_reg == R_SS
1463 #ifdef TARGET_X86_64
1464 && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
1465 #endif
1466 ) {
1467 raise_exception_err(env, EXCP0D_GPF, 0);
1468 }
1469 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
1470 } else {
1471
1472 if (selector & 0x4) {
1473 dt = &env->ldt;
1474 } else {
1475 dt = &env->gdt;
1476 }
1477 index = selector & ~7;
1478 if ((index + 7) > dt->limit) {
1479 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1480 }
1481 ptr = dt->base + index;
1482 e1 = cpu_ldl_kernel(env, ptr);
1483 e2 = cpu_ldl_kernel(env, ptr + 4);
1484
1485 if (!(e2 & DESC_S_MASK)) {
1486 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1487 }
1488 rpl = selector & 3;
1489 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1490 if (seg_reg == R_SS) {
1491 /* must be writable segment */
1492 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
1493 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1494 }
1495 if (rpl != cpl || dpl != cpl) {
1496 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1497 }
1498 } else {
1499 /* must be readable segment */
1500 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK) {
1501 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1502 }
1503
1504 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1505 /* if not conforming code, test rights */
1506 if (dpl < cpl || dpl < rpl) {
1507 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1508 }
1509 }
1510 }
1511
1512 if (!(e2 & DESC_P_MASK)) {
1513 if (seg_reg == R_SS) {
1514 raise_exception_err(env, EXCP0C_STACK, selector & 0xfffc);
1515 } else {
1516 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1517 }
1518 }
1519
1520 /* set the access bit if not already set */
1521 if (!(e2 & DESC_A_MASK)) {
1522 e2 |= DESC_A_MASK;
1523 cpu_stl_kernel(env, ptr + 4, e2);
1524 }
1525
1526 cpu_x86_load_seg_cache(env, seg_reg, selector,
1527 get_seg_base(e1, e2),
1528 get_seg_limit(e1, e2),
1529 e2);
1530 #if 0
1531 qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1532 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1533 #endif
1534 }
1535 }
1536
1537 /* protected mode jump */
1538 void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
1539 int next_eip_addend)
1540 {
1541 int gate_cs, type;
1542 uint32_t e1, e2, cpl, dpl, rpl, limit;
1543 target_ulong next_eip;
1544
1545 if ((new_cs & 0xfffc) == 0) {
1546 raise_exception_err(env, EXCP0D_GPF, 0);
1547 }
1548 if (load_segment(env, &e1, &e2, new_cs) != 0) {
1549 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1550 }
1551 cpl = env->hflags & HF_CPL_MASK;
1552 if (e2 & DESC_S_MASK) {
1553 if (!(e2 & DESC_CS_MASK)) {
1554 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1555 }
1556 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1557 if (e2 & DESC_C_MASK) {
1558 /* conforming code segment */
1559 if (dpl > cpl) {
1560 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1561 }
1562 } else {
1563 /* non conforming code segment */
1564 rpl = new_cs & 3;
1565 if (rpl > cpl) {
1566 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1567 }
1568 if (dpl != cpl) {
1569 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1570 }
1571 }
1572 if (!(e2 & DESC_P_MASK)) {
1573 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1574 }
1575 limit = get_seg_limit(e1, e2);
1576 if (new_eip > limit &&
1577 !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK)) {
1578 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1579 }
1580 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1581 get_seg_base(e1, e2), limit, e2);
1582 EIP = new_eip;
1583 } else {
1584 /* jump to call or task gate */
1585 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1586 rpl = new_cs & 3;
1587 cpl = env->hflags & HF_CPL_MASK;
1588 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1589 switch (type) {
1590 case 1: /* 286 TSS */
1591 case 9: /* 386 TSS */
1592 case 5: /* task gate */
1593 if (dpl < cpl || dpl < rpl) {
1594 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1595 }
1596 next_eip = env->eip + next_eip_addend;
1597 switch_tss(env, new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
1598 CC_OP = CC_OP_EFLAGS;
1599 break;
1600 case 4: /* 286 call gate */
1601 case 12: /* 386 call gate */
1602 if ((dpl < cpl) || (dpl < rpl)) {
1603 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1604 }
1605 if (!(e2 & DESC_P_MASK)) {
1606 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1607 }
1608 gate_cs = e1 >> 16;
1609 new_eip = (e1 & 0xffff);
1610 if (type == 12) {
1611 new_eip |= (e2 & 0xffff0000);
1612 }
1613 if (load_segment(env, &e1, &e2, gate_cs) != 0) {
1614 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1615 }
1616 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1617 /* must be code segment */
1618 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
1619 (DESC_S_MASK | DESC_CS_MASK))) {
1620 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1621 }
1622 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
1623 (!(e2 & DESC_C_MASK) && (dpl != cpl))) {
1624 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1625 }
1626 if (!(e2 & DESC_P_MASK)) {
1627 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1628 }
1629 limit = get_seg_limit(e1, e2);
1630 if (new_eip > limit) {
1631 raise_exception_err(env, EXCP0D_GPF, 0);
1632 }
1633 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
1634 get_seg_base(e1, e2), limit, e2);
1635 EIP = new_eip;
1636 break;
1637 default:
1638 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1639 break;
1640 }
1641 }
1642 }
1643
1644 /* real mode call */
1645 void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1,
1646 int shift, int next_eip)
1647 {
1648 int new_eip;
1649 uint32_t esp, esp_mask;
1650 target_ulong ssp;
1651
1652 new_eip = new_eip1;
1653 esp = ESP;
1654 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1655 ssp = env->segs[R_SS].base;
1656 if (shift) {
1657 PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
1658 PUSHL(ssp, esp, esp_mask, next_eip);
1659 } else {
1660 PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
1661 PUSHW(ssp, esp, esp_mask, next_eip);
1662 }
1663
1664 SET_ESP(esp, esp_mask);
1665 env->eip = new_eip;
1666 env->segs[R_CS].selector = new_cs;
1667 env->segs[R_CS].base = (new_cs << 4);
1668 }
1669
1670 /* protected mode call */
1671 void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
1672 int shift, int next_eip_addend)
1673 {
1674 int new_stack, i;
1675 uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
1676 uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, sp, type, ss_dpl, sp_mask;
1677 uint32_t val, limit, old_sp_mask;
1678 target_ulong ssp, old_ssp, next_eip;
1679
1680 next_eip = env->eip + next_eip_addend;
1681 LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
1682 LOG_PCALL_STATE(env);
1683 if ((new_cs & 0xfffc) == 0) {
1684 raise_exception_err(env, EXCP0D_GPF, 0);
1685 }
1686 if (load_segment(env, &e1, &e2, new_cs) != 0) {
1687 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1688 }
1689 cpl = env->hflags & HF_CPL_MASK;
1690 LOG_PCALL("desc=%08x:%08x\n", e1, e2);
1691 if (e2 & DESC_S_MASK) {
1692 if (!(e2 & DESC_CS_MASK)) {
1693 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1694 }
1695 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1696 if (e2 & DESC_C_MASK) {
1697 /* conforming code segment */
1698 if (dpl > cpl) {
1699 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1700 }
1701 } else {
1702 /* non conforming code segment */
1703 rpl = new_cs & 3;
1704 if (rpl > cpl) {
1705 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1706 }
1707 if (dpl != cpl) {
1708 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1709 }
1710 }
1711 if (!(e2 & DESC_P_MASK)) {
1712 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1713 }
1714
1715 #ifdef TARGET_X86_64
1716 /* XXX: check 16/32 bit cases in long mode */
1717 if (shift == 2) {
1718 target_ulong rsp;
1719
1720 /* 64 bit case */
1721 rsp = ESP;
1722 PUSHQ(rsp, env->segs[R_CS].selector);
1723 PUSHQ(rsp, next_eip);
1724 /* from this point, not restartable */
1725 ESP = rsp;
1726 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1727 get_seg_base(e1, e2),
1728 get_seg_limit(e1, e2), e2);
1729 EIP = new_eip;
1730 } else
1731 #endif
1732 {
1733 sp = ESP;
1734 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1735 ssp = env->segs[R_SS].base;
1736 if (shift) {
1737 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1738 PUSHL(ssp, sp, sp_mask, next_eip);
1739 } else {
1740 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1741 PUSHW(ssp, sp, sp_mask, next_eip);
1742 }
1743
1744 limit = get_seg_limit(e1, e2);
1745 if (new_eip > limit) {
1746 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1747 }
1748 /* from this point, not restartable */
1749 SET_ESP(sp, sp_mask);
1750 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1751 get_seg_base(e1, e2), limit, e2);
1752 EIP = new_eip;
1753 }
1754 } else {
1755 /* check gate type */
1756 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1757 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1758 rpl = new_cs & 3;
1759 switch (type) {
1760 case 1: /* available 286 TSS */
1761 case 9: /* available 386 TSS */
1762 case 5: /* task gate */
1763 if (dpl < cpl || dpl < rpl) {
1764 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1765 }
1766 switch_tss(env, new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
1767 CC_OP = CC_OP_EFLAGS;
1768 return;
1769 case 4: /* 286 call gate */
1770 case 12: /* 386 call gate */
1771 break;
1772 default:
1773 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1774 break;
1775 }
1776 shift = type >> 3;
1777
1778 if (dpl < cpl || dpl < rpl) {
1779 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1780 }
1781 /* check valid bit */
1782 if (!(e2 & DESC_P_MASK)) {
1783 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1784 }
1785 selector = e1 >> 16;
1786 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
1787 param_count = e2 & 0x1f;
1788 if ((selector & 0xfffc) == 0) {
1789 raise_exception_err(env, EXCP0D_GPF, 0);
1790 }
1791
1792 if (load_segment(env, &e1, &e2, selector) != 0) {
1793 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1794 }
1795 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
1796 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1797 }
1798 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1799 if (dpl > cpl) {
1800 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1801 }
1802 if (!(e2 & DESC_P_MASK)) {
1803 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1804 }
1805
1806 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
1807 /* to inner privilege */
1808 get_ss_esp_from_tss(env, &ss, &sp, dpl);
1809 LOG_PCALL("new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx
1810 "\n",
1811 ss, sp, param_count, ESP);
1812 if ((ss & 0xfffc) == 0) {
1813 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1814 }
1815 if ((ss & 3) != dpl) {
1816 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1817 }
1818 if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) {
1819 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1820 }
1821 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
1822 if (ss_dpl != dpl) {
1823 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1824 }
1825 if (!(ss_e2 & DESC_S_MASK) ||
1826 (ss_e2 & DESC_CS_MASK) ||
1827 !(ss_e2 & DESC_W_MASK)) {
1828 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1829 }
1830 if (!(ss_e2 & DESC_P_MASK)) {
1831 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1832 }
1833
1834 /* push_size = ((param_count * 2) + 8) << shift; */
1835
1836 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
1837 old_ssp = env->segs[R_SS].base;
1838
1839 sp_mask = get_sp_mask(ss_e2);
1840 ssp = get_seg_base(ss_e1, ss_e2);
1841 if (shift) {
1842 PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
1843 PUSHL(ssp, sp, sp_mask, ESP);
1844 for (i = param_count - 1; i >= 0; i--) {
1845 val = cpu_ldl_kernel(env, old_ssp + ((ESP + i * 4) &
1846 old_sp_mask));
1847 PUSHL(ssp, sp, sp_mask, val);
1848 }
1849 } else {
1850 PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
1851 PUSHW(ssp, sp, sp_mask, ESP);
1852 for (i = param_count - 1; i >= 0; i--) {
1853 val = cpu_lduw_kernel(env, old_ssp + ((ESP + i * 2) &
1854 old_sp_mask));
1855 PUSHW(ssp, sp, sp_mask, val);
1856 }
1857 }
1858 new_stack = 1;
1859 } else {
1860 /* to same privilege */
1861 sp = ESP;
1862 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1863 ssp = env->segs[R_SS].base;
1864 /* push_size = (4 << shift); */
1865 new_stack = 0;
1866 }
1867
1868 if (shift) {
1869 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1870 PUSHL(ssp, sp, sp_mask, next_eip);
1871 } else {
1872 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1873 PUSHW(ssp, sp, sp_mask, next_eip);
1874 }
1875
1876 /* from this point, not restartable */
1877
1878 if (new_stack) {
1879 ss = (ss & ~3) | dpl;
1880 cpu_x86_load_seg_cache(env, R_SS, ss,
1881 ssp,
1882 get_seg_limit(ss_e1, ss_e2),
1883 ss_e2);
1884 }
1885
1886 selector = (selector & ~3) | dpl;
1887 cpu_x86_load_seg_cache(env, R_CS, selector,
1888 get_seg_base(e1, e2),
1889 get_seg_limit(e1, e2),
1890 e2);
1891 cpu_x86_set_cpl(env, dpl);
1892 SET_ESP(sp, sp_mask);
1893 EIP = offset;
1894 }
1895 }
1896
1897 /* real and vm86 mode iret */
1898 void helper_iret_real(CPUX86State *env, int shift)
1899 {
1900 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
1901 target_ulong ssp;
1902 int eflags_mask;
1903
1904 sp_mask = 0xffff; /* XXXX: use SS segment size? */
1905 sp = ESP;
1906 ssp = env->segs[R_SS].base;
1907 if (shift == 1) {
1908 /* 32 bits */
1909 POPL(ssp, sp, sp_mask, new_eip);
1910 POPL(ssp, sp, sp_mask, new_cs);
1911 new_cs &= 0xffff;
1912 POPL(ssp, sp, sp_mask, new_eflags);
1913 } else {
1914 /* 16 bits */
1915 POPW(ssp, sp, sp_mask, new_eip);
1916 POPW(ssp, sp, sp_mask, new_cs);
1917 POPW(ssp, sp, sp_mask, new_eflags);
1918 }
1919 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
1920 env->segs[R_CS].selector = new_cs;
1921 env->segs[R_CS].base = (new_cs << 4);
1922 env->eip = new_eip;
1923 if (env->eflags & VM_MASK) {
1924 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK |
1925 NT_MASK;
1926 } else {
1927 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK |
1928 RF_MASK | NT_MASK;
1929 }
1930 if (shift == 0) {
1931 eflags_mask &= 0xffff;
1932 }
1933 cpu_load_eflags(env, new_eflags, eflags_mask);
1934 env->hflags2 &= ~HF2_NMI_MASK;
1935 }
1936
1937 static inline void validate_seg(CPUX86State *env, int seg_reg, int cpl)
1938 {
1939 int dpl;
1940 uint32_t e2;
1941
1942 /* XXX: on x86_64, we do not want to nullify FS and GS because
1943 they may still contain a valid base. I would be interested to
1944 know how a real x86_64 CPU behaves */
1945 if ((seg_reg == R_FS || seg_reg == R_GS) &&
1946 (env->segs[seg_reg].selector & 0xfffc) == 0) {
1947 return;
1948 }
1949
1950 e2 = env->segs[seg_reg].flags;
1951 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1952 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1953 /* data or non conforming code segment */
1954 if (dpl < cpl) {
1955 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
1956 }
1957 }
1958 }
1959
1960 /* protected mode iret */
1961 static inline void helper_ret_protected(CPUX86State *env, int shift,
1962 int is_iret, int addend)
1963 {
1964 uint32_t new_cs, new_eflags, new_ss;
1965 uint32_t new_es, new_ds, new_fs, new_gs;
1966 uint32_t e1, e2, ss_e1, ss_e2;
1967 int cpl, dpl, rpl, eflags_mask, iopl;
1968 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
1969
1970 #ifdef TARGET_X86_64
1971 if (shift == 2) {
1972 sp_mask = -1;
1973 } else
1974 #endif
1975 {
1976 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1977 }
1978 sp = ESP;
1979 ssp = env->segs[R_SS].base;
1980 new_eflags = 0; /* avoid warning */
1981 #ifdef TARGET_X86_64
1982 if (shift == 2) {
1983 POPQ(sp, new_eip);
1984 POPQ(sp, new_cs);
1985 new_cs &= 0xffff;
1986 if (is_iret) {
1987 POPQ(sp, new_eflags);
1988 }
1989 } else
1990 #endif
1991 {
1992 if (shift == 1) {
1993 /* 32 bits */
1994 POPL(ssp, sp, sp_mask, new_eip);
1995 POPL(ssp, sp, sp_mask, new_cs);
1996 new_cs &= 0xffff;
1997 if (is_iret) {
1998 POPL(ssp, sp, sp_mask, new_eflags);
1999 if (new_eflags & VM_MASK) {
2000 goto return_to_vm86;
2001 }
2002 }
2003 } else {
2004 /* 16 bits */
2005 POPW(ssp, sp, sp_mask, new_eip);
2006 POPW(ssp, sp, sp_mask, new_cs);
2007 if (is_iret) {
2008 POPW(ssp, sp, sp_mask, new_eflags);
2009 }
2010 }
2011 }
2012 LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2013 new_cs, new_eip, shift, addend);
2014 LOG_PCALL_STATE(env);
2015 if ((new_cs & 0xfffc) == 0) {
2016 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2017 }
2018 if (load_segment(env, &e1, &e2, new_cs) != 0) {
2019 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2020 }
2021 if (!(e2 & DESC_S_MASK) ||
2022 !(e2 & DESC_CS_MASK)) {
2023 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2024 }
2025 cpl = env->hflags & HF_CPL_MASK;
2026 rpl = new_cs & 3;
2027 if (rpl < cpl) {
2028 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2029 }
2030 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2031 if (e2 & DESC_C_MASK) {
2032 if (dpl > rpl) {
2033 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2034 }
2035 } else {
2036 if (dpl != rpl) {
2037 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2038 }
2039 }
2040 if (!(e2 & DESC_P_MASK)) {
2041 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
2042 }
2043
2044 sp += addend;
2045 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
2046 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
2047 /* return to same privilege level */
2048 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2049 get_seg_base(e1, e2),
2050 get_seg_limit(e1, e2),
2051 e2);
2052 } else {
2053 /* return to different privilege level */
2054 #ifdef TARGET_X86_64
2055 if (shift == 2) {
2056 POPQ(sp, new_esp);
2057 POPQ(sp, new_ss);
2058 new_ss &= 0xffff;
2059 } else
2060 #endif
2061 {
2062 if (shift == 1) {
2063 /* 32 bits */
2064 POPL(ssp, sp, sp_mask, new_esp);
2065 POPL(ssp, sp, sp_mask, new_ss);
2066 new_ss &= 0xffff;
2067 } else {
2068 /* 16 bits */
2069 POPW(ssp, sp, sp_mask, new_esp);
2070 POPW(ssp, sp, sp_mask, new_ss);
2071 }
2072 }
2073 LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n",
2074 new_ss, new_esp);
2075 if ((new_ss & 0xfffc) == 0) {
2076 #ifdef TARGET_X86_64
2077 /* NULL ss is allowed in long mode if cpl != 3 */
2078 /* XXX: test CS64? */
2079 if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2080 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2081 0, 0xffffffff,
2082 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2083 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
2084 DESC_W_MASK | DESC_A_MASK);
2085 ss_e2 = DESC_B_MASK; /* XXX: should not be needed? */
2086 } else
2087 #endif
2088 {
2089 raise_exception_err(env, EXCP0D_GPF, 0);
2090 }
2091 } else {
2092 if ((new_ss & 3) != rpl) {
2093 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2094 }
2095 if (load_segment(env, &ss_e1, &ss_e2, new_ss) != 0) {
2096 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2097 }
2098 if (!(ss_e2 & DESC_S_MASK) ||
2099 (ss_e2 & DESC_CS_MASK) ||
2100 !(ss_e2 & DESC_W_MASK)) {
2101 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2102 }
2103 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2104 if (dpl != rpl) {
2105 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2106 }
2107 if (!(ss_e2 & DESC_P_MASK)) {
2108 raise_exception_err(env, EXCP0B_NOSEG, new_ss & 0xfffc);
2109 }
2110 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2111 get_seg_base(ss_e1, ss_e2),
2112 get_seg_limit(ss_e1, ss_e2),
2113 ss_e2);
2114 }
2115
2116 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2117 get_seg_base(e1, e2),
2118 get_seg_limit(e1, e2),
2119 e2);
2120 cpu_x86_set_cpl(env, rpl);
2121 sp = new_esp;
2122 #ifdef TARGET_X86_64
2123 if (env->hflags & HF_CS64_MASK) {
2124 sp_mask = -1;
2125 } else
2126 #endif
2127 {
2128 sp_mask = get_sp_mask(ss_e2);
2129 }
2130
2131 /* validate data segments */
2132 validate_seg(env, R_ES, rpl);
2133 validate_seg(env, R_DS, rpl);
2134 validate_seg(env, R_FS, rpl);
2135 validate_seg(env, R_GS, rpl);
2136
2137 sp += addend;
2138 }
2139 SET_ESP(sp, sp_mask);
2140 env->eip = new_eip;
2141 if (is_iret) {
2142 /* NOTE: 'cpl' is the _old_ CPL */
2143 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
2144 if (cpl == 0) {
2145 eflags_mask |= IOPL_MASK;
2146 }
2147 iopl = (env->eflags >> IOPL_SHIFT) & 3;
2148 if (cpl <= iopl) {
2149 eflags_mask |= IF_MASK;
2150 }
2151 if (shift == 0) {
2152 eflags_mask &= 0xffff;
2153 }
2154 cpu_load_eflags(env, new_eflags, eflags_mask);
2155 }
2156 return;
2157
2158 return_to_vm86:
2159 POPL(ssp, sp, sp_mask, new_esp);
2160 POPL(ssp, sp, sp_mask, new_ss);
2161 POPL(ssp, sp, sp_mask, new_es);
2162 POPL(ssp, sp, sp_mask, new_ds);
2163 POPL(ssp, sp, sp_mask, new_fs);
2164 POPL(ssp, sp, sp_mask, new_gs);
2165
2166 /* modify processor state */
2167 cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK |
2168 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK |
2169 VIP_MASK);
2170 load_seg_vm(env, R_CS, new_cs & 0xffff);
2171 cpu_x86_set_cpl(env, 3);
2172 load_seg_vm(env, R_SS, new_ss & 0xffff);
2173 load_seg_vm(env, R_ES, new_es & 0xffff);
2174 load_seg_vm(env, R_DS, new_ds & 0xffff);
2175 load_seg_vm(env, R_FS, new_fs & 0xffff);
2176 load_seg_vm(env, R_GS, new_gs & 0xffff);
2177
2178 env->eip = new_eip & 0xffff;
2179 ESP = new_esp;
2180 }
2181
2182 void helper_iret_protected(CPUX86State *env, int shift, int next_eip)
2183 {
2184 int tss_selector, type;
2185 uint32_t e1, e2;
2186
2187 /* specific case for TSS */
2188 if (env->eflags & NT_MASK) {
2189 #ifdef TARGET_X86_64
2190 if (env->hflags & HF_LMA_MASK) {
2191 raise_exception_err(env, EXCP0D_GPF, 0);
2192 }
2193 #endif
2194 tss_selector = cpu_lduw_kernel(env, env->tr.base + 0);
2195 if (tss_selector & 4) {
2196 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
2197 }
2198 if (load_segment(env, &e1, &e2, tss_selector) != 0) {
2199 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
2200 }
2201 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2202 /* NOTE: we check both segment and busy TSS */
2203 if (type != 3) {
2204 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
2205 }
2206 switch_tss(env, tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2207 } else {
2208 helper_ret_protected(env, shift, 1, 0);
2209 }
2210 env->hflags2 &= ~HF2_NMI_MASK;
2211 }
2212
2213 void helper_lret_protected(CPUX86State *env, int shift, int addend)
2214 {
2215 helper_ret_protected(env, shift, 0, addend);
2216 }
2217
2218 void helper_sysenter(CPUX86State *env)
2219 {
2220 if (env->sysenter_cs == 0) {
2221 raise_exception_err(env, EXCP0D_GPF, 0);
2222 }
2223 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
2224 cpu_x86_set_cpl(env, 0);
2225
2226 #ifdef TARGET_X86_64
2227 if (env->hflags & HF_LMA_MASK) {
2228 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2229 0, 0xffffffff,
2230 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2231 DESC_S_MASK |
2232 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2233 DESC_L_MASK);
2234 } else
2235 #endif
2236 {
2237 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2238 0, 0xffffffff,
2239 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2240 DESC_S_MASK |
2241 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2242 }
2243 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2244 0, 0xffffffff,
2245 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2246 DESC_S_MASK |
2247 DESC_W_MASK | DESC_A_MASK);
2248 ESP = env->sysenter_esp;
2249 EIP = env->sysenter_eip;
2250 }
2251
2252 void helper_sysexit(CPUX86State *env, int dflag)
2253 {
2254 int cpl;
2255
2256 cpl = env->hflags & HF_CPL_MASK;
2257 if (env->sysenter_cs == 0 || cpl != 0) {
2258 raise_exception_err(env, EXCP0D_GPF, 0);
2259 }
2260 cpu_x86_set_cpl(env, 3);
2261 #ifdef TARGET_X86_64
2262 if (dflag == 2) {
2263 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 32) & 0xfffc) |
2264 3, 0, 0xffffffff,
2265 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2266 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2267 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2268 DESC_L_MASK);
2269 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 40) & 0xfffc) |
2270 3, 0, 0xffffffff,
2271 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2272 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2273 DESC_W_MASK | DESC_A_MASK);
2274 } else
2275 #endif
2276 {
2277 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) |
2278 3, 0, 0xffffffff,
2279 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2280 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2281 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2282 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) |
2283 3, 0, 0xffffffff,
2284 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2285 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2286 DESC_W_MASK | DESC_A_MASK);
2287 }
2288 ESP = ECX;
2289 EIP = EDX;
2290 }
2291
2292 target_ulong helper_lsl(CPUX86State *env, target_ulong selector1)
2293 {
2294 unsigned int limit;
2295 uint32_t e1, e2, eflags, selector;
2296 int rpl, dpl, cpl, type;
2297
2298 selector = selector1 & 0xffff;
2299 eflags = cpu_cc_compute_all(env, CC_OP);
2300 if ((selector & 0xfffc) == 0) {
2301 goto fail;
2302 }
2303 if (load_segment(env, &e1, &e2, selector) != 0) {
2304 goto fail;
2305 }
2306 rpl = selector & 3;
2307 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2308 cpl = env->hflags & HF_CPL_MASK;
2309 if (e2 & DESC_S_MASK) {
2310 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2311 /* conforming */
2312 } else {
2313 if (dpl < cpl || dpl < rpl) {
2314 goto fail;
2315 }
2316 }
2317 } else {
2318 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2319 switch (type) {
2320 case 1:
2321 case 2:
2322 case 3:
2323 case 9:
2324 case 11:
2325 break;
2326 default:
2327 goto fail;
2328 }
2329 if (dpl < cpl || dpl < rpl) {
2330 fail:
2331 CC_SRC = eflags & ~CC_Z;
2332 return 0;
2333 }
2334 }
2335 limit = get_seg_limit(e1, e2);
2336 CC_SRC = eflags | CC_Z;
2337 return limit;
2338 }
2339
2340 target_ulong helper_lar(CPUX86State *env, target_ulong selector1)
2341 {
2342 uint32_t e1, e2, eflags, selector;
2343 int rpl, dpl, cpl, type;
2344
2345 selector = selector1 & 0xffff;
2346 eflags = cpu_cc_compute_all(env, CC_OP);
2347 if ((selector & 0xfffc) == 0) {
2348 goto fail;
2349 }
2350 if (load_segment(env, &e1, &e2, selector) != 0) {
2351 goto fail;
2352 }
2353 rpl = selector & 3;
2354 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2355 cpl = env->hflags & HF_CPL_MASK;
2356 if (e2 & DESC_S_MASK) {
2357 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2358 /* conforming */
2359 } else {
2360 if (dpl < cpl || dpl < rpl) {
2361 goto fail;
2362 }
2363 }
2364 } else {
2365 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2366 switch (type) {
2367 case 1:
2368 case 2:
2369 case 3:
2370 case 4:
2371 case 5:
2372 case 9:
2373 case 11:
2374 case 12:
2375 break;
2376 default:
2377 goto fail;
2378 }
2379 if (dpl < cpl || dpl < rpl) {
2380 fail:
2381 CC_SRC = eflags & ~CC_Z;
2382 return 0;
2383 }
2384 }
2385 CC_SRC = eflags | CC_Z;
2386 return e2 & 0x00f0ff00;
2387 }
2388
2389 void helper_verr(CPUX86State *env, target_ulong selector1)
2390 {
2391 uint32_t e1, e2, eflags, selector;
2392 int rpl, dpl, cpl;
2393
2394 selector = selector1 & 0xffff;
2395 eflags = cpu_cc_compute_all(env, CC_OP);
2396 if ((selector & 0xfffc) == 0) {
2397 goto fail;
2398 }
2399 if (load_segment(env, &e1, &e2, selector) != 0) {
2400 goto fail;
2401 }
2402 if (!(e2 & DESC_S_MASK)) {
2403 goto fail;
2404 }
2405 rpl = selector & 3;
2406 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2407 cpl = env->hflags & HF_CPL_MASK;
2408 if (e2 & DESC_CS_MASK) {
2409 if (!(e2 & DESC_R_MASK)) {
2410 goto fail;
2411 }
2412 if (!(e2 & DESC_C_MASK)) {
2413 if (dpl < cpl || dpl < rpl) {
2414 goto fail;
2415 }
2416 }
2417 } else {
2418 if (dpl < cpl || dpl < rpl) {
2419 fail:
2420 CC_SRC = eflags & ~CC_Z;
2421 return;
2422 }
2423 }
2424 CC_SRC = eflags | CC_Z;
2425 }
2426
2427 void helper_verw(CPUX86State *env, target_ulong selector1)
2428 {
2429 uint32_t e1, e2, eflags, selector;
2430 int rpl, dpl, cpl;
2431
2432 selector = selector1 & 0xffff;
2433 eflags = cpu_cc_compute_all(env, CC_OP);
2434 if ((selector & 0xfffc) == 0) {
2435 goto fail;
2436 }
2437 if (load_segment(env, &e1, &e2, selector) != 0) {
2438 goto fail;
2439 }
2440 if (!(e2 & DESC_S_MASK)) {
2441 goto fail;
2442 }
2443 rpl = selector & 3;
2444 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2445 cpl = env->hflags & HF_CPL_MASK;
2446 if (e2 & DESC_CS_MASK) {
2447 goto fail;
2448 } else {
2449 if (dpl < cpl || dpl < rpl) {
2450 goto fail;
2451 }
2452 if (!(e2 & DESC_W_MASK)) {
2453 fail:
2454 CC_SRC = eflags & ~CC_Z;
2455 return;
2456 }
2457 }
2458 CC_SRC = eflags | CC_Z;
2459 }
2460
2461 #if defined(CONFIG_USER_ONLY)
2462 void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector)
2463 {
2464 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
2465 selector &= 0xffff;
2466 cpu_x86_load_seg_cache(env, seg_reg, selector,
2467 (selector << 4), 0xffff, 0);
2468 } else {
2469 helper_load_seg(env, seg_reg, selector);
2470 }
2471 }
2472 #endif
Qemu copy for testing