/* output pin */
qemu_irq irl;
-} a_r2d_fpga;
+} r2d_fpga_t;
enum r2d_fpga_irq {
PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
[TP] = { 12, 1<<15 },
};
-static void update_irl(a_r2d_fpga *fpga)
+static void update_irl(r2d_fpga_t *fpga)
{
int i, irl = 15;
for (i = 0; i < NR_IRQS; i++)
static void r2d_fpga_irq_set(void *opaque, int n, int level)
{
- a_r2d_fpga *fpga = opaque;
+ r2d_fpga_t *fpga = opaque;
if (level)
fpga->irlmon |= irqtab[n].msk;
else
update_irl(fpga);
}
-static uint32_t r2d_fpga_read(void *opaque, a_target_phys_addr addr)
+static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
{
- a_r2d_fpga *s = opaque;
+ r2d_fpga_t *s = opaque;
switch (addr) {
case PA_IRLMSK:
}
static void
-r2d_fpga_write(void *opaque, a_target_phys_addr addr, uint32_t value)
+r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
{
- a_r2d_fpga *s = opaque;
+ r2d_fpga_t *s = opaque;
switch (addr) {
case PA_IRLMSK:
NULL,
};
-static qemu_irq *r2d_fpga_init(a_target_phys_addr base, qemu_irq irl)
+static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
{
int iomemtype;
- a_r2d_fpga *s;
+ r2d_fpga_t *s;
- s = qemu_mallocz(sizeof(a_r2d_fpga));
+ s = qemu_mallocz(sizeof(r2d_fpga_t));
s->irl = irl;
return intx[d->devfn >> 3];
}
-static void r2d_init(a_ram_addr ram_size,
+static void r2d_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
struct SH7750State *s;
- a_ram_addr sdram_addr;
+ ram_addr_t sdram_addr;
qemu_irq *irq;
PCIBus *pci;
DriveInfo *dinfo;