x86 Fabrice Bellard
ARM Paul Brook
SPARC Blue Swirl
-MIPS Thiemo Seufer
+MIPS ?
PowerPC ?
M68K Paul Brook
SH4 ?
mips_r4k.c Aurelien Jarno
mips_malta.c Aurelien Jarno
mips_jazz.c Hervé Poussineau
- mips_mipssim.c Thiemo Seufer
+ mips_mipssim.c ?
PowerPC
ppc_prep.c ?
ppc_oldworld.c Fabrice Bellard
# OldWorld PowerMac
obj-ppc-y += heathrow_pic.o grackle_pci.o ppc_oldworld.o
# NewWorld PowerMac
-obj-ppc-y += unin_pci.o ppc_newworld.o
+obj-ppc-y += unin_pci.o ppc_newworld.o dec_pci.o
# PowerPC 4xx boards
obj-ppc-y += pflash_cfi02.o ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
obj-ppc-y += ppc440.o ppc440_bamboo.o
//#define DEBUG_BLK_MIGRATION
#ifdef DEBUG_BLK_MIGRATION
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do { printf("blk_migration: " fmt, ## __VA_ARGS__); } while (0)
#else
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do { } while (0)
#endif
{
BlkMigBlock *blk;
- dprintf("%s Enter submitted %d read_done %d transferred %d\n",
+ DPRINTF("%s Enter submitted %d read_done %d transferred %d\n",
__FUNCTION__, block_mig_state.submitted, block_mig_state.read_done,
block_mig_state.transferred);
assert(block_mig_state.read_done >= 0);
}
- dprintf("%s Exit submitted %d read_done %d transferred %d\n", __FUNCTION__,
+ DPRINTF("%s Exit submitted %d read_done %d transferred %d\n", __FUNCTION__,
block_mig_state.submitted, block_mig_state.read_done,
block_mig_state.transferred);
}
static int block_save_live(Monitor *mon, QEMUFile *f, int stage, void *opaque)
{
- dprintf("Enter save live stage %d submitted %d transferred %d\n",
+ DPRINTF("Enter save live stage %d submitted %d transferred %d\n",
stage, block_mig_state.submitted, block_mig_state.transferred);
if (stage < 0) {
// #define DEBUG_VERBOSE
#ifdef DEBUG_CURL
-#define dprintf(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
+#define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
#else
-#define dprintf(fmt, ...) do { } while (0)
+#define DPRINTF(fmt, ...) do { } while (0)
#endif
#define CURL_NUM_STATES 8
static int curl_sock_cb(CURL *curl, curl_socket_t fd, int action,
void *s, void *sp)
{
- dprintf("CURL (AIO): Sock action %d on fd %d\n", action, fd);
+ DPRINTF("CURL (AIO): Sock action %d on fd %d\n", action, fd);
switch (action) {
case CURL_POLL_IN:
qemu_aio_set_fd_handler(fd, curl_multi_do, NULL, NULL, NULL, s);
size_t realsize = size * nmemb;
int i;
- dprintf("CURL: Just reading %lld bytes\n", (unsigned long long)realsize);
+ DPRINTF("CURL: Just reading %lld bytes\n", (unsigned long long)realsize);
if (!s || !s->orig_buf)
goto read_end;
}
if ((s->readahead_size & 0x1ff) != 0) {
- fprintf(stderr, "HTTP_READAHEAD_SIZE %Zd is not a multiple of 512\n",
+ fprintf(stderr, "HTTP_READAHEAD_SIZE %zd is not a multiple of 512\n",
s->readahead_size);
goto out_noclean;
}
inited = 1;
}
- dprintf("CURL: Opening %s\n", file);
+ DPRINTF("CURL: Opening %s\n", file);
s->url = file;
state = curl_init_state(s);
if (!state)
s->len = (size_t)d;
else if(!s->len)
goto out;
- dprintf("CURL: Size = %lld\n", (long long)s->len);
+ DPRINTF("CURL: Size = %lld\n", (long long)s->len);
curl_clean_state(state);
curl_easy_cleanup(state->curl);
state->acb[0] = acb;
snprintf(state->range, 127, "%lld-%lld", (long long)start, (long long)end);
- dprintf("CURL (AIO): Reading %d at %lld (%s)\n", (nb_sectors * SECTOR_SIZE), start, state->range);
+ DPRINTF("CURL (AIO): Reading %d at %lld (%s)\n", (nb_sectors * SECTOR_SIZE), start, state->range);
curl_easy_setopt(state->curl, CURLOPT_RANGE, state->range);
curl_multi_add_handle(s->multi, state->curl);
BDRVCURLState *s = bs->opaque;
int i;
- dprintf("CURL: Close\n");
+ DPRINTF("CURL: Close\n");
for (i=0; i<CURL_NUM_STATES; i++) {
if (s->states[i].in_use)
curl_clean_state(&s->states[i]);
} QEMUFileBuffered;
#ifdef DEBUG_BUFFERED_FILE
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do { printf("buffered-file: " fmt, ## __VA_ARGS__); } while (0)
#else
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do { } while (0)
#endif
if (size > (s->buffer_capacity - s->buffer_size)) {
void *tmp;
- dprintf("increasing buffer capacity from %zu by %zu\n",
+ DPRINTF("increasing buffer capacity from %zu by %zu\n",
s->buffer_capacity, size + 1024);
s->buffer_capacity += size + 1024;
size_t offset = 0;
if (s->has_error) {
- dprintf("flush when error, bailing\n");
+ DPRINTF("flush when error, bailing\n");
return;
}
- dprintf("flushing %zu byte(s) of data\n", s->buffer_size);
+ DPRINTF("flushing %zu byte(s) of data\n", s->buffer_size);
while (offset < s->buffer_size) {
ssize_t ret;
ret = s->put_buffer(s->opaque, s->buffer + offset,
s->buffer_size - offset);
if (ret == -EAGAIN) {
- dprintf("backend not ready, freezing\n");
+ DPRINTF("backend not ready, freezing\n");
s->freeze_output = 1;
break;
}
if (ret <= 0) {
- dprintf("error flushing data, %zd\n", ret);
+ DPRINTF("error flushing data, %zd\n", ret);
s->has_error = 1;
break;
} else {
- dprintf("flushed %zd byte(s)\n", ret);
+ DPRINTF("flushed %zd byte(s)\n", ret);
offset += ret;
}
}
- dprintf("flushed %zu of %zu byte(s)\n", offset, s->buffer_size);
+ DPRINTF("flushed %zu of %zu byte(s)\n", offset, s->buffer_size);
memmove(s->buffer, s->buffer + offset, s->buffer_size - offset);
s->buffer_size -= offset;
}
int offset = 0;
ssize_t ret;
- dprintf("putting %d bytes at %" PRId64 "\n", size, pos);
+ DPRINTF("putting %d bytes at %" PRId64 "\n", size, pos);
if (s->has_error) {
- dprintf("flush when error, bailing\n");
+ DPRINTF("flush when error, bailing\n");
return -EINVAL;
}
- dprintf("unfreezing output\n");
+ DPRINTF("unfreezing output\n");
s->freeze_output = 0;
buffered_flush(s);
while (!s->freeze_output && offset < size) {
if (s->bytes_xfer > s->xfer_limit) {
- dprintf("transfer limit exceeded when putting\n");
+ DPRINTF("transfer limit exceeded when putting\n");
break;
}
ret = s->put_buffer(s->opaque, buf + offset, size - offset);
if (ret == -EAGAIN) {
- dprintf("backend not ready, freezing\n");
+ DPRINTF("backend not ready, freezing\n");
s->freeze_output = 1;
break;
}
if (ret <= 0) {
- dprintf("error putting\n");
+ DPRINTF("error putting\n");
s->has_error = 1;
offset = -EINVAL;
break;
}
- dprintf("put %zd byte(s)\n", ret);
+ DPRINTF("put %zd byte(s)\n", ret);
offset += ret;
s->bytes_xfer += ret;
}
if (offset >= 0) {
- dprintf("buffering %d bytes\n", size - offset);
+ DPRINTF("buffering %d bytes\n", size - offset);
buffered_append(s, buf + offset, size - offset);
offset = size;
}
QEMUFileBuffered *s = opaque;
int ret;
- dprintf("closing\n");
+ DPRINTF("closing\n");
while (!s->has_error && s->buffer_size) {
buffered_flush(s);
gcc_flags="-Wold-style-declaration -Wold-style-definition -fstack-protector-all"
cat > $TMPC << EOF
-int main(void) { }
+int main(void) { return 0; }
EOF
for flag in $gcc_flags; do
- if compile_prog "$QEMU_CFLAGS" "$flag" ; then
+ if compile_prog "-Werror $QEMU_CFLAGS" "-Werror $flag" ; then
QEMU_CFLAGS="$flag $QEMU_CFLAGS"
fi
done
;;
--enable-gprof) gprof="yes"
;;
- --static) static="yes"
+ --static)
+ static="yes"
+ LDFLAGS="-static $LDFLAGS"
;;
--sysconfdir) sysconfdir="$optarg"
;;
echo " --enable-io-thread enable IO thread"
echo " --disable-blobs disable installing provided firmware blobs"
echo " --kerneldir=PATH look for kernel includes in PATH"
+echo " --enable-docs enable documentation build"
+echo " --disable-docs disable documentation build"
echo ""
echo "NOTE: The object files are built at the place where configure is launched"
exit 1
int main( void ) { return SDL_Init (SDL_INIT_VIDEO); }
EOF
sdl_cflags=`$sdlconfig --cflags 2> /dev/null`
- sdl_libs=`$sdlconfig --libs 2> /dev/null`
+ if test "$static" = "yes" ; then
+ sdl_libs=`$sdlconfig --static-libs 2>/dev/null`
+ else
+ sdl_libs=`$sdlconfig --libs 2> /dev/null`
+ fi
if compile_prog "$sdl_cflags" "$sdl_libs" ; then
if test "$_sdlversion" -lt 121 ; then
sdl_too_old=yes
# static link with sdl ? (note: sdl.pc's --static --libs is broken)
if test "$sdl" = "yes" -a "$static" = "yes" ; then
- sdl_libs=`sdl-config --static-libs 2>/dev/null`
if test $? = 0 && echo $sdl_libs | grep -- -laa > /dev/null; then
sdl_libs="$sdl_libs `aalib-config --static-libs >2 /dev/null`"
sdl_cflags="$sdl_cflags `aalib-config --cflags >2 /dev/null`"
fi
if test "$static" = "yes" ; then
echo "CONFIG_STATIC=y" >> $config_host_mak
- LDFLAGS="-static $LDFLAGS"
fi
if test $profiler = "yes" ; then
echo "CONFIG_PROFILER=y" >> $config_host_mak
void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
+void qemu_flush_coalesced_mmio_buffer(void);
+
/*******************************************/
/* host CPU ticks (if available) */
const char *cpu_model_str; \
struct KVMState *kvm_state; \
struct kvm_run *kvm_run; \
- int kvm_fd;
+ int kvm_fd; \
+ int kvm_vcpu_dirty;
#endif
#define R_386_GOTOFF 9
#define R_386_GOTPC 10
#define R_386_NUM 11
+/* Not a dynamic reloc, so not included in R_386_NUM. Used in TCG. */
+#define R_386_PC8 23
#define R_MIPS_NONE 0
#define R_MIPS_16 1
kvm_uncoalesce_mmio_region(addr, size);
}
+void qemu_flush_coalesced_mmio_buffer(void)
+{
+ if (kvm_enabled())
+ kvm_flush_coalesced_mmio_buffer();
+}
+
ram_addr_t qemu_ram_alloc(ram_addr_t size)
{
RAMBlock *new_block;
ram_addr_t qemu_ram_addr_from_host(void *ptr)
{
RAMBlock *prev;
- RAMBlock **prevp;
RAMBlock *block;
uint8_t *host = ptr;
prev = NULL;
- prevp = &ram_blocks;
block = ram_blocks;
while (block && (block->host > host
|| block->host + block->length <= host)) {
- if (prev)
- prevp = &prev->next;
prev = block;
block = block->next;
}
#if (defined(CONFIG_BSD) && !defined(__APPLE__) && !defined(__GLIBC__)) || \
(defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10)
fpsetround(val);
-#elif defined(__arm__)
- /* nothing to do */
#else
fesetround(val);
#endif
float64 float64_round_to_int( float64 a STATUS_PARAM )
{
-#if defined(__arm__)
- switch(STATUS(float_rounding_mode)) {
- default:
- case float_round_nearest_even:
- asm("rndd %0, %1" : "=f" (a) : "f"(a));
- break;
- case float_round_down:
- asm("rnddm %0, %1" : "=f" (a) : "f"(a));
- break;
- case float_round_up:
- asm("rnddp %0, %1" : "=f" (a) : "f"(a));
- break;
- case float_round_to_zero:
- asm("rnddz %0, %1" : "=f" (a) : "f"(a));
- break;
- }
-#else
return rint(a);
-#endif
}
float64 float64_rem( float64 a, float64 b STATUS_PARAM)
float_round_up = FP_RP,
float_round_to_zero = FP_RZ
};
-#elif defined(__arm__)
-enum {
- float_round_nearest_even = 0,
- float_round_down = 1,
- float_round_up = 2,
- float_round_to_zero = 3
-};
#else
enum {
float_round_nearest_even = FE_TONEAREST,
--- /dev/null
+/*
+ * QEMU DEC 21154 PCI bridge
+ *
+ * Copyright (c) 2006-2007 Fabrice Bellard
+ * Copyright (c) 2007 Jocelyn Mayer
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "dec_pci.h"
+#include "sysbus.h"
+#include "pci.h"
+#include "pci_host.h"
+
+/* debug DEC */
+//#define DEBUG_DEC
+
+#ifdef DEBUG_DEC
+#define DEC_DPRINTF(fmt, ...) \
+ do { printf("DEC: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DEC_DPRINTF(fmt, ...)
+#endif
+
+typedef struct DECState {
+ SysBusDevice busdev;
+ PCIHostState host_state;
+} DECState;
+
+static int dec_map_irq(PCIDevice *pci_dev, int irq_num)
+{
+ return irq_num;
+}
+
+PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)
+{
+ DeviceState *dev;
+ PCIBus *ret;
+
+ dev = qdev_create(NULL, "dec-21154");
+ qdev_init_nofail(dev);
+ ret = pci_bridge_init(parent_bus, devfn,
+ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21154,
+ dec_map_irq, "DEC 21154 PCI-PCI bridge");
+
+ return ret;
+}
+
+static int pci_dec_21154_init_device(SysBusDevice *dev)
+{
+ DECState *s;
+ int pci_mem_config, pci_mem_data;
+
+ s = FROM_SYSBUS(DECState, dev);
+
+ pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
+ pci_mem_data = pci_host_data_register_mmio(&s->host_state);
+ sysbus_init_mmio(dev, 0x1000, pci_mem_config);
+ sysbus_init_mmio(dev, 0x1000, pci_mem_data);
+ return 0;
+}
+
+static int dec_21154_pci_host_init(PCIDevice *d)
+{
+ /* PCI2PCI bridge same values as PearPC - check this */
+ pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
+ pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
+ d->config[0x08] = 0x02; // revision
+ pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
+ d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
+ return 0;
+}
+
+static PCIDeviceInfo dec_21154_pci_host_info = {
+ .qdev.name = "dec-21154",
+ .qdev.size = sizeof(PCIDevice),
+ .init = dec_21154_pci_host_init,
+ .header_type = PCI_HEADER_TYPE_BRIDGE,
+};
+
+static void dec_register_devices(void)
+{
+ sysbus_register_dev("dec-21154", sizeof(DECState),
+ pci_dec_21154_init_device);
+ pci_qdev_register(&dec_21154_pci_host_info);
+}
+
+device_init(dec_register_devices)
--- /dev/null
+#ifndef DEC_PCI_H
+#define DEC_PCI_H
+
+#include "qemu-common.h"
+
+PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn);
+
+#endif
typedef enum {
chn_a, chn_b,
-} chn_id_t;
+} ChnID;
#define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a')
typedef enum {
ser, kbd, mouse,
-} chn_type_t;
+} ChnType;
#define SERIO_QUEUE_SIZE 256
qemu_irq irq;
uint32_t reg;
uint32_t rxint, txint, rxint_under_svc, txint_under_svc;
- chn_id_t chn; // this channel, A (base+4) or B (base+0)
- chn_type_t type;
+ ChnID chn; // this channel, A (base+4) or B (base+0)
+ ChnType type;
struct ChannelState *otherchn;
uint8_t rx, tx, wregs[SERIAL_REGS], rregs[SERIAL_REGS];
SERIOQueue queue;
uint8_t *async_buf;
uint32_t async_len;
- espdma_memory_read_write dma_memory_read;
- espdma_memory_read_write dma_memory_write;
+ ESPDMAMemoryReadWriteFunc dma_memory_read;
+ ESPDMAMemoryReadWriteFunc dma_memory_write;
void *dma_opaque;
};
};
void esp_init(target_phys_addr_t espaddr, int it_shift,
- espdma_memory_read_write dma_memory_read,
- espdma_memory_read_write dma_memory_write,
+ ESPDMAMemoryReadWriteFunc dma_memory_read,
+ ESPDMAMemoryReadWriteFunc dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset)
{
DeviceState *dev;
/* esp.c */
#define ESP_MAX_DEVS 7
-typedef void (*espdma_memory_read_write)(void *opaque, uint8_t *buf, int len);
+typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
void esp_init(target_phys_addr_t espaddr, int it_shift,
- espdma_memory_read_write dma_memory_read,
- espdma_memory_read_write dma_memory_write,
+ ESPDMAMemoryReadWriteFunc dma_memory_read,
+ ESPDMAMemoryReadWriteFunc dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset);
#endif
#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
/* Floppy disk drive emulation */
-typedef enum fdisk_type_t {
+typedef enum FDiskType {
FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
FDRIVE_DISK_USER = 0x04, /* User defined geometry */
FDRIVE_DISK_NONE = 0x05, /* No disk */
-} fdisk_type_t;
+} FDiskType;
-typedef enum fdrive_type_t {
+typedef enum FDriveType {
FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
FDRIVE_DRV_NONE = 0x03, /* No drive connected */
-} fdrive_type_t;
+} FDriveType;
-typedef enum fdisk_flags_t {
+typedef enum FDiskFlags {
FDISK_DBL_SIDES = 0x01,
-} fdisk_flags_t;
+} FDiskFlags;
-typedef struct fdrive_t {
+typedef struct FDrive {
DriveInfo *dinfo;
BlockDriverState *bs;
/* Drive status */
- fdrive_type_t drive;
+ FDriveType drive;
uint8_t perpendicular; /* 2.88 MB access mode */
/* Position */
uint8_t head;
uint8_t track;
uint8_t sect;
/* Media */
- fdisk_flags_t flags;
+ FDiskFlags flags;
uint8_t last_sect; /* Nb sector per track */
uint8_t max_track; /* Nb of tracks */
uint16_t bps; /* Bytes per sector */
uint8_t ro; /* Is read-only */
-} fdrive_t;
+} FDrive;
-static void fd_init (fdrive_t *drv)
+static void fd_init(FDrive *drv)
{
/* Drive */
drv->bs = drv->dinfo ? drv->dinfo->bdrv : NULL;
drv->max_track = 0;
}
-static int _fd_sector (uint8_t head, uint8_t track,
- uint8_t sect, uint8_t last_sect)
+static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
+ uint8_t last_sect)
{
return (((track * 2) + head) * last_sect) + sect - 1;
}
/* Returns current position, in sectors, for given drive */
-static int fd_sector (fdrive_t *drv)
+static int fd_sector(FDrive *drv)
{
- return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
+ return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect);
}
/* Seek to a new position:
* returns 3 if sector is invalid
* returns 4 if seek is disabled
*/
-static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
- int enable_seek)
+static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
+ int enable_seek)
{
uint32_t sector;
int ret;
drv->max_track, drv->last_sect);
return 3;
}
- sector = _fd_sector(head, track, sect, drv->last_sect);
+ sector = fd_sector_calc(head, track, sect, drv->last_sect);
ret = 0;
if (sector != fd_sector(drv)) {
#if 0
}
/* Set drive back to track 0 */
-static void fd_recalibrate (fdrive_t *drv)
+static void fd_recalibrate(FDrive *drv)
{
FLOPPY_DPRINTF("recalibrate\n");
drv->head = 0;
}
/* Recognize floppy formats */
-typedef struct fd_format_t {
- fdrive_type_t drive;
- fdisk_type_t disk;
+typedef struct FDFormat {
+ FDriveType drive;
+ FDiskType disk;
uint8_t last_sect;
uint8_t max_track;
uint8_t max_head;
const char *str;
-} fd_format_t;
+} FDFormat;
-static const fd_format_t fd_formats[] = {
+static const FDFormat fd_formats[] = {
/* First entry is default format */
/* 1.44 MB 3"1/2 floppy disks */
{ FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
};
/* Revalidate a disk drive after a disk change */
-static void fd_revalidate (fdrive_t *drv)
+static void fd_revalidate(FDrive *drv)
{
- const fd_format_t *parse;
+ const FDFormat *parse;
uint64_t nb_sectors, size;
int i, first_match, match;
int nb_heads, max_track, last_sect, ro;
/********************************************************/
/* Intel 82078 floppy disk controller emulation */
-static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
-static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
+static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
+static void fdctrl_reset_fifo(FDCtrl *fdctrl);
static int fdctrl_transfer_handler (void *opaque, int nchan,
int dma_pos, int dma_len);
-static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
-
-static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
-static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
-static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
-static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
-static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
-static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
-static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
-static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
-static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
-static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
-static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
+static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
+
+static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
+static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
+static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
+static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
+static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
+static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
+static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
+static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
+static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
+static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
+static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
enum {
FD_DIR_WRITE = 0,
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
-struct fdctrl_t {
+struct FDCtrl {
/* Controller's identification */
uint8_t version;
/* HW */
int sun4m;
/* Floppy drives */
uint8_t num_floppies;
- fdrive_t drives[MAX_FD];
+ FDrive drives[MAX_FD];
int reset_sensei;
};
-typedef struct fdctrl_sysbus_t {
+typedef struct FDCtrlSysBus {
SysBusDevice busdev;
- struct fdctrl_t state;
-} fdctrl_sysbus_t;
+ struct FDCtrl state;
+} FDCtrlSysBus;
-typedef struct fdctrl_isabus_t {
+typedef struct FDCtrlISABus {
ISADevice busdev;
- struct fdctrl_t state;
-} fdctrl_isabus_t;
+ struct FDCtrl state;
+} FDCtrlISABus;
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
{
- fdctrl_t *fdctrl = opaque;
+ FDCtrl *fdctrl = opaque;
uint32_t retval;
switch (reg) {
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
{
- fdctrl_t *fdctrl = opaque;
+ FDCtrl *fdctrl = opaque;
FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
- VMSTATE_UINT8(head, fdrive_t),
- VMSTATE_UINT8(track, fdrive_t),
- VMSTATE_UINT8(sect, fdrive_t),
+ VMSTATE_UINT8(head, FDrive),
+ VMSTATE_UINT8(track, FDrive),
+ VMSTATE_UINT8(sect, FDrive),
VMSTATE_END_OF_LIST()
}
};
static void fdc_pre_save(void *opaque)
{
- fdctrl_t *s = opaque;
+ FDCtrl *s = opaque;
s->dor_vmstate = s->dor | GET_CUR_DRV(s);
}
static int fdc_post_load(void *opaque, int version_id)
{
- fdctrl_t *s = opaque;
+ FDCtrl *s = opaque;
SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
.post_load = fdc_post_load,
.fields = (VMStateField []) {
/* Controller State */
- VMSTATE_UINT8(sra, fdctrl_t),
- VMSTATE_UINT8(srb, fdctrl_t),
- VMSTATE_UINT8(dor_vmstate, fdctrl_t),
- VMSTATE_UINT8(tdr, fdctrl_t),
- VMSTATE_UINT8(dsr, fdctrl_t),
- VMSTATE_UINT8(msr, fdctrl_t),
- VMSTATE_UINT8(status0, fdctrl_t),
- VMSTATE_UINT8(status1, fdctrl_t),
- VMSTATE_UINT8(status2, fdctrl_t),
+ VMSTATE_UINT8(sra, FDCtrl),
+ VMSTATE_UINT8(srb, FDCtrl),
+ VMSTATE_UINT8(dor_vmstate, FDCtrl),
+ VMSTATE_UINT8(tdr, FDCtrl),
+ VMSTATE_UINT8(dsr, FDCtrl),
+ VMSTATE_UINT8(msr, FDCtrl),
+ VMSTATE_UINT8(status0, FDCtrl),
+ VMSTATE_UINT8(status1, FDCtrl),
+ VMSTATE_UINT8(status2, FDCtrl),
/* Command FIFO */
- VMSTATE_VARRAY_INT32(fifo, fdctrl_t, fifo_size, 0, vmstate_info_uint8, uint8),
- VMSTATE_UINT32(data_pos, fdctrl_t),
- VMSTATE_UINT32(data_len, fdctrl_t),
- VMSTATE_UINT8(data_state, fdctrl_t),
- VMSTATE_UINT8(data_dir, fdctrl_t),
- VMSTATE_UINT8(eot, fdctrl_t),
+ VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8, uint8),
+ VMSTATE_UINT32(data_pos, FDCtrl),
+ VMSTATE_UINT32(data_len, FDCtrl),
+ VMSTATE_UINT8(data_state, FDCtrl),
+ VMSTATE_UINT8(data_dir, FDCtrl),
+ VMSTATE_UINT8(eot, FDCtrl),
/* States kept only to be returned back */
- VMSTATE_UINT8(timer0, fdctrl_t),
- VMSTATE_UINT8(timer1, fdctrl_t),
- VMSTATE_UINT8(precomp_trk, fdctrl_t),
- VMSTATE_UINT8(config, fdctrl_t),
- VMSTATE_UINT8(lock, fdctrl_t),
- VMSTATE_UINT8(pwrd, fdctrl_t),
- VMSTATE_UINT8_EQUAL(num_floppies, fdctrl_t),
- VMSTATE_STRUCT_ARRAY(drives, fdctrl_t, MAX_FD, 1,
- vmstate_fdrive, fdrive_t),
+ VMSTATE_UINT8(timer0, FDCtrl),
+ VMSTATE_UINT8(timer1, FDCtrl),
+ VMSTATE_UINT8(precomp_trk, FDCtrl),
+ VMSTATE_UINT8(config, FDCtrl),
+ VMSTATE_UINT8(lock, FDCtrl),
+ VMSTATE_UINT8(pwrd, FDCtrl),
+ VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
+ VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
+ vmstate_fdrive, FDrive),
VMSTATE_END_OF_LIST()
}
};
static void fdctrl_external_reset_sysbus(DeviceState *d)
{
- fdctrl_sysbus_t *sys = container_of(d, fdctrl_sysbus_t, busdev.qdev);
- fdctrl_t *s = &sys->state;
+ FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
+ FDCtrl *s = &sys->state;
fdctrl_reset(s, 0);
}
static void fdctrl_external_reset_isa(DeviceState *d)
{
- fdctrl_isabus_t *isa = container_of(d, fdctrl_isabus_t, busdev.qdev);
- fdctrl_t *s = &isa->state;
+ FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
+ FDCtrl *s = &isa->state;
fdctrl_reset(s, 0);
}
static void fdctrl_handle_tc(void *opaque, int irq, int level)
{
- //fdctrl_t *s = opaque;
+ //FDCtrl *s = opaque;
if (level) {
// XXX
}
/* XXX: may change if moved to bdrv */
-int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
+int fdctrl_get_drive_type(FDCtrl *fdctrl, int drive_num)
{
return fdctrl->drives[drive_num].drive;
}
/* Change IRQ state */
-static void fdctrl_reset_irq (fdctrl_t *fdctrl)
+static void fdctrl_reset_irq(FDCtrl *fdctrl)
{
if (!(fdctrl->sra & FD_SRA_INTPEND))
return;
fdctrl->sra &= ~FD_SRA_INTPEND;
}
-static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
+static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
{
/* Sparc mutation */
if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
}
/* Reset controller */
-static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
+static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
{
int i;
}
}
-static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
+static inline FDrive *drv0(FDCtrl *fdctrl)
{
return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
}
-static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
+static inline FDrive *drv1(FDCtrl *fdctrl)
{
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
return &fdctrl->drives[1];
}
#if MAX_FD == 4
-static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
+static inline FDrive *drv2(FDCtrl *fdctrl)
{
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
return &fdctrl->drives[2];
return &fdctrl->drives[1];
}
-static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
+static inline FDrive *drv3(FDCtrl *fdctrl)
{
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
return &fdctrl->drives[3];
}
#endif
-static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
+static FDrive *get_cur_drv(FDCtrl *fdctrl)
{
switch (fdctrl->cur_drv) {
case 0: return drv0(fdctrl);
}
/* Status A register : 0x00 (read-only) */
-static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
+static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
{
uint32_t retval = fdctrl->sra;
}
/* Status B register : 0x01 (read-only) */
-static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
+static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
{
uint32_t retval = fdctrl->srb;
}
/* Digital output register : 0x02 */
-static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
+static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
{
uint32_t retval = fdctrl->dor;
return retval;
}
-static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
+static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
{
FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
}
/* Tape drive register : 0x03 */
-static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
+static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
{
uint32_t retval = fdctrl->tdr;
return retval;
}
-static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
+static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
{
/* Reset mode */
if (!(fdctrl->dor & FD_DOR_nRESET)) {
}
/* Main status register : 0x04 (read) */
-static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
+static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
{
uint32_t retval = fdctrl->msr;
}
/* Data select rate register : 0x04 (write) */
-static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
+static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
{
/* Reset mode */
if (!(fdctrl->dor & FD_DOR_nRESET)) {
fdctrl->dsr = value;
}
-static int fdctrl_media_changed(fdrive_t *drv)
+static int fdctrl_media_changed(FDrive *drv)
{
int ret;
}
/* Digital input register : 0x07 (read-only) */
-static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
+static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
{
uint32_t retval = 0;
}
/* FIFO state control */
-static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
+static void fdctrl_reset_fifo(FDCtrl *fdctrl)
{
fdctrl->data_dir = FD_DIR_WRITE;
fdctrl->data_pos = 0;
}
/* Set FIFO status for the host to read */
-static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
+static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
{
fdctrl->data_dir = FD_DIR_READ;
fdctrl->data_len = fifo_len;
}
/* Set an error: unimplemented/unknown command */
-static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
+static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
{
FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
fdctrl->fifo[0] = FD_SR0_INVCMD;
}
/* Seek to next sector */
-static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
+static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
{
FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
cur_drv->head, cur_drv->track, cur_drv->sect,
}
/* Callback for transfer end (stop or abort) */
-static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
- uint8_t status1, uint8_t status2)
+static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
+ uint8_t status1, uint8_t status2)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
cur_drv = get_cur_drv(fdctrl);
FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
}
/* Prepare a data transfer (either DMA or FIFO) */
-static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
+static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
uint8_t kh, kt, ks;
int did_seek = 0;
ks = fdctrl->fifo[4];
FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
GET_CUR_DRV(fdctrl), kh, kt, ks,
- _fd_sector(kh, kt, ks, cur_drv->last_sect));
+ fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
case 2:
/* sect too big */
}
/* Prepare a transfer of deleted data */
-static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
+static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
{
FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
static int fdctrl_transfer_handler (void *opaque, int nchan,
int dma_pos, int dma_len)
{
- fdctrl_t *fdctrl;
- fdrive_t *cur_drv;
+ FDCtrl *fdctrl;
+ FDrive *cur_drv;
int len, start_pos, rel_pos;
uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
}
/* Data register : 0x05 */
-static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
+static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
uint32_t retval = 0;
int pos;
return retval;
}
-static void fdctrl_format_sector (fdctrl_t *fdctrl)
+static void fdctrl_format_sector(FDCtrl *fdctrl)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
uint8_t kh, kt, ks;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
ks = fdctrl->fifo[8];
FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
GET_CUR_DRV(fdctrl), kh, kt, ks,
- _fd_sector(kh, kt, ks, cur_drv->last_sect));
+ fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
case 2:
/* sect too big */
}
}
-static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
{
fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
fdctrl->fifo[0] = fdctrl->lock << 4;
fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
}
-static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv = get_cur_drv(fdctrl);
/* Drives position */
fdctrl->fifo[0] = drv0(fdctrl)->track;
fdctrl_set_fifo(fdctrl, 10, 0);
}
-static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
{
/* Controller's version */
fdctrl->fifo[0] = fdctrl->version;
fdctrl_set_fifo(fdctrl, 1, 1);
}
-static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
{
fdctrl->fifo[0] = 0x41; /* Stepping 1 */
fdctrl_set_fifo(fdctrl, 1, 0);
}
-static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv = get_cur_drv(fdctrl);
/* Drives position */
drv0(fdctrl)->track = fdctrl->fifo[3];
fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv = get_cur_drv(fdctrl);
fdctrl->fifo[0] = 0;
fdctrl->fifo[1] = 0;
fdctrl_set_fifo(fdctrl, 15, 1);
}
-static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv = get_cur_drv(fdctrl);
/* XXX: should set main status register to busy */
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
}
-static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
}
-static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
{
fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
fdctrl->timer1 = fdctrl->fifo[2] >> 1;
fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
fdctrl_set_fifo(fdctrl, 1, 0);
}
-static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
}
-static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv = get_cur_drv(fdctrl);
if(fdctrl->reset_sensei > 0) {
fdctrl->fifo[0] =
fdctrl->status0 = FD_SR0_RDYCHG;
}
-static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
}
}
-static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv = get_cur_drv(fdctrl);
if (fdctrl->fifo[1] & 0x80)
cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
{
fdctrl->config = fdctrl->fifo[2];
fdctrl->precomp_trk = fdctrl->fifo[3];
fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
{
fdctrl->pwrd = fdctrl->fifo[1];
fdctrl->fifo[0] = fdctrl->fifo[1];
fdctrl_set_fifo(fdctrl, 1, 1);
}
-static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
{
/* No result back */
fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv = get_cur_drv(fdctrl);
if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
/* Command parameters done */
}
}
-static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
}
-static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
uint8_t mask;
const char* name;
int parameters;
- void (*handler)(fdctrl_t *fdctrl, int direction);
+ void (*handler)(FDCtrl *fdctrl, int direction);
int direction;
} handlers[] = {
{ FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
/* Associate command to an index in the 'handlers' array */
static uint8_t command_to_handler[256];
-static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
+static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
int pos;
/* Reset mode */
static void fdctrl_result_timer(void *opaque)
{
- fdctrl_t *fdctrl = opaque;
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDCtrl *fdctrl = opaque;
+ FDrive *cur_drv = get_cur_drv(fdctrl);
/* Pretend we are spinning.
* This is needed for Coherent, which uses READ ID to check for
}
/* Init functions */
-static void fdctrl_connect_drives(fdctrl_t *fdctrl)
+static void fdctrl_connect_drives(FDCtrl *fdctrl)
{
unsigned int i;
}
}
-fdctrl_t *fdctrl_init_isa(DriveInfo **fds)
+FDCtrl *fdctrl_init_isa(DriveInfo **fds)
{
ISADevice *dev;
qdev_prop_set_drive(&dev->qdev, "driveB", fds[1]);
if (qdev_init(&dev->qdev) < 0)
return NULL;
- return &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state);
+ return &(DO_UPCAST(FDCtrlISABus, busdev, dev)->state);
}
-fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
- target_phys_addr_t mmio_base,
- DriveInfo **fds)
+FDCtrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
+ target_phys_addr_t mmio_base, DriveInfo **fds)
{
- fdctrl_t *fdctrl;
+ FDCtrl *fdctrl;
DeviceState *dev;
- fdctrl_sysbus_t *sys;
+ FDCtrlSysBus *sys;
dev = qdev_create(NULL, "sysbus-fdc");
- sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
+ sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
fdctrl = &sys->state;
fdctrl->dma_chann = dma_chann; /* FIXME */
qdev_prop_set_drive(dev, "driveA", fds[0]);
return fdctrl;
}
-fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
- DriveInfo **fds, qemu_irq *fdc_tc)
+FDCtrl *sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
+ DriveInfo **fds, qemu_irq *fdc_tc)
{
DeviceState *dev;
- fdctrl_sysbus_t *sys;
- fdctrl_t *fdctrl;
+ FDCtrlSysBus *sys;
+ FDCtrl *fdctrl;
dev = qdev_create(NULL, "SUNW,fdtwo");
qdev_prop_set_drive(dev, "drive", fds[0]);
qdev_init_nofail(dev);
- sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
+ sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
fdctrl = &sys->state;
sysbus_connect_irq(&sys->busdev, 0, irq);
sysbus_mmio_map(&sys->busdev, 0, io_base);
return fdctrl;
}
-static int fdctrl_init_common(fdctrl_t *fdctrl, target_phys_addr_t io_base)
+static int fdctrl_init_common(FDCtrl *fdctrl, target_phys_addr_t io_base)
{
int i, j;
static int command_tables_inited = 0;
static int isabus_fdc_init1(ISADevice *dev)
{
- fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev);
- fdctrl_t *fdctrl = &isa->state;
+ FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
+ FDCtrl *fdctrl = &isa->state;
int iobase = 0x3f0;
int isairq = 6;
int dma_chann = 2;
static int sysbus_fdc_init1(SysBusDevice *dev)
{
- fdctrl_sysbus_t *sys = DO_UPCAST(fdctrl_sysbus_t, busdev, dev);
- fdctrl_t *fdctrl = &sys->state;
+ FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
+ FDCtrl *fdctrl = &sys->state;
int io;
int ret;
static int sun4m_fdc_init1(SysBusDevice *dev)
{
- fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
+ FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
int io;
io = cpu_register_io_memory(fdctrl_mem_read_strict,
static ISADeviceInfo isa_fdc_info = {
.init = isabus_fdc_init1,
.qdev.name = "isa-fdc",
- .qdev.size = sizeof(fdctrl_isabus_t),
+ .qdev.size = sizeof(FDCtrlISABus),
.qdev.no_user = 1,
.qdev.reset = fdctrl_external_reset_isa,
.qdev.props = (Property[]) {
- DEFINE_PROP_DRIVE("driveA", fdctrl_isabus_t, state.drives[0].dinfo),
- DEFINE_PROP_DRIVE("driveB", fdctrl_isabus_t, state.drives[1].dinfo),
+ DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].dinfo),
+ DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].dinfo),
DEFINE_PROP_END_OF_LIST(),
},
};
static SysBusDeviceInfo sysbus_fdc_info = {
.init = sysbus_fdc_init1,
.qdev.name = "sysbus-fdc",
- .qdev.size = sizeof(fdctrl_sysbus_t),
+ .qdev.size = sizeof(FDCtrlSysBus),
.qdev.reset = fdctrl_external_reset_sysbus,
.qdev.props = (Property[]) {
- DEFINE_PROP_DRIVE("driveA", fdctrl_sysbus_t, state.drives[0].dinfo),
- DEFINE_PROP_DRIVE("driveB", fdctrl_sysbus_t, state.drives[1].dinfo),
+ DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].dinfo),
+ DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].dinfo),
DEFINE_PROP_END_OF_LIST(),
},
};
static SysBusDeviceInfo sun4m_fdc_info = {
.init = sun4m_fdc_init1,
.qdev.name = "SUNW,fdtwo",
- .qdev.size = sizeof(fdctrl_sysbus_t),
+ .qdev.size = sizeof(FDCtrlSysBus),
.qdev.reset = fdctrl_external_reset_sysbus,
.qdev.props = (Property[]) {
- DEFINE_PROP_DRIVE("drive", fdctrl_sysbus_t, state.drives[0].dinfo),
+ DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].dinfo),
DEFINE_PROP_END_OF_LIST(),
},
};
#include "sysemu.h"
#define MAX_FD 2
-typedef struct fdctrl_t fdctrl_t;
+typedef struct FDCtrl FDCtrl;
-fdctrl_t *fdctrl_init_isa(DriveInfo **fds);
-fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
- target_phys_addr_t mmio_base,
- DriveInfo **fds);
-fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
- DriveInfo **fds, qemu_irq *fdc_tc);
-int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
+FDCtrl *fdctrl_init_isa(DriveInfo **fds);
+FDCtrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
+ target_phys_addr_t mmio_base, DriveInfo **fds);
+FDCtrl *sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
+ DriveInfo **fds, qemu_irq *fdc_tc);
+int fdctrl_get_drive_type(FDCtrl *fdctrl, int drive_num);
#define FW_CFG_SIZE 2
-typedef struct _FWCfgEntry {
+typedef struct FWCfgEntry {
uint32_t len;
uint8_t *data;
void *callback_opaque;
FWCfgCallback callback;
} FWCfgEntry;
-struct _FWCfgState {
+struct FWCfgState {
FWCfgEntry entries[2][FW_CFG_MAX_ENTRY];
FWCfgFiles *files;
uint16_t cur_entry;
typedef void (*FWCfgCallback)(void *opaque, uint8_t *data);
-typedef struct _FWCfgState FWCfgState;
+typedef struct FWCfgState FWCfgState;
int fw_cfg_add_bytes(FWCfgState *s, uint16_t key, uint8_t *data, uint32_t len);
int fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value);
int fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value);
return 0;
}
-static int pci_dec_21154_init_device(SysBusDevice *dev)
-{
- GrackleState *s;
- int pci_mem_config, pci_mem_data;
-
- s = FROM_SYSBUS(GrackleState, dev);
-
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
- pci_mem_data = pci_host_data_register_mmio(&s->host_state);
- sysbus_init_mmio(dev, 0x1000, pci_mem_config);
- sysbus_init_mmio(dev, 0x1000, pci_mem_data);
- return 0;
-}
-
static int grackle_pci_host_init(PCIDevice *d)
{
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
return 0;
}
-static int dec_21154_pci_host_init(PCIDevice *d)
-{
- /* PCI2PCI bridge same values as PearPC - check this */
- pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
- pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
- d->config[0x08] = 0x02; // revision
- pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
- d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
-
- d->config[0x18] = 0x0; // primary_bus
- d->config[0x19] = 0x1; // secondary_bus
- d->config[0x1a] = 0x1; // subordinate_bus
- d->config[0x1c] = 0x10; // io_base
- d->config[0x1d] = 0x20; // io_limit
-
- d->config[0x20] = 0x80; // memory_base
- d->config[0x21] = 0x80;
- d->config[0x22] = 0x90; // memory_limit
- d->config[0x23] = 0x80;
-
- d->config[0x24] = 0x00; // prefetchable_memory_base
- d->config[0x25] = 0x84;
- d->config[0x26] = 0x00; // prefetchable_memory_limit
- d->config[0x27] = 0x85;
- return 0;
-}
-
static PCIDeviceInfo grackle_pci_host_info = {
.qdev.name = "grackle",
.qdev.size = sizeof(PCIDevice),
.init = grackle_pci_host_init,
};
-static PCIDeviceInfo dec_21154_pci_host_info = {
- .qdev.name = "dec-21154",
- .qdev.size = sizeof(PCIDevice),
- .init = dec_21154_pci_host_init,
- .header_type = PCI_HEADER_TYPE_BRIDGE,
-};
-
static void grackle_register_devices(void)
{
sysbus_register_dev("grackle", sizeof(GrackleState),
pci_grackle_init_device);
pci_qdev_register(&grackle_pci_host_info);
- sysbus_register_dev("dec-21154", sizeof(GrackleState),
- pci_dec_21154_init_device);
- pci_qdev_register(&dec_21154_pci_host_info);
}
device_init(grackle_register_devices)
//#define DEBUG
#ifdef DEBUG
-#define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
+#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
#else
-#define dprintf(fmt, ...)
+#define DPRINTF(fmt, ...)
#endif
#define GT_REGS (0x1000 >> 2)
check_reserved_space(&start, &length);
length = 0x1000;
/* Map new address */
- dprintf("ISD: %x@%x -> %x@%x, %x\n", s->ISD_length, s->ISD_start,
+ DPRINTF("ISD: %x@%x -> %x@%x, %x\n", s->ISD_length, s->ISD_start,
length, start, s->ISD_handle);
s->ISD_start = start;
s->ISD_length = length;
case GT_DEV_B3:
case GT_DEV_BOOT:
/* Not implemented */
- dprintf ("Unimplemented device register offset 0x%x\n", saddr << 2);
+ DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2);
break;
/* ECC */
case GT_DMA2_CUR:
case GT_DMA3_CUR:
/* Not implemented */
- dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
+ DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
break;
/* DMA Channel Control */
case GT_DMA2_CTRL:
case GT_DMA3_CTRL:
/* Not implemented */
- dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
+ DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
break;
/* DMA Arbiter */
case GT_DMA_ARB:
/* Not implemented */
- dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
+ DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
break;
/* Timer/Counter */
case GT_TC3:
case GT_TC_CONTROL:
/* Not implemented */
- dprintf ("Unimplemented timer register offset 0x%x\n", saddr << 2);
+ DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2);
break;
/* PCI Internal */
/* not really implemented */
s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
- dprintf("INTRCAUSE %x\n", val);
+ DPRINTF("INTRCAUSE %x\n", val);
break;
case GT_INTRMASK:
s->regs[saddr] = val & 0x3c3ffffe;
- dprintf("INTRMASK %x\n", val);
+ DPRINTF("INTRMASK %x\n", val);
break;
case GT_PCI0_ICMASK:
s->regs[saddr] = val & 0x03fffffe;
- dprintf("ICMASK %x\n", val);
+ DPRINTF("ICMASK %x\n", val);
break;
case GT_PCI0_SERR0MASK:
s->regs[saddr] = val & 0x0000003f;
- dprintf("SERR0MASK %x\n", val);
+ DPRINTF("SERR0MASK %x\n", val);
break;
/* Reserved when only PCI_0 is configured. */
break;
default:
- dprintf ("Bad register offset 0x%x\n", (int)addr);
+ DPRINTF ("Bad register offset 0x%x\n", (int)addr);
break;
}
}
/* Interrupts */
case GT_INTRCAUSE:
val = s->regs[saddr];
- dprintf("INTRCAUSE %x\n", val);
+ DPRINTF("INTRCAUSE %x\n", val);
break;
case GT_INTRMASK:
val = s->regs[saddr];
- dprintf("INTRMASK %x\n", val);
+ DPRINTF("INTRMASK %x\n", val);
break;
case GT_PCI0_ICMASK:
val = s->regs[saddr];
- dprintf("ICMASK %x\n", val);
+ DPRINTF("ICMASK %x\n", val);
break;
case GT_PCI0_SERR0MASK:
val = s->regs[saddr];
- dprintf("SERR0MASK %x\n", val);
+ DPRINTF("SERR0MASK %x\n", val);
break;
/* Reserved when only PCI_0 is configured. */
default:
val = s->regs[saddr];
- dprintf ("Bad register offset 0x%x\n", (int)addr);
+ DPRINTF ("Bad register offset 0x%x\n", (int)addr);
break;
}
//#define HPET_DEBUG
#ifdef HPET_DEBUG
-#define dprintf printf
+#define DPRINTF printf
#else
-#define dprintf(...)
+#define DPRINTF(...)
#endif
static HPETState *hpet_statep;
HPETState *s = (HPETState *)opaque;
uint64_t cur_tick, index;
- dprintf("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
+ DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
index = addr;
/*address range of all TN regs*/
if (index >= 0x100 && index <= 0x3ff) {
case HPET_TN_ROUTE:
return timer->fsb >> 32;
default:
- dprintf("qemu: invalid hpet_ram_readl\n");
+ DPRINTF("qemu: invalid hpet_ram_readl\n");
break;
}
} else {
case HPET_CFG:
return s->config;
case HPET_CFG + 4:
- dprintf("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
+ DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
return 0;
case HPET_COUNTER:
if (hpet_enabled())
cur_tick = hpet_get_ticks();
else
cur_tick = s->hpet_counter;
- dprintf("qemu: reading counter = %" PRIx64 "\n", cur_tick);
+ DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick);
return cur_tick;
case HPET_COUNTER + 4:
if (hpet_enabled())
cur_tick = hpet_get_ticks();
else
cur_tick = s->hpet_counter;
- dprintf("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
+ DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
return cur_tick >> 32;
case HPET_STATUS:
return s->isr;
default:
- dprintf("qemu: invalid hpet_ram_readl\n");
+ DPRINTF("qemu: invalid hpet_ram_readl\n");
break;
}
}
HPETState *s = (HPETState *)opaque;
uint64_t old_val, new_val, val, index;
- dprintf("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
+ DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
index = addr;
old_val = hpet_ram_readl(opaque, addr);
new_val = value;
/*address range of all TN regs*/
if (index >= 0x100 && index <= 0x3ff) {
uint8_t timer_id = (addr - 0x100) / 0x20;
- dprintf("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
+ DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
HPETTimer *timer = &s->timer[timer_id];
switch ((addr - 0x100) % 0x20) {
case HPET_TN_CFG:
- dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n");
+ DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
timer->config = (timer->config & 0xffffffff00000000ULL) | val;
if (new_val & HPET_TN_32BIT) {
break;
case HPET_TN_CFG + 4: // Interrupt capabilities
- dprintf("qemu: invalid HPET_TN_CFG+4 write\n");
+ DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
break;
case HPET_TN_CMP: // comparator register
- dprintf("qemu: hpet_ram_writel HPET_TN_CMP \n");
+ DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
if (timer->config & HPET_TN_32BIT)
new_val = (uint32_t)new_val;
if (!timer_is_periodic(timer) ||
hpet_set_timer(timer);
break;
case HPET_TN_CMP + 4: // comparator register high order
- dprintf("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
+ DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
if (!timer_is_periodic(timer) ||
(timer->config & HPET_TN_SETVAL))
timer->cmp = (timer->cmp & 0xffffffffULL)
hpet_set_timer(timer);
break;
case HPET_TN_ROUTE + 4:
- dprintf("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
+ DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
break;
default:
- dprintf("qemu: invalid hpet_ram_writel\n");
+ DPRINTF("qemu: invalid hpet_ram_writel\n");
break;
}
return;
}
break;
case HPET_CFG + 4:
- dprintf("qemu: invalid HPET_CFG+4 write \n");
+ DPRINTF("qemu: invalid HPET_CFG+4 write \n");
break;
case HPET_STATUS:
/* FIXME: need to handle level-triggered interrupts */
printf("qemu: Writing counter while HPET enabled!\n");
s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL)
| value;
- dprintf("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
+ DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
value, s->hpet_counter);
break;
case HPET_COUNTER + 4:
printf("qemu: Writing counter while HPET enabled!\n");
s->hpet_counter = (s->hpet_counter & 0xffffffffULL)
| (((uint64_t)value) << 32);
- dprintf("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
+ DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
value, s->hpet_counter);
break;
default:
- dprintf("qemu: invalid hpet_ram_writel\n");
+ DPRINTF("qemu: invalid hpet_ram_writel\n");
break;
}
}
int i, iomemtype;
HPETState *s;
- dprintf ("hpet_init\n");
+ DPRINTF ("hpet_init\n");
s = qemu_mallocz(sizeof(HPETState));
hpet_statep = s;
* http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
*/
-struct m48t59_t {
+struct M48t59State {
/* Model parameters */
uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
/* Hardware parameters */
typedef struct M48t59ISAState {
ISADevice busdev;
- m48t59_t state;
+ M48t59State state;
} M48t59ISAState;
typedef struct M48t59SysBusState {
SysBusDevice busdev;
- m48t59_t state;
+ M48t59State state;
} M48t59SysBusState;
/* Fake timer functions */
{
struct tm tm;
uint64_t next_time;
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
qemu_set_irq(NVRAM->IRQ, 1);
if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
qemu_set_irq(NVRAM->IRQ, 0);
}
-static void set_alarm (m48t59_t *NVRAM)
+static void set_alarm(M48t59State *NVRAM)
{
int diff;
if (NVRAM->alrm_timer != NULL) {
}
/* RTC management helpers */
-static inline void get_time (m48t59_t *NVRAM, struct tm *tm)
+static inline void get_time(M48t59State *NVRAM, struct tm *tm)
{
qemu_get_timedate(tm, NVRAM->time_offset);
}
-static void set_time (m48t59_t *NVRAM, struct tm *tm)
+static void set_time(M48t59State *NVRAM, struct tm *tm)
{
NVRAM->time_offset = qemu_timedate_diff(tm);
set_alarm(NVRAM);
/* Watchdog management */
static void watchdog_cb (void *opaque)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
NVRAM->buffer[0x1FF0] |= 0x80;
if (NVRAM->buffer[0x1FF7] & 0x80) {
}
}
-static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
+static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
{
uint64_t interval; /* in 1/16 seconds */
/* Direct access to NVRAM */
void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
struct tm tm;
int tmp;
uint32_t m48t59_read (void *opaque, uint32_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
struct tm tm;
uint32_t retval = 0xFF;
void m48t59_set_addr (void *opaque, uint32_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
NVRAM->addr = addr;
}
void m48t59_toggle_lock (void *opaque, int lock)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
NVRAM->lock ^= 1 << lock;
}
/* IO access to NVRAM */
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
addr -= NVRAM->io_base;
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
uint32_t retval;
addr -= NVRAM->io_base;
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
m48t59_write(NVRAM, addr, value & 0xff);
}
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
m48t59_write(NVRAM, addr + 1, value & 0xff);
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr);
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr) << 8;
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr) << 24;
static void m48t59_save(QEMUFile *f, void *opaque)
{
- m48t59_t *s = opaque;
+ M48t59State *s = opaque;
qemu_put_8s(f, &s->lock);
qemu_put_be16s(f, &s->addr);
static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
{
- m48t59_t *s = opaque;
+ M48t59State *s = opaque;
if (version_id != 1)
return -EINVAL;
return 0;
}
-static void m48t59_reset_common(m48t59_t *NVRAM)
+static void m48t59_reset_common(M48t59State *NVRAM)
{
NVRAM->addr = 0;
NVRAM->lock = 0;
static void m48t59_reset_isa(DeviceState *d)
{
M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev);
- m48t59_t *NVRAM = &isa->state;
+ M48t59State *NVRAM = &isa->state;
m48t59_reset_common(NVRAM);
}
static void m48t59_reset_sysbus(DeviceState *d)
{
M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev);
- m48t59_t *NVRAM = &sys->state;
+ M48t59State *NVRAM = &sys->state;
m48t59_reset_common(NVRAM);
}
/* Initialisation routine */
-m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
- uint32_t io_base, uint16_t size,
- int type)
+M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
+ uint32_t io_base, uint16_t size, int type)
{
DeviceState *dev;
SysBusDevice *s;
return &d->state;
}
-m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
+M48t59State *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
{
M48t59ISAState *d;
ISADevice *dev;
- m48t59_t *s;
+ M48t59State *s;
dev = isa_create("m48t59_isa");
qdev_prop_set_uint32(&dev->qdev, "type", type);
return s;
}
-static void m48t59_init_common(m48t59_t *s)
+static void m48t59_init_common(M48t59State *s)
{
s->buffer = qemu_mallocz(s->size);
if (s->type == 59) {
static int m48t59_init_isa1(ISADevice *dev)
{
M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
- m48t59_t *s = &d->state;
+ M48t59State *s = &d->state;
isa_init_irq(dev, &s->IRQ, 8);
m48t59_init_common(s);
static int m48t59_init1(SysBusDevice *dev)
{
M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
- m48t59_t *s = &d->state;
+ M48t59State *s = &d->state;
int mem_index;
sysbus_init_irq(dev, &s->IRQ);
CPUState *env = opaque;
cpu_reset(env);
- /* The bootload does not need to be rewritten as it is located in a
+ /* The bootloader does not need to be rewritten as it is located in a
read only location. The kernel location and the arguments table
location does not change. */
if (loaderparams.kernel_filename) {
ISADevice *isa_dev;
CPUState *env;
RTCState *rtc_state;
- fdctrl_t *floppy_controller;
+ FDCtrl *floppy_controller;
MaltaFPGAState *malta_fpga;
qemu_irq *i8259;
int piix4_devfn;
uint32_t initrd_image, uint32_t initrd_size,
uint32_t NVRAM_image,
int width, int height, int depth);
-typedef struct m48t59_t m48t59_t;
+typedef struct M48t59State M48t59State;
void m48t59_write (void *private, uint32_t addr, uint32_t val);
uint32_t m48t59_read (void *private, uint32_t addr);
void m48t59_toggle_lock (void *private, int lock);
-m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type);
-m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
- uint32_t io_base, uint16_t size,
- int type);
+M48t59State *m48t59_init_isa(uint32_t io_base, uint16_t size, int type);
+M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
+ uint32_t io_base, uint16_t size, int type);
void m48t59_set_addr (void *opaque, uint32_t addr);
#endif /* !NVRAM_H */
#define MAX_IDE_BUS 2
-static fdctrl_t *floppy_controller;
+static FDCtrl *floppy_controller;
static RTCState *rtc_state;
static PITState *pit;
static PCII440FXState *i440fx_state;
}
class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
- if (class == 0x0604) {
+ if (class == PCI_CLASS_BRIDGE_HOST || class == PCI_CLASS_BRIDGE_PCI) {
QDict *qdict;
QObject *pci_bridge;
"'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
"'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
"'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
- dev->config[0x19], dev->config[PCI_SECONDARY_BUS],
+ dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
dev->config[PCI_SUBORDINATE_BUS],
pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
PCI_BASE_ADDRESS_MEM_PREFETCH));
- if (dev->config[0x19] != 0) {
- qdict = qobject_to_qdict(pci_bridge);
- qdict_put_obj(qdict, "devices",
- pci_get_devices_list(bus, dev->config[0x19]));
- }
+ if (dev->config[PCI_SECONDARY_BUS] != 0) {
+ PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
+ if (child_bus) {
+ qdict = qobject_to_qdict(pci_bridge);
+ qdict_put_obj(qdict, "devices",
+ pci_get_devices_list(child_bus,
+ dev->config[PCI_SECONDARY_BUS]));
+ }
+ }
qdict = qobject_to_qdict(obj);
qdict_put_obj(qdict, "pci_bridge", pci_bridge);
}
PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
{
- PCIBus *sec;
+ PCIBus *sec, *ret;
if (!bus)
return NULL;
/* try child bus */
QLIST_FOREACH(sec, &bus->child, sibling) {
-
if (!bus->parent_dev /* pci host bridge */
- || (pci_bus_num(sec) <= bus_num &&
- bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
- return pci_find_bus(sec, bus_num);
+ || (pci_bus_num(sec) >= bus_num &&
+ bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS]) ) {
+ ret = pci_find_bus(sec, bus_num);
+ if (ret) {
+ return ret;
+ }
}
}
/* Fake super-io ports for PREP platform (Intel 82378ZB) */
typedef struct sysctrl_t {
qemu_irq reset_irq;
- m48t59_t *nvram;
+ M48t59State *nvram;
uint8_t state;
uint8_t syscontrol;
uint8_t fake_io[2];
CPUState *env = NULL, *envs[MAX_CPUS];
char *filename;
nvram_t nvram;
- m48t59_t *m48t59;
+ M48t59State *m48t59;
int PPC_io_memory;
int linux_boot, i, nb_nics1, bios_size;
ram_addr_t ram_offset, bios_offset;
uint16_t keyctlclr;
uint16_t pad0;
uint16_t pad1;
- uint16_t powoff;
uint16_t verreg;
uint16_t inport;
uint16_t outport;
case PA_OUTPORT:
return s->outport;
case PA_POWOFF:
- return s->powoff;
+ return 0x00;
case PA_VERREG:
return 0x10;
}
s->outport = value;
break;
case PA_POWOFF:
- s->powoff = value;
- break;
+ if (value & 1) {
+ qemu_system_shutdown_request();
+ }
+ break;
case PA_VERREG:
/* Discard writes */
break;
return 0;
}
-static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
- const char *boot_devices, ram_addr_t RAM_size,
- uint32_t kernel_size,
+static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
+ const char *cmdline, const char *boot_devices,
+ ram_addr_t RAM_size, uint32_t kernel_size,
int width, int height, int depth,
int nvram_machine_id, const char *arch)
{
return 0;
}
-static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
- const char *arch,
- ram_addr_t RAM_size,
- const char *boot_devices,
- uint32_t kernel_image, uint32_t kernel_size,
- const char *cmdline,
- uint32_t initrd_image, uint32_t initrd_size,
- uint32_t NVRAM_image,
- int width, int height, int depth,
- const uint8_t *macaddr)
+static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
+ const char *arch, ram_addr_t RAM_size,
+ const char *boot_devices,
+ uint32_t kernel_image, uint32_t kernel_size,
+ const char *cmdline,
+ uint32_t initrd_image, uint32_t initrd_size,
+ uint32_t NVRAM_image,
+ int width, int height, int depth,
+ const uint8_t *macaddr)
{
unsigned int i;
uint32_t start, end;
const struct hwdef *hwdef)
{
CPUState *env;
- m48t59_t *nvram;
+ M48t59State *nvram;
unsigned int i;
long initrd_size, kernel_size;
PCIBus *pci_bus, *pci_bus2, *pci_bus3;
return 0;
}
-static int pci_dec_21154_init_device(SysBusDevice *dev)
-{
- UNINState *s;
- int pci_mem_config, pci_mem_data;
-
- /* Uninorth bridge */
- s = FROM_SYSBUS(UNINState, dev);
-
- // XXX: s = &pci_bridge[2];
- pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
- pci_mem_data = pci_host_data_register_mmio(&s->host_state);
- sysbus_init_mmio(dev, 0x1000, pci_mem_config);
- sysbus_init_mmio(dev, 0x1000, pci_mem_data);
- return 0;
-}
-
static int pci_unin_agp_init_device(SysBusDevice *dev)
{
UNINState *s;
return 0;
}
-static int dec_21154_pci_host_init(PCIDevice *d)
-{
- /* pci-to-pci bridge */
- pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
- pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
- d->config[0x08] = 0x05; // revision
- pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
- d->config[0x0C] = 0x08; // cache_line_size
- d->config[0x0D] = 0x20; // latency_timer
- d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
-
- d->config[0x18] = 0x01; // primary_bus
- d->config[0x19] = 0x02; // secondary_bus
- d->config[0x1A] = 0x02; // subordinate_bus
- d->config[0x1B] = 0x20; // secondary_latency_timer
- d->config[0x1C] = 0x11; // io_base
- d->config[0x1D] = 0x01; // io_limit
- d->config[0x20] = 0x00; // memory_base
- d->config[0x21] = 0x80;
- d->config[0x22] = 0x00; // memory_limit
- d->config[0x23] = 0x80;
- d->config[0x24] = 0x01; // prefetchable_memory_base
- d->config[0x25] = 0x80;
- d->config[0x26] = 0xF1; // prefectchable_memory_limit
- d->config[0x27] = 0x7F;
- // d->config[0x34] = 0xdc // capabilities_pointer
- return 0;
-}
-
static int unin_agp_pci_host_init(PCIDevice *d)
{
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
.init = unin_main_pci_host_init,
};
-static PCIDeviceInfo dec_21154_pci_host_info = {
- .qdev.name = "dec-21154",
- .qdev.size = sizeof(PCIDevice),
- .init = dec_21154_pci_host_init,
- .header_type = PCI_HEADER_TYPE_BRIDGE,
-};
-
static PCIDeviceInfo unin_agp_pci_host_info = {
.qdev.name = "uni-north-agp",
.qdev.size = sizeof(PCIDevice),
sysbus_register_dev("uni-north", sizeof(UNINState),
pci_unin_main_init_device);
pci_qdev_register(&unin_main_pci_host_info);
- sysbus_register_dev("dec-21154", sizeof(UNINState),
- pci_dec_21154_init_device);
- pci_qdev_register(&dec_21154_pci_host_info);
sysbus_register_dev("uni-north-agp", sizeof(UNINState),
pci_unin_agp_init_device);
pci_qdev_register(&unin_agp_pci_host_info);
//#define OHCI_TIME_WARP 1
#ifdef DEBUG_OHCI
-#define dprintf printf
+#define DPRINTF printf
#else
-#define dprintf(...)
+#define DPRINTF(...)
#endif
/* Number of Downstream Ports on the root hub. */
/* send the attach message */
usb_send_msg(dev, USB_MSG_ATTACH);
- dprintf("usb-ohci: Attached port %d\n", port1->index);
+ DPRINTF("usb-ohci: Attached port %d\n", port1->index);
} else {
/* set connect status */
if (port->ctrl & OHCI_PORT_CCS) {
usb_send_msg(dev, USB_MSG_DETACH);
}
port->port.dev = NULL;
- dprintf("usb-ohci: Detached port %d\n", port1->index);
+ DPRINTF("usb-ohci: Detached port %d\n", port1->index);
}
if (old_state != port->ctrl)
usb_cancel_packet(&ohci->usb_packet);
ohci->async_td = 0;
}
- dprintf("usb-ohci: Reset %s\n", ohci->name);
+ DPRINTF("usb-ohci: Reset %s\n", ohci->name);
}
/* Get an array of dwords from main memory */
{
OHCIState *ohci = opaque;
#ifdef DEBUG_PACKET
- dprintf("Async packet complete\n");
+ DPRINTF("Async packet complete\n");
#endif
ohci->async_complete = 1;
ohci_process_lists(ohci, 1);
#endif
if (relative_frame_number < 0) {
- dprintf("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
+ DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
return 1;
} else if (relative_frame_number > frame_count) {
/* ISO TD expired - retire the TD to the Done Queue and continue with
the next ISO TD of the same ED */
- dprintf("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
+ DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
frame_count);
OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
ed->head &= ~OHCI_DPTR_MASK;
completion = (addr == ohci->async_td);
if (completion && !ohci->async_complete) {
#ifdef DEBUG_PACKET
- dprintf("Skipping async TD\n");
+ DPRINTF("Skipping async TD\n");
#endif
return 1;
}
flag_r = (td.flags & OHCI_TD_R) != 0;
#ifdef DEBUG_PACKET
- dprintf(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
+ DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
addr, len, str, flag_r, td.cbp, td.be);
if (len > 0 && dir != OHCI_TD_DIR_IN) {
- dprintf(" data:");
+ DPRINTF(" data:");
for (i = 0; i < len; i++)
printf(" %.2x", ohci->usb_buf[i]);
- dprintf("\n");
+ DPRINTF("\n");
}
#endif
if (completion) {
timely manner.
*/
#ifdef DEBUG_PACKET
- dprintf("Too many pending packets\n");
+ DPRINTF("Too many pending packets\n");
#endif
return 1;
}
break;
}
#ifdef DEBUG_PACKET
- dprintf("ret=%d\n", ret);
+ DPRINTF("ret=%d\n", ret);
#endif
if (ret == USB_RET_ASYNC) {
ohci->async_td = addr;
if (dir == OHCI_TD_DIR_IN) {
ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
#ifdef DEBUG_PACKET
- dprintf(" data:");
+ DPRINTF(" data:");
for (i = 0; i < ret; i++)
printf(" %.2x", ohci->usb_buf[i]);
- dprintf("\n");
+ DPRINTF("\n");
#endif
} else {
ret = len;
ed->head |= OHCI_ED_C;
} else {
if (ret >= 0) {
- dprintf("usb-ohci: Underrun\n");
+ DPRINTF("usb-ohci: Underrun\n");
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
} else {
switch (ret) {
case USB_RET_NODEV:
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
case USB_RET_NAK:
- dprintf("usb-ohci: got NAK\n");
+ DPRINTF("usb-ohci: got NAK\n");
return 1;
case USB_RET_STALL:
- dprintf("usb-ohci: got STALL\n");
+ DPRINTF("usb-ohci: got STALL\n");
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
break;
case USB_RET_BABBLE:
- dprintf("usb-ohci: got BABBLE\n");
+ DPRINTF("usb-ohci: got BABBLE\n");
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
break;
default:
while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
#ifdef DEBUG_PACKET
- dprintf("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
+ DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
"h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
{
if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head)
- dprintf("usb-ohci: head %x, cur %x\n",
+ DPRINTF("usb-ohci: head %x, cur %x\n",
ohci->ctrl_head, ohci->ctrl_cur);
if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
ohci->ctrl_cur = 0;
return 0;
}
- dprintf("usb-ohci: %s: USB Operational\n", ohci->name);
+ DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
ohci_sof(ohci);
val &= OHCI_FMI_FI;
if (val != ohci->fi) {
- dprintf("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
+ DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
ohci->name, ohci->fi, ohci->fi);
}
break;
case OHCI_USB_SUSPEND:
ohci_bus_stop(ohci);
- dprintf("usb-ohci: %s: USB Suspended\n", ohci->name);
+ DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
break;
case OHCI_USB_RESUME:
- dprintf("usb-ohci: %s: USB Resume\n", ohci->name);
+ DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
break;
case OHCI_USB_RESET:
ohci_reset(ohci);
- dprintf("usb-ohci: %s: USB Reset\n", ohci->name);
+ DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
break;
}
}
for (i = 0; i < ohci->num_ports; i++)
ohci_port_power(ohci, i, 0);
- dprintf("usb-ohci: powered down all ports\n");
+ DPRINTF("usb-ohci: powered down all ports\n");
}
if (val & OHCI_RHS_LPSC) {
for (i = 0; i < ohci->num_ports; i++)
ohci_port_power(ohci, i, 1);
- dprintf("usb-ohci: powered up all ports\n");
+ DPRINTF("usb-ohci: powered up all ports\n");
}
if (val & OHCI_RHS_DRWE)
ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS))
- dprintf("usb-ohci: port %d: SUSPEND\n", portnum);
+ DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
- dprintf("usb-ohci: port %d: RESET\n", portnum);
+ DPRINTF("usb-ohci: port %d: RESET\n", portnum);
usb_send_msg(port->port.dev, USB_MSG_RESET);
port->ctrl &= ~OHCI_PORT_PRS;
/* ??? Should this also set OHCI_PORT_PESC. */
usb_bit_time = 1;
}
#endif
- dprintf("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
+ DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
usb_frame_time, usb_bit_time);
}
#define NB_PORTS 2
#ifdef DEBUG
-#define dprintf printf
+#define DPRINTF printf
static const char *pid2str(int pid)
{
}
#else
-#define dprintf(...)
+#define DPRINTF(...)
#endif
#ifdef DEBUG_DUMP_DATA
static void uhci_async_cancel(UHCIState *s, UHCIAsync *async)
{
- dprintf("uhci: cancel td 0x%x token 0x%x done %u\n",
+ DPRINTF("uhci: cancel td 0x%x token 0x%x done %u\n",
async->td, async->token, async->done);
if (!async->done)
int i;
UHCIPort *port;
- dprintf("uhci: full reset\n");
+ DPRINTF("uhci: full reset\n");
pci_conf = s->dev.config;
UHCIState *s = opaque;
addr &= 0x1f;
- dprintf("uhci: writew port=0x%04x val=0x%04x\n", addr, val);
+ DPRINTF("uhci: writew port=0x%04x val=0x%04x\n", addr, val);
switch(addr) {
case 0x00:
break;
}
- dprintf("uhci: readw port=0x%04x val=0x%04x\n", addr, val);
+ DPRINTF("uhci: readw port=0x%04x val=0x%04x\n", addr, val);
return val;
}
UHCIState *s = opaque;
addr &= 0x1f;
- dprintf("uhci: writel port=0x%04x val=0x%08x\n", addr, val);
+ DPRINTF("uhci: writel port=0x%04x val=0x%08x\n", addr, val);
switch(addr) {
case 0x08:
{
int i, ret;
- dprintf("uhci: packet enter. pid %s addr 0x%02x ep %d len %d\n",
+ DPRINTF("uhci: packet enter. pid %s addr 0x%02x ep %d len %d\n",
pid2str(p->pid), p->devaddr, p->devep, p->len);
if (p->pid == USB_TOKEN_OUT || p->pid == USB_TOKEN_SETUP)
dump_data(p->data, p->len);
ret = dev->info->handle_packet(dev, p);
}
- dprintf("uhci: packet exit. ret %d len %d\n", ret, p->len);
+ DPRINTF("uhci: packet exit. ret %d len %d\n", ret, p->len);
if (p->pid == USB_TOKEN_IN && ret > 0)
dump_data(p->data, ret);
if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
*int_mask |= 0x02;
/* short packet: do not update QH */
- dprintf("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token);
+ DPRINTF("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token);
return 1;
}
}
UHCIState *s = opaque;
UHCIAsync *async = (UHCIAsync *) packet;
- dprintf("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token);
+ DPRINTF("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token);
async->done = 1;
frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
- dprintf("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr);
+ DPRINTF("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr);
cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4);
le32_to_cpus(&link);
* are already done, and async completion handler will re-process
* the frame when something is ready.
*/
- dprintf("uhci: detected loop. qh 0x%x\n", link);
+ DPRINTF("uhci: detected loop. qh 0x%x\n", link);
break;
}
le32_to_cpus(&qh.link);
le32_to_cpus(&qh.el_link);
- dprintf("uhci: QH 0x%x load. link 0x%x elink 0x%x\n",
+ DPRINTF("uhci: QH 0x%x load. link 0x%x elink 0x%x\n",
link, qh.link, qh.el_link);
if (!is_valid(qh.el_link)) {
le32_to_cpus(&td.token);
le32_to_cpus(&td.buffer);
- dprintf("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
+ DPRINTF("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
link, td.link, td.ctrl, td.token, curr_qh);
old_td_ctrl = td.ctrl;
}
if (ret == 2 || ret == 1) {
- dprintf("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
+ DPRINTF("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
link, ret == 2 ? "pend" : "skip",
td.link, td.ctrl, td.token, curr_qh);
/* completed TD */
- dprintf("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
+ DPRINTF("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
link, td.link, td.ctrl, td.token, curr_qh);
link = td.link;
if (!depth_first(link)) {
/* done with this QH */
- dprintf("uhci: QH 0x%x done. link 0x%x elink 0x%x\n",
+ DPRINTF("uhci: QH 0x%x done. link 0x%x elink 0x%x\n",
curr_qh, qh.link, qh.el_link);
curr_qh = 0;
/* set hchalted bit in status - UHCI11D 2.1.2 */
s->status |= UHCI_STS_HCHALTED;
- dprintf("uhci: halted\n");
+ DPRINTF("uhci: halted\n");
return;
}
/* Start new frame */
s->frnum = (s->frnum + 1) & 0x7ff;
- dprintf("uhci: new frame #%u\n" , s->frnum);
+ DPRINTF("uhci: new frame #%u\n" , s->frnum);
uhci_async_validate_begin(s);
#include "isa.h"
#include "pc.h"
#include "sysemu.h"
+#include "kvm.h"
//#define VMPORT_DEBUG
unsigned char command;
uint32_t eax;
+ cpu_synchronize_state(env);
+
eax = env->regs[R_EAX];
if (eax != VMPORT_MAGIC)
return eax;
.rela.fini : { *(.rela.fini) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
+ .rel.plt :
+ {
+ *(.rel.plt)
+ PROVIDE_HIDDEN (__rel_iplt_start = .);
+ *(.rel.iplt)
+ PROVIDE_HIDDEN (__rel_iplt_end = .);
+ }
+ .rela.plt :
+ {
+ *(.rela.plt)
+ PROVIDE_HIDDEN (__rela_iplt_start = .);
+ *(.rela.iplt)
+ PROVIDE_HIDDEN (__rela_iplt_end = .);
+ }
.init : { *(.init) } =0x47ff041f
.text :
{
KVMSlot slots[32];
int fd;
int vmfd;
- int regs_modified;
int coalesced_mmio;
+#ifdef KVM_CAP_COALESCED_MMIO
+ struct kvm_coalesced_mmio_ring *coalesced_mmio_ring;
+#endif
int broken_set_mem_region;
int migration_log;
int vcpu_events;
goto err;
}
+#ifdef KVM_CAP_COALESCED_MMIO
+ if (s->coalesced_mmio && !s->coalesced_mmio_ring)
+ s->coalesced_mmio_ring = (void *) env->kvm_run +
+ s->coalesced_mmio * PAGE_SIZE;
+#endif
+
ret = kvm_arch_init_vcpu(env);
if (ret == 0) {
qemu_register_reset(kvm_reset_vcpu, env);
goto err;
}
+ s->coalesced_mmio = 0;
#ifdef KVM_CAP_COALESCED_MMIO
s->coalesced_mmio = kvm_check_extension(s, KVM_CAP_COALESCED_MMIO);
-#else
- s->coalesced_mmio = 0;
+ s->coalesced_mmio_ring = NULL;
#endif
s->broken_set_mem_region = 1;
return 1;
}
-static void kvm_run_coalesced_mmio(CPUState *env, struct kvm_run *run)
+void kvm_flush_coalesced_mmio_buffer(void)
{
#ifdef KVM_CAP_COALESCED_MMIO
KVMState *s = kvm_state;
- if (s->coalesced_mmio) {
- struct kvm_coalesced_mmio_ring *ring;
-
- ring = (void *)run + (s->coalesced_mmio * TARGET_PAGE_SIZE);
+ if (s->coalesced_mmio_ring) {
+ struct kvm_coalesced_mmio_ring *ring = s->coalesced_mmio_ring;
while (ring->first != ring->last) {
struct kvm_coalesced_mmio *ent;
void kvm_cpu_synchronize_state(CPUState *env)
{
- if (!env->kvm_state->regs_modified) {
+ if (!env->kvm_vcpu_dirty) {
kvm_arch_get_registers(env);
- env->kvm_state->regs_modified = 1;
+ env->kvm_vcpu_dirty = 1;
}
}
break;
}
- if (env->kvm_state->regs_modified) {
+ if (env->kvm_vcpu_dirty) {
kvm_arch_put_registers(env);
- env->kvm_state->regs_modified = 0;
+ env->kvm_vcpu_dirty = 0;
}
kvm_arch_pre_run(env, run);
abort();
}
- kvm_run_coalesced_mmio(env, run);
+ kvm_flush_coalesced_mmio_buffer();
ret = 0; /* exit loop */
switch (run->exit_reason) {
struct kvm_set_guest_debug_data *dbg_data = data;
CPUState *env = dbg_data->env;
- if (env->kvm_state->regs_modified) {
+ if (env->kvm_vcpu_dirty) {
kvm_arch_put_registers(env);
- env->kvm_state->regs_modified = 0;
+ env->kvm_vcpu_dirty = 0;
}
dbg_data->err = kvm_vcpu_ioctl(env, KVM_SET_GUEST_DEBUG, &dbg_data->dbg);
}
int kvm_coalesce_mmio_region(target_phys_addr_t start, ram_addr_t size);
int kvm_uncoalesce_mmio_region(target_phys_addr_t start, ram_addr_t size);
+void kvm_flush_coalesced_mmio_buffer(void);
int kvm_insert_breakpoint(CPUState *current_env, target_ulong addr,
target_ulong len, int type);
//#define DEBUG_MIGRATION_EXEC
#ifdef DEBUG_MIGRATION_EXEC
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do { printf("migration-exec: " fmt, ## __VA_ARGS__); } while (0)
#else
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do { } while (0)
#endif
static int exec_close(FdMigrationState *s)
{
- dprintf("exec_close\n");
+ DPRINTF("exec_close\n");
if (s->opaque) {
qemu_fclose(s->opaque);
s->opaque = NULL;
f = popen(command, "w");
if (f == NULL) {
- dprintf("Unable to popen exec target\n");
+ DPRINTF("Unable to popen exec target\n");
goto err_after_alloc;
}
s->fd = fileno(f);
if (s->fd == -1) {
- dprintf("Unable to retrieve file descriptor for popen'd handle\n");
+ DPRINTF("Unable to retrieve file descriptor for popen'd handle\n");
goto err_after_open;
}
goto err;
}
qemu_announce_self();
- dprintf("successfully loaded vm state\n");
+ DPRINTF("successfully loaded vm state\n");
/* we've successfully migrated, close the fd */
qemu_set_fd_handler2(qemu_stdio_fd(f), NULL, NULL, NULL, NULL);
if (autostart)
{
QEMUFile *f;
- dprintf("Attempting to start an incoming migration\n");
+ DPRINTF("Attempting to start an incoming migration\n");
f = qemu_popen_cmd(command, "r");
if(f == NULL) {
- dprintf("Unable to apply qemu wrapper to popen file\n");
+ DPRINTF("Unable to apply qemu wrapper to popen file\n");
return -errno;
}
//#define DEBUG_MIGRATION_FD
#ifdef DEBUG_MIGRATION_FD
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do { printf("migration-fd: " fmt, ## __VA_ARGS__); } while (0)
#else
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do { } while (0)
#endif
static int fd_close(FdMigrationState *s)
{
- dprintf("fd_close\n");
+ DPRINTF("fd_close\n");
if (s->fd != -1) {
close(s->fd);
s->fd = -1;
s->fd = monitor_get_fd(mon, fdname);
if (s->fd == -1) {
- dprintf("fd_migration: invalid file descriptor identifier\n");
+ DPRINTF("fd_migration: invalid file descriptor identifier\n");
goto err_after_alloc;
}
if (fcntl(s->fd, F_SETFL, O_NONBLOCK) == -1) {
- dprintf("Unable to set nonblocking mode on file descriptor\n");
+ DPRINTF("Unable to set nonblocking mode on file descriptor\n");
goto err_after_open;
}
goto err;
}
qemu_announce_self();
- dprintf("successfully loaded vm state\n");
+ DPRINTF("successfully loaded vm state\n");
/* we've successfully migrated, close the fd */
qemu_set_fd_handler2(qemu_stdio_fd(f), NULL, NULL, NULL, NULL);
if (autostart)
int fd;
QEMUFile *f;
- dprintf("Attempting to start an incoming migration via fd\n");
+ DPRINTF("Attempting to start an incoming migration via fd\n");
fd = strtol(infd, NULL, 0);
f = qemu_fdopen(fd, "rb");
if(f == NULL) {
- dprintf("Unable to apply qemu wrapper to file descriptor\n");
+ DPRINTF("Unable to apply qemu wrapper to file descriptor\n");
return -errno;
}
//#define DEBUG_MIGRATION_TCP
#ifdef DEBUG_MIGRATION_TCP
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do { printf("migration-tcp: " fmt, ## __VA_ARGS__); } while (0)
#else
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do { } while (0)
#endif
static int tcp_close(FdMigrationState *s)
{
- dprintf("tcp_close\n");
+ DPRINTF("tcp_close\n");
if (s->fd != -1) {
close(s->fd);
s->fd = -1;
int val, ret;
socklen_t valsize = sizeof(val);
- dprintf("connect completed\n");
+ DPRINTF("connect completed\n");
do {
ret = getsockopt(s->fd, SOL_SOCKET, SO_ERROR, (void *) &val, &valsize);
} while (ret == -1 && (s->get_error(s)) == EINTR);
if (val == 0)
migrate_fd_connect(s);
else {
- dprintf("error connecting %d\n", val);
+ DPRINTF("error connecting %d\n", val);
migrate_fd_error(s);
}
}
} while (ret == -EINTR);
if (ret < 0 && ret != -EINPROGRESS && ret != -EWOULDBLOCK) {
- dprintf("connect failed\n");
+ DPRINTF("connect failed\n");
close(s->fd);
qemu_free(s);
return NULL;
c = qemu_accept(s, (struct sockaddr *)&addr, &addrlen);
} while (c == -1 && socket_error() == EINTR);
- dprintf("accepted migration\n");
+ DPRINTF("accepted migration\n");
if (c == -1) {
fprintf(stderr, "could not accept migration connection\n");
goto out_fopen;
}
qemu_announce_self();
- dprintf("successfully loaded vm state\n");
+ DPRINTF("successfully loaded vm state\n");
/* we've successfully migrated, close the server socket */
qemu_set_fd_handler2(s, NULL, NULL, NULL, NULL);
//#define DEBUG_MIGRATION_UNIX
#ifdef DEBUG_MIGRATION_UNIX
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do { printf("migration-unix: " fmt, ## __VA_ARGS__); } while (0)
#else
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do { } while (0)
#endif
static int unix_close(FdMigrationState *s)
{
- dprintf("unix_close\n");
+ DPRINTF("unix_close\n");
if (s->fd != -1) {
close(s->fd);
s->fd = -1;
int val, ret;
socklen_t valsize = sizeof(val);
- dprintf("connect completed\n");
+ DPRINTF("connect completed\n");
do {
ret = getsockopt(s->fd, SOL_SOCKET, SO_ERROR, (void *) &val, &valsize);
} while (ret == -1 && (s->get_error(s)) == EINTR);
if (val == 0)
migrate_fd_connect(s);
else {
- dprintf("error connecting %d\n", val);
+ DPRINTF("error connecting %d\n", val);
migrate_fd_error(s);
}
}
s->bandwidth_limit = bandwidth_limit;
s->fd = qemu_socket(PF_UNIX, SOCK_STREAM, 0);
if (s->fd < 0) {
- dprintf("Unable to open socket");
+ DPRINTF("Unable to open socket");
goto err_after_alloc;
}
} while (ret == -EINTR);
if (ret < 0 && ret != -EINPROGRESS && ret != -EWOULDBLOCK) {
- dprintf("connect failed\n");
+ DPRINTF("connect failed\n");
goto err_after_open;
}
c = qemu_accept(s, (struct sockaddr *)&addr, &addrlen);
} while (c == -1 && socket_error() == EINTR);
- dprintf("accepted migration\n");
+ DPRINTF("accepted migration\n");
if (c == -1) {
fprintf(stderr, "could not accept migration connection\n");
goto out_fopen;
}
qemu_announce_self();
- dprintf("successfully loaded vm state\n");
+ DPRINTF("successfully loaded vm state\n");
/* we've successfully migrated, close the server socket */
qemu_set_fd_handler2(s, NULL, NULL, NULL, NULL);
struct sockaddr_un un;
int sock;
- dprintf("Attempting to start an incoming migration\n");
+ DPRINTF("Attempting to start an incoming migration\n");
sock = qemu_socket(PF_UNIX, SOCK_STREAM, 0);
if (sock < 0) {
//#define DEBUG_MIGRATION
#ifdef DEBUG_MIGRATION
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do { printf("migration: " fmt, ## __VA_ARGS__); } while (0)
#else
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do { } while (0)
#endif
{
s->mon = mon;
if (monitor_suspend(mon) == 0) {
- dprintf("suspending monitor\n");
+ DPRINTF("suspending monitor\n");
} else {
monitor_printf(mon, "terminal does not allow synchronous "
"migration, continuing detached\n");
void migrate_fd_error(FdMigrationState *s)
{
- dprintf("setting error state\n");
+ DPRINTF("setting error state\n");
s->state = MIG_STATE_ERROR;
migrate_fd_cleanup(s);
}
qemu_set_fd_handler2(s->fd, NULL, NULL, NULL, NULL);
if (s->file) {
- dprintf("closing file\n");
+ DPRINTF("closing file\n");
qemu_fclose(s->file);
s->file = NULL;
}
migrate_fd_wait_for_unfreeze,
migrate_fd_close);
- dprintf("beginning savevm\n");
+ DPRINTF("beginning savevm\n");
ret = qemu_savevm_state_begin(s->mon, s->file, s->mig_state.blk,
s->mig_state.shared);
if (ret < 0) {
- dprintf("failed, %d\n", ret);
+ DPRINTF("failed, %d\n", ret);
migrate_fd_error(s);
return;
}
FdMigrationState *s = opaque;
if (s->state != MIG_STATE_ACTIVE) {
- dprintf("put_ready returning because of non-active state\n");
+ DPRINTF("put_ready returning because of non-active state\n");
return;
}
- dprintf("iterate\n");
+ DPRINTF("iterate\n");
if (qemu_savevm_state_iterate(s->mon, s->file) == 1) {
int state;
int old_vm_running = vm_running;
- dprintf("done iterating\n");
+ DPRINTF("done iterating\n");
vm_stop(0);
qemu_aio_flush();
if (s->state != MIG_STATE_ACTIVE)
return;
- dprintf("cancelling migration\n");
+ DPRINTF("cancelling migration\n");
s->state = MIG_STATE_CANCELLED;
qemu_savevm_state_cancel(s->mon, s->file);
{
FdMigrationState *s = migrate_to_fms(mig_state);
- dprintf("releasing state\n");
+ DPRINTF("releasing state\n");
if (s->state == MIG_STATE_ACTIVE) {
s->state = MIG_STATE_CANCELLED;
FdMigrationState *s = opaque;
int ret;
- dprintf("wait for unfreeze\n");
+ DPRINTF("wait for unfreeze\n");
if (s->state != MIG_STATE_ACTIVE)
return;
/* Please keep in synch with qemu-img.texi */
static void help(void)
{
- printf("qemu-img version " QEMU_VERSION ", Copyright (c) 2004-2008 Fabrice Bellard\n"
+ const char *help_msg =
+ "qemu-img version " QEMU_VERSION ", Copyright (c) 2004-2008 Fabrice Bellard\n"
"usage: qemu-img command [command options]\n"
"QEMU disk image utility\n"
"\n"
" '-a' applies a snapshot (revert disk to saved state)\n"
" '-c' creates a snapshot\n"
" '-d' deletes a snapshot\n"
- " '-l' lists all snapshots in the given image\n"
- );
- printf("\nSupported formats:");
+ " '-l' lists all snapshots in the given image\n";
+
+ printf("%s\nSupported formats:", help_msg);
bdrv_iterate_format(format_print, NULL);
printf("\n");
exit(1);
ETEXI
DEF("m", HAS_ARG, QEMU_OPTION_m,
- "-m megs set virtual RAM size to megs MB [default=%d]\n")
+ "-m megs set virtual RAM size to megs MB [default="
+ stringify(DEFAULT_RAM_SIZE) "]\n")
STEXI
@item -m @var{megs}
Set virtual RAM size to @var{megs} megabytes. Default is 128 MiB. Optionally,
ETEXI
DEF("uuid", HAS_ARG, QEMU_OPTION_uuid,
- "-uuid %%08x-%%04x-%%04x-%%04x-%%012x\n"
+ "-uuid %08x-%04x-%04x-%04x-%012x\n"
" specify machine UUID\n")
STEXI
@item -uuid @var{uuid}
DEF("smbios", HAS_ARG, QEMU_OPTION_smbios,
"-smbios file=binary\n"
" load SMBIOS entry from binary file\n"
- "-smbios type=0[,vendor=str][,version=str][,date=str][,release=%%d.%%d]\n"
+ "-smbios type=0[,vendor=str][,version=str][,date=str][,release=%d.%d]\n"
" specify SMBIOS type 0 fields\n"
"-smbios type=1[,manufacturer=str][,product=str][,version=str][,serial=str]\n"
" [,uuid=uuid][,sku=str][,family=str]\n"
#else
"-net tap[,vlan=n][,name=str][,fd=h][,ifname=name][,script=file][,downscript=dfile][,sndbuf=nbytes][,vnet_hdr=on|off]\n"
" connect the host TAP network interface to VLAN 'n' and use the\n"
- " network scripts 'file' (default=%s)\n"
- " and 'dfile' (default=%s)\n"
+ " network scripts 'file' (default=" DEFAULT_NETWORK_SCRIPT ")\n"
+ " and 'dfile' (default=" DEFAULT_NETWORK_DOWN_SCRIPT ")\n"
" use '[down]script=no' to disable script execution\n"
" use 'fd=h' to connect to an already opened TAP interface\n"
" use 'sndbuf=nbytes' to limit the size of the send buffer (the\n"
ETEXI
DEF("s", 0, QEMU_OPTION_s, \
- "-s shorthand for -gdb tcp::%s\n")
+ "-s shorthand for -gdb tcp::" DEFAULT_GDBSTUB_PORT "\n")
STEXI
@item -s
Shorthand for -gdb tcp::1234, i.e. open a gdbserver on TCP port 1234
ETEXI
DEF("d", HAS_ARG, QEMU_OPTION_d, \
- "-d item1,... output log to %s (use -d ? for a list of log items)\n")
+ "-d item1,... output log to /tmp/qemu.log (use -d ? for a list of log items)\n")
STEXI
@item -d
Output log in /tmp/qemu.log
#define IS_ESC 1
#define IS_CSI 2
+#undef printf
#define printf do_not_use_printf
void readline_show_prompt(ReadLineState *rs)
static const uint8_t rfc1533_cookie[] = { RFC1533_COOKIE };
#ifdef DEBUG
-#define dprintf(fmt, ...) \
+#define DPRINTF(fmt, ...) \
do if (slirp_debug & DBG_CALL) { fprintf(dfd, fmt, ## __VA_ARGS__); fflush(dfd); } while (0)
#else
-#define dprintf(fmt, ...)
+#define DPRINTF(fmt, ...)
#endif
static BOOTPClient *get_new_addr(Slirp *slirp, struct in_addr *paddr,
if (p >= p_end)
break;
len = *p++;
- dprintf("dhcp: tag=%d len=%d\n", tag, len);
+ DPRINTF("dhcp: tag=%d len=%d\n", tag, len);
switch(tag) {
case RFC2132_MSG_TYPE:
/* extract exact DHCP msg type */
dhcp_decode(bp, &dhcp_msg_type, &preq_addr);
- dprintf("bootp packet op=%d msgtype=%d", bp->bp_op, dhcp_msg_type);
+ DPRINTF("bootp packet op=%d msgtype=%d", bp->bp_op, dhcp_msg_type);
if (preq_addr)
- dprintf(" req_addr=%08x\n", ntohl(preq_addr->s_addr));
+ DPRINTF(" req_addr=%08x\n", ntohl(preq_addr->s_addr));
else
- dprintf("\n");
+ DPRINTF("\n");
if (dhcp_msg_type == 0)
dhcp_msg_type = DHCPREQUEST; /* Force reply for old BOOTP clients */
new_addr:
bc = get_new_addr(slirp, &daddr.sin_addr, slirp->client_ethaddr);
if (!bc) {
- dprintf("no address left\n");
+ DPRINTF("no address left\n");
return;
}
}
q += 4;
if (bc) {
- dprintf("%s addr=%08x\n",
+ DPRINTF("%s addr=%08x\n",
(dhcp_msg_type == DHCPDISCOVER) ? "offered" : "ack'ed",
ntohl(daddr.sin_addr.s_addr));
} else {
static const char nak_msg[] = "requested address not available";
- dprintf("nak'ed addr=%08x\n", ntohl(preq_addr->s_addr));
+ DPRINTF("nak'ed addr=%08x\n", ntohl(preq_addr->s_addr));
*q++ = RFC2132_MSG_TYPE;
*q++ = 1;
break;
case R_EDX:
ret = cpuid->entries[i].edx;
- if (function == 0x80000001) {
+ switch (function) {
+ case 1:
+ /* KVM before 2.6.30 misreports the following features */
+ ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
+ break;
+ case 0x80000001:
/* On Intel, kvm returns cpuid according to the Intel spec,
* so add missing bits according to the AMD spec:
*/
cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
ret |= cpuid_1_edx & 0xdfeff7ff;
+ break;
}
break;
}
events.sipi_vector = env->sipi_vector;
+ events.flags =
+ KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
+
return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
#else
return 0;
ot = dflag + OT_WORD;
modrm = ldub_code(s->pc++);
- mod = (modrm >> 6) & 3;
- rm = (modrm & 7) | REX_B(s);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
void do_interrupt (CPUState *env);
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
-target_phys_addr_t do_translate_address (CPUState *env, target_ulong address,
- int rw);
+target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address,
+ int rw);
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
}
#if !defined(CONFIG_USER_ONLY)
-target_phys_addr_t do_translate_address(CPUState *env, target_ulong address, int rw)
+target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
{
target_phys_addr_t physical;
int prot;
address, rw, access_type);
if (ret != TLBRET_MATCH) {
raise_mmu_exception(env, address, rw, ret);
- cpu_loop_exit();
+ return -1LL;
+ } else {
+ return physical;
}
-
- return physical;
}
#endif
#endif
#ifndef CONFIG_USER_ONLY
+
+static inline target_phys_addr_t do_translate_address(target_ulong address, int rw)
+{
+ target_phys_addr_t lladdr;
+
+ lladdr = cpu_mips_translate_address(env, address, rw);
+
+ if (lladdr == -1LL) {
+ cpu_loop_exit();
+ } else {
+ return lladdr;
+ }
+}
+
#define HELPER_LD_ATOMIC(name, insn) \
target_ulong helper_##name(target_ulong arg, int mem_idx) \
{ \
- env->lladdr = do_translate_address(env, arg, 0); \
+ env->lladdr = do_translate_address(arg, 0); \
env->llval = do_##insn(arg, mem_idx); \
return env->llval; \
}
env->CP0_BadVAddr = arg2; \
helper_raise_exception(EXCP_AdES); \
} \
- if (do_translate_address(env, arg2, 1) == env->lladdr) { \
+ if (do_translate_address(arg2, 1) == env->lladdr) { \
tmp = do_##ld_insn(arg2, mem_idx); \
if (tmp == env->llval) { \
do_##st_insn(arg2, arg1, mem_idx); \
DEF_HELPER_2(divs, tl, tl, tl)
DEF_HELPER_2(divso, tl, tl, tl)
-DEF_HELPER_1(load_dcr, i32, i32);
-DEF_HELPER_2(store_dcr, void, i32, i32)
+DEF_HELPER_1(load_dcr, tl, tl);
+DEF_HELPER_2(store_dcr, void, tl, tl)
DEF_HELPER_1(load_dump_spr, void, i32)
DEF_HELPER_1(store_dump_spr, void, i32)
/* Embedded PowerPC specific helpers */
/* XXX: to be improved to check access rights when in user-mode */
-uint32_t helper_load_dcr (uint32_t dcrn)
+target_ulong helper_load_dcr (target_ulong dcrn)
{
uint32_t val = 0;
qemu_log("No DCR environment\n");
helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
- } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
- qemu_log("DCR read error %d %03x\n", dcrn, dcrn);
+ } else if (unlikely(ppc_dcr_read(env->dcr_env, (uint32_t)dcrn, &val) != 0)) {
+ qemu_log("DCR read error %d %03x\n", (uint32_t)dcrn, (uint32_t)dcrn);
helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
}
return val;
}
-void helper_store_dcr (uint32_t dcrn, uint32_t val)
+void helper_store_dcr (target_ulong dcrn, target_ulong val)
{
if (unlikely(env->dcr_env == NULL)) {
qemu_log("No DCR environment\n");
helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
- } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
- qemu_log("DCR write error %d %03x\n", dcrn, dcrn);
+ } else if (unlikely(ppc_dcr_write(env->dcr_env, (uint32_t)dcrn, (uint32_t)val) != 0)) {
+ qemu_log("DCR write error %d %03x\n", (uint32_t)dcrn, (uint32_t)dcrn);
helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
}
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 1);
tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */
+ tcg_gen_mov_i32(REG(B11_8), addr); /* modify register status */
tcg_temp_free(addr);
}
return;
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 2);
tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2);
+ tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
}
return;
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
+ tcg_gen_mov_i32(REG(B11_8), addr);
}
return;
case 0x6004: /* mov.b @Rm+,Rn */
return;
case 0x6008: /* swap.b Rm,Rn */
{
- TCGv highw, high, low;
- highw = tcg_temp_new();
- tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000);
+ TCGv high, low;
high = tcg_temp_new();
- tcg_gen_ext8u_i32(high, REG(B7_4));
- tcg_gen_shli_i32(high, high, 8);
+ tcg_gen_andi_i32(high, REG(B7_4), 0xffff0000);
low = tcg_temp_new();
- tcg_gen_shri_i32(low, REG(B7_4), 8);
- tcg_gen_ext8u_i32(low, low);
+ tcg_gen_ext16u_i32(low, REG(B7_4));
+ tcg_gen_bswap16_i32(low, low);
tcg_gen_or_i32(REG(B11_8), high, low);
- tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw);
tcg_temp_free(low);
tcg_temp_free(high);
}
{
TCGv high, low;
high = tcg_temp_new();
- tcg_gen_ext16u_i32(high, REG(B7_4));
- tcg_gen_shli_i32(high, high, 16);
+ tcg_gen_shli_i32(high, REG(B7_4), 16);
low = tcg_temp_new();
tcg_gen_shri_i32(low, REG(B7_4), 16);
tcg_gen_ext16u_i32(low, low);
{
TCGv high, low;
high = tcg_temp_new();
- tcg_gen_ext16u_i32(high, REG(B7_4));
- tcg_gen_shli_i32(high, high, 16);
+ tcg_gen_shli_i32(high, REG(B7_4), 16);
low = tcg_temp_new();
tcg_gen_shri_i32(low, REG(B11_8), 16);
tcg_gen_ext16u_i32(low, low);
int label2 = gen_new_label();
int label3 = gen_new_label();
int label4 = gen_new_label();
- TCGv shift = tcg_temp_local_new();
+ TCGv shift;
tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
/* Rm positive, shift to the left */
+ shift = tcg_temp_new();
tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
+ tcg_temp_free(shift);
tcg_gen_br(label4);
/* Rm negative, shift to the right */
gen_set_label(label1);
+ shift = tcg_temp_new();
tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
tcg_gen_not_i32(shift, REG(B7_4));
tcg_gen_andi_i32(shift, shift, 0x1f);
tcg_gen_addi_i32(shift, shift, 1);
tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift);
+ tcg_temp_free(shift);
tcg_gen_br(label4);
/* Rm = -32 */
gen_set_label(label2);
gen_set_label(label3);
tcg_gen_movi_i32(REG(B11_8), 0xffffffff);
gen_set_label(label4);
- tcg_temp_free(shift);
}
return;
case 0x400d: /* shld Rm,Rn */
int label1 = gen_new_label();
int label2 = gen_new_label();
int label3 = gen_new_label();
- TCGv shift = tcg_temp_local_new();
+ TCGv shift;
tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
/* Rm positive, shift to the left */
+ shift = tcg_temp_new();
tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
+ tcg_temp_free(shift);
tcg_gen_br(label3);
/* Rm negative, shift to the right */
gen_set_label(label1);
+ shift = tcg_temp_new();
tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
tcg_gen_not_i32(shift, REG(B7_4));
tcg_gen_andi_i32(shift, shift, 0x1f);
tcg_gen_addi_i32(shift, shift, 1);
tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift);
+ tcg_temp_free(shift);
tcg_gen_br(label3);
/* Rm = -32 */
gen_set_label(label2);
tcg_gen_movi_i32(REG(B11_8), 0);
gen_set_label(label3);
- tcg_temp_free(shift);
}
return;
case 0x3008: /* sub Rm,Rn */
int fr = XREG(B7_4);
tcg_gen_subi_i32(addr, REG(B11_8), 4);
tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
- tcg_gen_subi_i32(addr, REG(B11_8), 8);
+ tcg_gen_subi_i32(addr, addr, 4);
tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx);
tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
addr = tcg_temp_new_i32();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
+ tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
}
return;
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx);
+ tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
}
return;
}
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx);
+ tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
}
return;
#define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \
case stpnum: \
prechk \
{ \
- TCGv addr = tcg_temp_new(); \
+ TCGv addr = tcg_temp_new(); \
tcg_gen_subi_i32(addr, REG(B11_8), 4); \
tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \
+ tcg_gen_mov_i32(REG(B11_8), addr); \
tcg_temp_free(addr); \
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \
} \
return;
LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {})
addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
tcg_gen_qemu_st32(val, addr, ctx->memidx);
+ tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
tcg_temp_free(val);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
}
return;
case 0x00c3: /* movca.l R0,@Rm */
Indicate that the value of t0 won't be used later. It is useful to
force dead code elimination.
+********* Conditional moves
+
+* setcond_i32/i64 cond, dest, t1, t2
+
+dest = (t1 cond t2)
+
+Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0.
+
********* Type conversions
* ext_i32_i64 t0, t1
write(t0, t1 + offset)
Write 8, 16, 32 or 64 bits to host memory.
+********* 64-bit target on 32-bit host support
+
+The following opcodes are internal to TCG. Thus they are to be implemented by
+32-bit host code generators, but are not to be emitted by guest translators.
+They are emitted as needed by inline functions within "tcg-op.h".
+
+* brcond2_i32 cond, t0_low, t0_high, t1_low, t1_high, label
+
+Similar to brcond, except that the 64-bit values T0 and T1
+are formed from two 32-bit arguments.
+
+* add2_i32 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
+* sub2_i32 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
+
+Similar to add/sub, except that the 64-bit inputs T1 and T2 are
+formed from two 32-bit arguments, and the 64-bit output T0
+is returned in two 32-bit outputs.
+
+* mulu2_i32 t0_low, t0_high, t1, t2
+
+Similar to mul, except two 32-bit (unsigned) inputs T1 and T2 yielding
+the full 64-bit product T0. The later is returned in two 32-bit outputs.
+
+* setcond2_i32 cond, dest, t1_low, t1_high, t2_low, t2_high
+
+Similar to setcond, except that the 64-bit values T1 and T2 are
+formed from two 32-bit arguments. The result is a 32-bit value.
+
********* QEMU specific operations
* tb_exit t0
case R_386_PC32:
*(uint32_t *)code_ptr = value - (long)code_ptr;
break;
+ case R_386_PC8:
+ value -= (long)code_ptr;
+ if (value != (int8_t)value) {
+ tcg_abort();
+ }
+ *(uint8_t *)code_ptr = value;
+ break;
default:
tcg_abort();
}
tgen_arithi(s, ARITH_ADD, reg, val, 0);
}
-static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
+/* Use SMALL != 0 to force a short forward branch. */
+static void tcg_out_jxx(TCGContext *s, int opc, int label_index, int small)
{
int32_t val, val1;
TCGLabel *l = &s->labels[label_index];
val = l->u.value - (tcg_target_long)s->code_ptr;
val1 = val - 2;
if ((int8_t)val1 == val1) {
- if (opc == -1)
+ if (opc == -1) {
tcg_out8(s, 0xeb);
- else
+ } else {
tcg_out8(s, 0x70 + opc);
+ }
tcg_out8(s, val1);
} else {
+ if (small) {
+ tcg_abort();
+ }
if (opc == -1) {
tcg_out8(s, 0xe9);
tcg_out32(s, val - 5);
tcg_out32(s, val - 6);
}
}
+ } else if (small) {
+ if (opc == -1) {
+ tcg_out8(s, 0xeb);
+ } else {
+ tcg_out8(s, 0x70 + opc);
+ }
+ tcg_out_reloc(s, s->code_ptr, R_386_PC8, label_index, -1);
+ s->code_ptr += 1;
} else {
if (opc == -1) {
tcg_out8(s, 0xe9);
}
}
-static void tcg_out_brcond(TCGContext *s, int cond,
- TCGArg arg1, TCGArg arg2, int const_arg2,
- int label_index)
+static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2,
+ int const_arg2)
{
if (const_arg2) {
if (arg2 == 0) {
} else {
tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3), arg2, arg1);
}
- tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
+}
+
+static void tcg_out_brcond(TCGContext *s, int cond,
+ TCGArg arg1, TCGArg arg2, int const_arg2,
+ int label_index, int small)
+{
+ tcg_out_cmp(s, arg1, arg2, const_arg2);
+ tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index, small);
}
/* XXX: we implement it at the target level to avoid having to
handle cross basic blocks temporaries */
-static void tcg_out_brcond2(TCGContext *s,
- const TCGArg *args, const int *const_args)
+static void tcg_out_brcond2(TCGContext *s, const TCGArg *args,
+ const int *const_args, int small)
{
int label_next;
label_next = gen_new_label();
switch(args[4]) {
case TCG_COND_EQ:
- tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next);
- tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]);
+ tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2],
+ label_next, 1);
+ tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3],
+ args[5], small);
break;
case TCG_COND_NE:
- tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]);
- tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]);
+ tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2],
+ args[5], small);
+ tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3],
+ args[5], small);
break;
case TCG_COND_LT:
- tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
- tcg_out_jxx(s, JCC_JNE, label_next);
- tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
+ tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3],
+ args[5], small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2],
+ args[5], small);
break;
case TCG_COND_LE:
- tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
- tcg_out_jxx(s, JCC_JNE, label_next);
- tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
+ tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3],
+ args[5], small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2],
+ args[5], small);
break;
case TCG_COND_GT:
- tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
- tcg_out_jxx(s, JCC_JNE, label_next);
- tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
+ tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3],
+ args[5], small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2],
+ args[5], small);
break;
case TCG_COND_GE:
- tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
- tcg_out_jxx(s, JCC_JNE, label_next);
- tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
+ tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3],
+ args[5], small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2],
+ args[5], small);
break;
case TCG_COND_LTU:
- tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
- tcg_out_jxx(s, JCC_JNE, label_next);
- tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
+ tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3],
+ args[5], small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2],
+ args[5], small);
break;
case TCG_COND_LEU:
- tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
- tcg_out_jxx(s, JCC_JNE, label_next);
- tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
+ tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3],
+ args[5], small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2],
+ args[5], small);
break;
case TCG_COND_GTU:
- tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
- tcg_out_jxx(s, JCC_JNE, label_next);
- tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
+ tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3],
+ args[5], small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2],
+ args[5], small);
break;
case TCG_COND_GEU:
- tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
- tcg_out_jxx(s, JCC_JNE, label_next);
- tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
+ tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3],
+ args[5], small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2],
+ args[5], small);
break;
default:
tcg_abort();
tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
}
+static void tcg_out_setcond(TCGContext *s, int cond, TCGArg dest,
+ TCGArg arg1, TCGArg arg2, int const_arg2)
+{
+ tcg_out_cmp(s, arg1, arg2, const_arg2);
+ /* setcc */
+ tcg_out_modrm(s, 0x90 | tcg_cond_to_jcc[cond] | P_EXT, 0, dest);
+ tgen_arithi(s, ARITH_AND, dest, 0xff, 0);
+}
+
+static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
+ const int *const_args)
+{
+ TCGArg new_args[6];
+ int label_true, label_over;
+
+ memcpy(new_args, args+1, 5*sizeof(TCGArg));
+
+ if (args[0] == args[1] || args[0] == args[2]
+ || (!const_args[3] && args[0] == args[3])
+ || (!const_args[4] && args[0] == args[4])) {
+ /* When the destination overlaps with one of the argument
+ registers, don't do anything tricky. */
+ label_true = gen_new_label();
+ label_over = gen_new_label();
+
+ new_args[5] = label_true;
+ tcg_out_brcond2(s, new_args, const_args+1, 1);
+
+ tcg_out_movi(s, TCG_TYPE_I32, args[0], 0);
+ tcg_out_jxx(s, JCC_JMP, label_over, 1);
+ tcg_out_label(s, label_true, (tcg_target_long)s->code_ptr);
+
+ tcg_out_movi(s, TCG_TYPE_I32, args[0], 1);
+ tcg_out_label(s, label_over, (tcg_target_long)s->code_ptr);
+ } else {
+ /* When the destination does not overlap one of the arguments,
+ clear the destination first, jump if cond false, and emit an
+ increment in the true case. This results in smaller code. */
+
+ tcg_out_movi(s, TCG_TYPE_I32, args[0], 0);
+
+ label_over = gen_new_label();
+ new_args[4] = tcg_invert_cond(new_args[4]);
+ new_args[5] = label_over;
+ tcg_out_brcond2(s, new_args, const_args+1, 1);
+
+ tgen_arithi(s, ARITH_ADD, args[0], 1, 0);
+ tcg_out_label(s, label_over, (tcg_target_long)s->code_ptr);
+ }
+}
+
#if defined(CONFIG_SOFTMMU)
#include "../../softmmu_defs.h"
}
break;
case INDEX_op_br:
- tcg_out_jxx(s, JCC_JMP, args[0]);
+ tcg_out_jxx(s, JCC_JMP, args[0], 0);
break;
case INDEX_op_movi_i32:
tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
tcg_out_modrm(s, 0x01 | (ARITH_SBB << 3), args[5], args[1]);
break;
case INDEX_op_brcond_i32:
- tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]);
+ tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
+ args[3], 0);
break;
case INDEX_op_brcond2_i32:
- tcg_out_brcond2(s, args, const_args);
+ tcg_out_brcond2(s, args, const_args, 0);
break;
case INDEX_op_bswap16_i32:
tcg_out_modrm(s, 0xb7 | P_EXT, args[0], args[1]);
break;
+ case INDEX_op_setcond_i32:
+ tcg_out_setcond(s, args[3], args[0], args[1], args[2], const_args[2]);
+ break;
+ case INDEX_op_setcond2_i32:
+ tcg_out_setcond2(s, args, const_args);
+ break;
+
case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0);
break;
{ INDEX_op_ext8u_i32, { "r", "q"} },
{ INDEX_op_ext16u_i32, { "r", "r"} },
+ { INDEX_op_setcond_i32, { "q", "r", "ri" } },
+ { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
+
#if TARGET_LONG_BITS == 32
{ INDEX_op_qemu_ld8u, { "r", "L" } },
{ INDEX_op_qemu_ld8s, { "r", "L" } },
OPC_BEQ = 0x04 << 26,
OPC_BNE = 0x05 << 26,
OPC_ADDIU = 0x09 << 26,
+ OPC_SLTI = 0x0A << 26,
+ OPC_SLTIU = 0x0B << 26,
OPC_ANDI = 0x0C << 26,
OPC_ORI = 0x0D << 26,
OPC_XORI = 0x0E << 26,
reloc_pc16(label_ptr, (tcg_target_long) s->code_ptr);
}
+static void tcg_out_setcond(TCGContext *s, int cond, int ret,
+ int arg1, int arg2)
+{
+ switch (cond) {
+ case TCG_COND_EQ:
+ if (arg1 == 0) {
+ tcg_out_opc_imm(s, OPC_SLTIU, ret, arg2, 1);
+ } else if (arg2 == 0) {
+ tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
+ } else {
+ tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, arg1, arg2);
+ tcg_out_opc_imm(s, OPC_SLTIU, ret, TCG_REG_AT, 1);
+ }
+ break;
+ case TCG_COND_NE:
+ if (arg1 == 0) {
+ tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg2);
+ } else if (arg2 == 0) {
+ tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
+ } else {
+ tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, arg1, arg2);
+ tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, TCG_REG_AT);
+ }
+ break;
+ case TCG_COND_LT:
+ tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
+ break;
+ case TCG_COND_LTU:
+ tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
+ break;
+ case TCG_COND_GE:
+ tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, arg1, arg2);
+ tcg_out_opc_imm(s, OPC_XORI, ret, TCG_REG_AT, 1);
+ break;
+ case TCG_COND_GEU:
+ tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, arg1, arg2);
+ tcg_out_opc_imm(s, OPC_XORI, ret, TCG_REG_AT, 1);
+ break;
+ case TCG_COND_LE:
+ tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, arg2, arg1);
+ tcg_out_opc_imm(s, OPC_XORI, ret, TCG_REG_AT, 1);
+ break;
+ case TCG_COND_LEU:
+ tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, arg2, arg1);
+ tcg_out_opc_imm(s, OPC_XORI, ret, TCG_REG_AT, 1);
+ break;
+ case TCG_COND_GT:
+ tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
+ break;
+ case TCG_COND_GTU:
+ tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
+ break;
+ default:
+ tcg_abort();
+ break;
+ }
+}
+
#if defined(CONFIG_SOFTMMU)
#include "../../softmmu_defs.h"
tcg_out_brcond2(s, args[4], args[0], args[1], args[2], args[3], args[5]);
break;
+ case INDEX_op_setcond_i32:
+ tcg_out_setcond(s, args[3], args[0], args[1], args[2]);
+ break;
+
case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0);
break;
{ INDEX_op_sar_i32, { "r", "rZ", "riZ" } },
{ INDEX_op_brcond_i32, { "rZ", "rZ" } },
+ { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
{ INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } },
{ INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } },
#define STH OPCD(44)
#define STW OPCD(36)
+#define ADDIC OPCD(12)
#define ADDI OPCD(14)
#define ADDIS OPCD(15)
#define ORI OPCD(24)
#define CRANDC XO19(129)
#define CRNAND XO19(225)
#define CROR XO19(449)
+#define CRNOR XO19( 33)
#define EXTSB XO31(954)
#define EXTSH XO31(922)
#define MTSPR XO31(467)
#define SRAWI XO31(824)
#define NEG XO31(104)
+#define MFCR XO31( 19)
+#define CNTLZW XO31( 26)
#define LBZX XO31( 87)
#define LHZX XO31(279)
}
}
-static void tcg_out_brcond (TCGContext *s, int cond,
- TCGArg arg1, TCGArg arg2, int const_arg2,
- int label_index)
-{
- tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
- tcg_out_bc (s, tcg_to_bc[cond], label_index);
-}
-
-/* XXX: we implement it at the target level to avoid having to
- handle cross basic blocks temporaries */
-static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
- const int *const_args)
+static void tcg_out_cr7eq_from_cond (TCGContext *s, const TCGArg *args,
+ const int *const_args)
{
- int cond = args[4], label_index = args[5], op;
+ int cond = args[4], op;
struct { int bit1; int bit2; int cond2; } bits[] = {
[TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
[TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
default:
tcg_abort();
}
+}
+
+static void tcg_out_setcond (TCGContext *s, int cond, TCGArg arg0,
+ TCGArg arg1, TCGArg arg2, int const_arg2)
+{
+ int crop, sh, arg;
- tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), label_index);
+ switch (cond) {
+ case TCG_COND_EQ:
+ if (const_arg2) {
+ if (!arg2) {
+ arg = arg1;
+ }
+ else {
+ arg = 0;
+ if ((uint16_t) arg2 == arg2) {
+ tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
+ }
+ else {
+ tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
+ tcg_out32 (s, XOR | SAB (arg1, 0, 0));
+ }
+ }
+ }
+ else {
+ arg = 0;
+ tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
+ }
+ tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
+ tcg_out32 (s, (RLWINM
+ | RA (arg0)
+ | RS (0)
+ | SH (27)
+ | MB (5)
+ | ME (31)
+ )
+ );
+ break;
+
+ case TCG_COND_NE:
+ if (const_arg2) {
+ if (!arg2) {
+ arg = arg1;
+ }
+ else {
+ arg = 0;
+ if ((uint16_t) arg2 == arg2) {
+ tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
+ }
+ else {
+ tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
+ tcg_out32 (s, XOR | SAB (arg1, 0, 0));
+ }
+ }
+ }
+ else {
+ arg = 0;
+ tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
+ }
+
+ if (arg == arg1 && arg1 == arg0) {
+ tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
+ tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
+ }
+ else {
+ tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
+ tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
+ }
+ break;
+
+ case TCG_COND_GT:
+ case TCG_COND_GTU:
+ sh = 30;
+ crop = 0;
+ goto crtest;
+
+ case TCG_COND_LT:
+ case TCG_COND_LTU:
+ sh = 29;
+ crop = 0;
+ goto crtest;
+
+ case TCG_COND_GE:
+ case TCG_COND_GEU:
+ sh = 31;
+ crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
+ goto crtest;
+
+ case TCG_COND_LE:
+ case TCG_COND_LEU:
+ sh = 31;
+ crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
+ crtest:
+ tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
+ if (crop) tcg_out32 (s, crop);
+ tcg_out32 (s, MFCR | RT (0));
+ tcg_out32 (s, (RLWINM
+ | RA (arg0)
+ | RS (0)
+ | SH (sh)
+ | MB (31)
+ | ME (31)
+ )
+ );
+ break;
+
+ default:
+ tcg_abort ();
+ }
+}
+
+static void tcg_out_setcond2 (TCGContext *s, const TCGArg *args,
+ const int *const_args)
+{
+ tcg_out_cr7eq_from_cond (s, args + 1, const_args + 1);
+ tcg_out32 (s, MFCR | RT (0));
+ tcg_out32 (s, (RLWINM
+ | RA (args[0])
+ | RS (0)
+ | SH (31)
+ | MB (31)
+ | ME (31)
+ )
+ );
+}
+
+static void tcg_out_brcond (TCGContext *s, int cond,
+ TCGArg arg1, TCGArg arg2, int const_arg2,
+ int label_index)
+{
+ tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
+ tcg_out_bc (s, tcg_to_bc[cond], label_index);
+}
+
+/* XXX: we implement it at the target level to avoid having to
+ handle cross basic blocks temporaries */
+static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
+ const int *const_args)
+{
+ tcg_out_cr7eq_from_cond (s, args, const_args);
+ tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]);
}
void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
break;
+ case INDEX_op_setcond_i32:
+ tcg_out_setcond (s, args[3], args[0], args[1], args[2], const_args[2]);
+ break;
+ case INDEX_op_setcond2_i32:
+ tcg_out_setcond2 (s, args, const_args);
+ break;
+
default:
tcg_dump_ops (s, stderr);
tcg_abort ();
{ INDEX_op_neg_i32, { "r", "r" } },
+ { INDEX_op_setcond_i32, { "r", "r", "ri" } },
+ { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
+
#if TARGET_LONG_BITS == 32
{ INDEX_op_qemu_ld8u, { "r", "L" } },
{ INDEX_op_qemu_ld8s, { "r", "L" } },
#define LWA XO58( 2)
#define LWAX XO31(341)
+#define ADDIC OPCD( 12)
#define ADDI OPCD( 14)
#define ADDIS OPCD( 15)
#define ORI OPCD( 24)
#define CRANDC XO19(129)
#define CRNAND XO19(225)
#define CROR XO19(449)
+#define CRNOR XO19( 33)
#define EXTSB XO31(954)
#define EXTSH XO31(922)
#define MTSPR XO31(467)
#define SRAWI XO31(824)
#define NEG XO31(104)
+#define MFCR XO31( 19)
+#define CNTLZW XO31( 26)
+#define CNTLZD XO31( 58)
#define MULLD XO31(233)
#define MULHD XO31( 73)
}
+static void tcg_out_setcond (TCGContext *s, TCGType type, int cond, TCGArg arg0,
+ TCGArg arg1, TCGArg arg2, int const_arg2)
+{
+ int crop, sh, arg;
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ if (const_arg2) {
+ if (!arg2) {
+ arg = arg1;
+ }
+ else {
+ arg = 0;
+ if ((uint16_t) arg2 == arg2) {
+ tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
+ }
+ else {
+ tcg_out_movi (s, type, 0, arg2);
+ tcg_out32 (s, XOR | SAB (arg1, 0, 0));
+ }
+ }
+ }
+ else {
+ arg = 0;
+ tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
+ }
+
+ if (type == TCG_TYPE_I64) {
+ tcg_out32 (s, CNTLZD | RS (arg) | RA (0));
+ tcg_out_rld (s, RLDICL, arg0, 0, 58, 6);
+ }
+ else {
+ tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
+ tcg_out32 (s, (RLWINM
+ | RA (arg0)
+ | RS (0)
+ | SH (27)
+ | MB (5)
+ | ME (31)
+ )
+ );
+ }
+ break;
+
+ case TCG_COND_NE:
+ if (const_arg2) {
+ if (!arg2) {
+ arg = arg1;
+ }
+ else {
+ arg = 0;
+ if ((uint16_t) arg2 == arg2) {
+ tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
+ }
+ else {
+ tcg_out_movi (s, type, 0, arg2);
+ tcg_out32 (s, XOR | SAB (arg1, 0, 0));
+ }
+ }
+ }
+ else {
+ arg = 0;
+ tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
+ }
+
+ if (arg == arg1 && arg1 == arg0) {
+ tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
+ tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
+ }
+ else {
+ tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
+ tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
+ }
+ break;
+
+ case TCG_COND_GT:
+ case TCG_COND_GTU:
+ sh = 30;
+ crop = 0;
+ goto crtest;
+
+ case TCG_COND_LT:
+ case TCG_COND_LTU:
+ sh = 29;
+ crop = 0;
+ goto crtest;
+
+ case TCG_COND_GE:
+ case TCG_COND_GEU:
+ sh = 31;
+ crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
+ goto crtest;
+
+ case TCG_COND_LE:
+ case TCG_COND_LEU:
+ sh = 31;
+ crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
+ crtest:
+ tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, type == TCG_TYPE_I64);
+ if (crop) tcg_out32 (s, crop);
+ tcg_out32 (s, MFCR | RT (0));
+ tcg_out32 (s, (RLWINM
+ | RA (arg0)
+ | RS (0)
+ | SH (sh)
+ | MB (31)
+ | ME (31)
+ )
+ );
+ break;
+
+ default:
+ tcg_abort ();
+ }
+}
+
static void tcg_out_bc (TCGContext *s, int bc, int label_index)
{
TCGLabel *l = &s->labels[label_index];
tcg_out32 (s, c | RS (args[1]) | RA (args[0]));
break;
+ case INDEX_op_setcond_i32:
+ tcg_out_setcond (s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
+ const_args[2]);
+ break;
+ case INDEX_op_setcond_i64:
+ tcg_out_setcond (s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
+ const_args[2]);
+ break;
+
default:
tcg_dump_ops (s, stderr);
tcg_abort ();
{ INDEX_op_ext16s_i64, { "r", "r" } },
{ INDEX_op_ext32s_i64, { "r", "r" } },
+ { INDEX_op_setcond_i32, { "r", "r", "ri" } },
+ { INDEX_op_setcond_i64, { "r", "r", "ri" } },
+
{ -1 },
};
*gen_opparam_ptr++ = GET_TCGV_I64(arg6);
}
+static inline void tcg_gen_op6i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
+ TCGv_i32 arg3, TCGv_i32 arg4,
+ TCGv_i32 arg5, TCGArg arg6)
+{
+ *gen_opc_ptr++ = opc;
+ *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
+ *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
+ *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
+ *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
+ *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
+ *gen_opparam_ptr++ = arg6;
+}
+
+static inline void tcg_gen_op6i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
+ TCGv_i64 arg3, TCGv_i64 arg4,
+ TCGv_i64 arg5, TCGArg arg6)
+{
+ *gen_opc_ptr++ = opc;
+ *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
+ *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
+ *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
+ *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
+ *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
+ *gen_opparam_ptr++ = arg6;
+}
+
static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5,
TCGArg arg6)
tcg_temp_free_i32(t0);
}
+static inline void tcg_gen_setcond_i32(int cond, TCGv_i32 ret,
+ TCGv_i32 arg1, TCGv_i32 arg2)
+{
+ tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
+}
+
+static inline void tcg_gen_setcondi_i32(int cond, TCGv_i32 ret, TCGv_i32 arg1,
+ int32_t arg2)
+{
+ TCGv_i32 t0 = tcg_const_i32(arg2);
+ tcg_gen_setcond_i32(cond, ret, arg1, t0);
+ tcg_temp_free_i32(t0);
+}
+
static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
TCGV_HIGH(arg2), cond, label_index);
}
+static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret,
+ TCGv_i64 arg1, TCGv_i64 arg2)
+{
+ tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
+ TCGV_LOW(arg1), TCGV_HIGH(arg1),
+ TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
+ tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
+}
+
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
TCGv_i64 t0;
tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
}
+static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret,
+ TCGv_i64 arg1, TCGv_i64 arg2)
+{
+ tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
+}
+
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
tcg_temp_free_i64(t0);
}
+static inline void tcg_gen_setcondi_i64(int cond, TCGv_i64 ret, TCGv_i64 arg1,
+ int64_t arg2)
+{
+ TCGv_i64 t0 = tcg_const_i64(arg2);
+ tcg_gen_setcond_i64(cond, ret, arg1, t0);
+ tcg_temp_free_i64(t0);
+}
+
static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
{
TCGv_i64 t0 = tcg_const_i64(arg2);
#define tcg_gen_sari_tl tcg_gen_sari_i64
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
+#define tcg_gen_setcond_tl tcg_gen_setcond_i64
+#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
#define tcg_gen_mul_tl tcg_gen_mul_i64
#define tcg_gen_muli_tl tcg_gen_muli_i64
#define tcg_gen_div_tl tcg_gen_div_i64
#define tcg_gen_sari_tl tcg_gen_sari_i32
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
+#define tcg_gen_setcond_tl tcg_gen_setcond_i32
+#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
#define tcg_gen_mul_tl tcg_gen_mul_i32
#define tcg_gen_muli_tl tcg_gen_muli_i32
#define tcg_gen_div_tl tcg_gen_div_i32
DEF2(mov_i32, 1, 1, 0, 0)
DEF2(movi_i32, 1, 0, 1, 0)
+DEF2(setcond_i32, 1, 2, 1, 0)
/* load/store */
DEF2(ld8u_i32, 1, 1, 1, 0)
DEF2(ld8s_i32, 1, 1, 1, 0)
DEF2(sub2_i32, 2, 4, 0, 0)
DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
DEF2(mulu2_i32, 2, 2, 0, 0)
+DEF2(setcond2_i32, 1, 4, 1, 0)
#endif
#ifdef TCG_TARGET_HAS_ext8s_i32
DEF2(ext8s_i32, 1, 1, 0, 0)
#if TCG_TARGET_REG_BITS == 64
DEF2(mov_i64, 1, 1, 0, 0)
DEF2(movi_i64, 1, 0, 1, 0)
+DEF2(setcond_i64, 1, 2, 1, 0)
/* load/store */
DEF2(ld8u_i64, 1, 1, 1, 0)
DEF2(ld8s_i64, 1, 1, 1, 0)
}
#endif
+
static void tcg_reg_alloc_start(TCGContext *s)
{
int i;
fprintf(outfile, "%s",
tcg_get_arg_str_idx(s, buf, sizeof(buf), args[k++]));
}
- if (c == INDEX_op_brcond_i32
+ switch (c) {
+ case INDEX_op_brcond_i32:
+#if TCG_TARGET_REG_BITS == 32
+ case INDEX_op_brcond2_i32:
+#elif TCG_TARGET_REG_BITS == 64
+ case INDEX_op_brcond_i64:
+#endif
+ case INDEX_op_setcond_i32:
#if TCG_TARGET_REG_BITS == 32
- || c == INDEX_op_brcond2_i32
+ case INDEX_op_setcond2_i32:
#elif TCG_TARGET_REG_BITS == 64
- || c == INDEX_op_brcond_i64
+ case INDEX_op_setcond_i64:
#endif
- ) {
if (args[k] < ARRAY_SIZE(cond_name) && cond_name[args[k]])
fprintf(outfile, ",%s", cond_name[args[k++]]);
else
fprintf(outfile, ",$0x%" TCG_PRIlx, args[k++]);
i = 1;
- }
- else
+ break;
+ default:
i = 0;
+ break;
+ }
for(; i < nb_cargs; i++) {
if (k != 0)
fprintf(outfile, ",");
TCG_COND_GTU,
} TCGCond;
+static inline TCGCond tcg_invert_cond(TCGCond c)
+{
+ return (TCGCond)(c ^ 1);
+}
+
static inline TCGCond tcg_unsigned_cond(TCGCond c)
{
return (c >= TCG_COND_LT && c <= TCG_COND_GT ? c + 4 : c);
}
}
-static void tcg_out_brcond(TCGContext *s, int cond,
- TCGArg arg1, TCGArg arg2, int const_arg2,
- int label_index, int rexw)
+static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2,
+ int const_arg2, int rexw)
{
if (const_arg2) {
if (arg2 == 0) {
/* test r, r */
tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
} else {
- if (rexw)
+ if (rexw) {
tgen_arithi64(s, ARITH_CMP, arg1, arg2);
- else
+ } else {
tgen_arithi32(s, ARITH_CMP, arg1, arg2);
+ }
}
} else {
tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1);
}
+}
+
+static void tcg_out_brcond(TCGContext *s, int cond,
+ TCGArg arg1, TCGArg arg2, int const_arg2,
+ int label_index, int rexw)
+{
+ tcg_out_cmp(s, arg1, arg2, const_arg2, rexw);
tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
}
+static void tcg_out_setcond(TCGContext *s, int cond, TCGArg dest,
+ TCGArg arg1, TCGArg arg2, int const_arg2, int rexw)
+{
+ tcg_out_cmp(s, arg1, arg2, const_arg2, rexw);
+ /* setcc */
+ tcg_out_modrm(s, 0x90 | tcg_cond_to_jcc[cond] | P_EXT | P_REXB_RM, 0, dest);
+ tgen_arithi32(s, ARITH_AND, dest, 0xff);
+}
+
#if defined(CONFIG_SOFTMMU)
#include "../../softmmu_defs.h"
tcg_out_modrm(s, 0x8b, args[0], args[1]);
break;
+ case INDEX_op_setcond_i32:
+ tcg_out_setcond(s, args[3], args[0], args[1], args[2],
+ const_args[2], 0);
+ break;
+ case INDEX_op_setcond_i64:
+ tcg_out_setcond(s, args[3], args[0], args[1], args[2],
+ const_args[2], P_REXW);
+ break;
+
case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0);
break;
{ INDEX_op_ext16u_i64, { "r", "r"} },
{ INDEX_op_ext32u_i64, { "r", "r"} },
+ { INDEX_op_setcond_i32, { "r", "r", "ri" } },
+ { INDEX_op_setcond_i64, { "r", "r", "re" } },
+
{ INDEX_op_qemu_ld8u, { "r", "L" } },
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L" } },
//#define DEBUG
#ifdef DEBUG
-#define dprintf printf
+#define DPRINTF printf
#else
-#define dprintf(...)
+#define DPRINTF(...)
#endif
#define USBDBG_DEVOPENED "husb: opened %s/devices\n"
uint16_t offset;
uint8_t state;
struct usb_ctrlrequest req;
- uint8_t buffer[2048];
+ uint8_t buffer[8192];
};
struct USBAutoFilter {
return;
}
- dprintf("husb: async. reap urb failed errno %d\n", errno);
+ DPRINTF("husb: async. reap urb failed errno %d\n", errno);
return;
}
p = aurb->packet;
- dprintf("husb: async completed. aurb %p status %d alen %d\n",
+ DPRINTF("husb: async completed. aurb %p status %d alen %d\n",
aurb, aurb->urb.status, aurb->urb.actual_length);
if (p) {
AsyncURB *aurb = opaque;
USBHostDevice *s = aurb->hdev;
- dprintf("husb: async cancel. aurb %p\n", aurb);
+ DPRINTF("husb: async cancel. aurb %p\n", aurb);
/* Mark it as dead (see async_complete above) */
aurb->packet = NULL;
int r = ioctl(s->fd, USBDEVFS_DISCARDURB, aurb);
if (r < 0) {
- dprintf("husb: async. discard urb failed errno %d\n", errno);
+ DPRINTF("husb: async. discard urb failed errno %d\n", errno);
}
}
if (configuration == 0) /* address state - ignore */
return 1;
- dprintf("husb: claiming interfaces. config %d\n", configuration);
+ DPRINTF("husb: claiming interfaces. config %d\n", configuration);
i = 0;
dev_descr_len = dev->descr[0];
i += dev_descr_len;
while (i < dev->descr_len) {
- dprintf("husb: i is %d, descr_len is %d, dl %d, dt %d\n", i, dev->descr_len,
+ DPRINTF("husb: i is %d, descr_len is %d, dl %d, dt %d\n", i, dev->descr_len,
dev->descr[i], dev->descr[i+1]);
if (dev->descr[i+1] != USB_DT_CONFIG) {
{
int ret, i;
- dprintf("husb: releasing interfaces\n");
+ DPRINTF("husb: releasing interfaces\n");
for (i = 0; i < s->ninterfaces; i++) {
ret = ioctl(s->fd, USBDEVFS_RELEASEINTERFACE, &i);
{
USBHostDevice *s = DO_UPCAST(USBHostDevice, dev, dev);
- dprintf("husb: reset device %u.%u\n", s->bus_num, s->addr);
+ DPRINTF("husb: reset device %u.%u\n", s->bus_num, s->addr);
ioctl(s->fd, USBDEVFS_RESET);
if (is_halted(s, p->devep)) {
ret = ioctl(s->fd, USBDEVFS_CLEAR_HALT, &urb->endpoint);
if (ret < 0) {
- dprintf("husb: failed to clear halt. ep 0x%x errno %d\n",
+ DPRINTF("husb: failed to clear halt. ep 0x%x errno %d\n",
urb->endpoint, errno);
return USB_RET_NAK;
}
ret = ioctl(s->fd, USBDEVFS_SUBMITURB, urb);
- dprintf("husb: data submit. ep 0x%x len %u aurb %p\n", urb->endpoint, p->len, aurb);
+ DPRINTF("husb: data submit. ep 0x%x len %u aurb %p\n", urb->endpoint, p->len, aurb);
if (ret < 0) {
- dprintf("husb: submit failed. errno %d\n", errno);
+ DPRINTF("husb: submit failed. errno %d\n", errno);
async_free(aurb);
switch(errno) {
static int usb_host_set_address(USBHostDevice *s, int addr)
{
- dprintf("husb: ctrl set addr %u\n", addr);
+ DPRINTF("husb: ctrl set addr %u\n", addr);
s->dev.addr = addr;
return 0;
}
int ret = ioctl(s->fd, USBDEVFS_SETCONFIGURATION, &config);
- dprintf("husb: ctrl set config %d ret %d errno %d\n", config, ret, errno);
+ DPRINTF("husb: ctrl set config %d ret %d errno %d\n", config, ret, errno);
if (ret < 0)
return ctrl_error();
si.altsetting = alt;
ret = ioctl(s->fd, USBDEVFS_SETINTERFACE, &si);
- dprintf("husb: ctrl set iface %d altset %d ret %d errno %d\n",
+ DPRINTF("husb: ctrl set iface %d altset %d ret %d errno %d\n",
iface, alt, ret, errno);
if (ret < 0)
value = le16_to_cpu(s->ctrl.req.wValue);
index = le16_to_cpu(s->ctrl.req.wIndex);
- dprintf("husb: ctrl type 0x%x req 0x%x val 0x%x index %u len %u\n",
+ DPRINTF("husb: ctrl type 0x%x req 0x%x val 0x%x index %u len %u\n",
s->ctrl.req.bRequestType, s->ctrl.req.bRequest, value, index,
s->ctrl.len);
ret = ioctl(s->fd, USBDEVFS_SUBMITURB, urb);
- dprintf("husb: submit ctrl. len %u aurb %p\n", urb->buffer_length, aurb);
+ DPRINTF("husb: submit ctrl. len %u aurb %p\n", urb->buffer_length, aurb);
if (ret < 0) {
- dprintf("husb: submit failed. errno %d\n", errno);
+ DPRINTF("husb: submit failed. errno %d\n", errno);
async_free(aurb);
switch(errno) {
if (descriptors[i + 1] != USB_DT_CONFIG ||
descriptors[i + 5] != configuration) {
- dprintf("invalid descriptor data - configuration\n");
+ DPRINTF("invalid descriptor data - configuration\n");
return 1;
}
i += descriptors[i];
type = USBDEVFS_URB_TYPE_INTERRUPT;
break;
default:
- dprintf("usb_host: malformed endpoint type\n");
+ DPRINTF("usb_host: malformed endpoint type\n");
type = USBDEVFS_URB_TYPE_BULK;
}
s->endp_table[(devep & 0xf) - 1].type = type;
perror(buf);
goto fail;
}
- dprintf("husb: opened %s\n", buf);
+ DPRINTF("husb: opened %s\n", buf);
dev->bus_num = bus_num;
dev->addr = addr;
{
struct USBAutoFilter filter;
USBDevice *dev;
- USBHostDevice *s;
char *p;
dev = usb_create(NULL /* FIXME */, "usb-host");
- s = DO_UPCAST(USBHostDevice, dev, dev);
if (strstr(devname, "auto:")) {
if (parse_filter(devname, &filter) < 0)
strcpy(devpath, USBDEVBUS_PATH);
usb_fs_type = USB_FS_SYS;
closedir(dir);
- dprintf(USBDBG_DEVOPENED, USBSYSBUS_PATH);
+ DPRINTF(USBDBG_DEVOPENED, USBSYSBUS_PATH);
goto found_devices;
}
f = fopen(USBPROCBUS_PATH "/devices", "r");
strcpy(devpath, USBPROCBUS_PATH);
usb_fs_type = USB_FS_PROC;
fclose(f);
- dprintf(USBDBG_DEVOPENED, USBPROCBUS_PATH);
+ DPRINTF(USBDBG_DEVOPENED, USBPROCBUS_PATH);
goto found_devices;
}
/* try additional methods if an access method hasn't been found yet */
strcpy(devpath, USBDEVBUS_PATH);
usb_fs_type = USB_FS_DEV;
fclose(f);
- dprintf(USBDBG_DEVOPENED, USBDEVBUS_PATH);
+ DPRINTF(USBDBG_DEVOPENED, USBDEVBUS_PATH);
goto found_devices;
}
found_devices:
if (s->fd != -1)
return 0;
- dprintf("husb: auto open: bus_num %d addr %d\n", bus_num, addr);
+ DPRINTF("husb: auto open: bus_num %d addr %d\n", bus_num, addr);
usb_host_open(s, bus_num, addr, product_name);
}
fprintf(stderr,
"only 63 CPUs in NUMA mode supported.\n");
}
- value = (1 << (endvalue + 1)) - (1 << value);
+ value = (2ULL << endvalue) - (1ULL << value);
} else {
- value = 1 << value;
+ value = 1ULL << value;
}
}
node_cpumask[nodenr] = value;
DisplayState *ds = opaque;
DisplayChangeListener *dcl = ds->listeners;
+ qemu_flush_coalesced_mmio_buffer();
dpy_refresh(ds);
while (dcl != NULL) {
{
uint64_t interval = GUI_REFRESH_INTERVAL;
+ qemu_flush_coalesced_mmio_buffer();
qemu_mod_timer(nographic_timer, interval + qemu_get_clock(rt_clock));
}
return 0;
if (env->stopped)
return 0;
+ if (!vm_running)
+ return 0;
return 1;
}
static void help(int exitcode)
{
- version();
- printf("usage: %s [options] [disk_image]\n"
- "\n"
- "'disk_image' is a raw hard image image for IDE hard disk 0\n"
- "\n"
+ const char *options_help =
#define DEF(option, opt_arg, opt_enum, opt_help) \
opt_help
#define DEFHEADING(text) stringify(text) "\n"
#undef DEF
#undef DEFHEADING
#undef GEN_DOCS
+ ;
+ version();
+ printf("usage: %s [options] [disk_image]\n"
+ "\n"
+ "'disk_image' is a raw hard image image for IDE hard disk 0\n"
"\n"
+ "%s\n"
"During emulation, the following keys are useful:\n"
"ctrl-alt-f toggle full screen\n"
"ctrl-alt-n switch to virtual console 'n'\n"
"ctrl-alt toggle mouse and keyboard grab\n"
"\n"
- "When using -nographic, press 'ctrl-a h' to get some help.\n"
- ,
+ "When using -nographic, press 'ctrl-a h' to get some help.\n",
"qemu",
- DEFAULT_RAM_SIZE,
-#ifndef _WIN32
- DEFAULT_NETWORK_SCRIPT,
- DEFAULT_NETWORK_DOWN_SCRIPT,
-#endif
- DEFAULT_GDBSTUB_PORT,
- "/tmp/qemu.log");
+ options_help);
exit(exitcode);
}
const char *options;
int password = 0;
int reverse = 0;
- int to_port = 0;
#ifdef CONFIG_VNC_TLS
int tls = 0, x509 = 0;
#endif
password = 1; /* Require password auth */
} else if (strncmp(options, "reverse", 7) == 0) {
reverse = 1;
- } else if (strncmp(options, "to=", 3) == 0) {
- to_port = atoi(options+3) + 5900;
#ifdef CONFIG_VNC_SASL
} else if (strncmp(options, "sasl", 4) == 0) {
sasl = 1; /* Require SASL auth */
.rela.got : { *(.rela.got) }
.rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
.rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
+ .rel.plt :
+ {
+ *(.rel.plt)
+ PROVIDE_HIDDEN (__rel_iplt_start = .);
+ *(.rel.iplt)
+ PROVIDE_HIDDEN (__rel_iplt_end = .);
+ }
+ .rela.plt :
+ {
+ *(.rela.plt)
+ PROVIDE_HIDDEN (__rela_iplt_start = .);
+ *(.rela.iplt)
+ PROVIDE_HIDDEN (__rela_iplt_end = .);
+ }
.init :
{
KEEP (*(.init))
projects / qemu.git / commitdiff