uint32_t ticc; /* Global timer current count register */
uint32_t tibc; /* Global timer base count register */
} timers[MAX_TMR];
- /* IRQ out is used when in bypass mode (not implemented) */
- qemu_irq irq_out;
int max_irq;
int irq_ipi0;
int irq_tim0;
}
qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
- qemu_irq **irqs, qemu_irq irq_out)
+ qemu_irq **irqs)
{
OpenPICState *opp;
int i;
for (i = 0; i < nb_cpus; i++)
opp->dst[i].irqs = irqs[i];
- opp->irq_out = irq_out;
register_savevm(&opp->pci_dev.qdev, "openpic", 0, 2,
openpic_save, openpic_load, opp);
}
qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
- int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
+ int nb_cpus, qemu_irq **irqs)
{
OpenPICState *mpp;
int i;
for (i = 0; i < nb_cpus; i++)
mpp->dst[i].irqs = irqs[i];
- mpp->irq_out = irq_out;
/* Enable critical interrupt support */
mpp->flags |= OPENPIC_FLAG_IDE_CRIT;
#define OPENPIC_FLAG_IDE_CRIT (1 << 0)
qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
- qemu_irq **irqs, qemu_irq irq_out);
+ qemu_irq **irqs);
qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
- int nb_cpus, qemu_irq **irqs, qemu_irq irq_out);
+ int nb_cpus, qemu_irq **irqs);
#endif /* __OPENPIC_H__ */
exit(1);
}
}
- pic = openpic_init(&pic_mem, smp_cpus, openpic_irqs, NULL);
+ pic = openpic_init(&pic_mem, smp_cpus, openpic_irqs);
if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
/* 970 gets a U3 bus */
pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());