static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
{
APICCommonState *s = opaque;
+ APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
int i;
if (version_id > 2) {
s->next_time = qemu_get_be64(f);
if (version_id >= 2) {
- qemu_get_timer(f, s->timer);
+ s->timer_expiry = qemu_get_be64(f);
+ }
+
+ if (info->post_load) {
+ info->post_load(s);
}
return 0;
}
DeviceState *dev;
static int apic_mapped;
- if (kvm_enabled() && kvm_irqchip_in_kernel()) {
+ if (kvm_irqchip_in_kernel()) {
dev = qdev_create(NULL, "kvm-apic");
} else {
dev = qdev_create(NULL, "apic");
}
/* KVM does not support MSI yet. */
- if (!kvm_enabled() || !kvm_irqchip_in_kernel()) {
+ if (!kvm_irqchip_in_kernel()) {
msi_supported = true;
}
SysBusDevice *d;
unsigned int i;
- if (kvm_enabled() && kvm_irqchip_in_kernel()) {
+ if (kvm_irqchip_in_kernel()) {
dev = qdev_create(NULL, "kvm-ioapic");
} else {
dev = qdev_create(NULL, "ioapic");
}
gsi_state = g_malloc0(sizeof(*gsi_state));
- if (kvm_enabled() && kvm_irqchip_in_kernel()) {
+ if (kvm_irqchip_in_kernel()) {
kvm_piix3_setup_irq_routing(pci_enabled);
gsi = qemu_allocate_irqs(kvm_piix3_gsi_handler, gsi_state,
GSI_NUM_PINS);
}
isa_bus_irqs(isa_bus, gsi);
- if (kvm_enabled() && kvm_irqchip_in_kernel()) {
+ if (kvm_irqchip_in_kernel()) {
i8259 = kvm_i8259_init(isa_bus);
} else if (xen_enabled()) {
i8259 = xen_interrupt_controller_init();
#ifdef KVM_CAP_SET_GUEST_DEBUG
struct kvm_sw_breakpoint_head kvm_sw_breakpoints;
#endif
- int irqchip_in_kernel;
int pit_in_kernel;
int xsave, xcrs;
int many_ioeventfds;
};
KVMState *kvm_state;
+bool kvm_kernel_irqchip;
static const KVMCapabilityInfo kvm_required_capabilites[] = {
KVM_CAP_INFO(USER_MEMORY),
kvm_arch_reset_vcpu(env);
}
-int kvm_irqchip_in_kernel(void)
-{
- return kvm_state->irqchip_in_kernel;
-}
-
int kvm_pit_in_kernel(void)
{
return kvm_state->pit_in_kernel;
struct kvm_irq_level event;
int ret;
- assert(s->irqchip_in_kernel);
+ assert(kvm_irqchip_in_kernel());
event.level = level;
event.irq = irq;
if (kvm_check_extension(s, KVM_CAP_IRQ_INJECT_STATUS)) {
s->irqchip_inject_ioctl = KVM_IRQ_LINE_STATUS;
}
- s->irqchip_in_kernel = 1;
+ kvm_kernel_irqchip = true;
kvm_init_irq_routing(s);
int kvm_allows_irq0_override(void)
{
- return !kvm_enabled() || !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
+ return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
}
void kvm_setup_guest_memory(void *start, size_t size)
#include "gdbstub.h"
#include "kvm.h"
-int kvm_irqchip_in_kernel(void)
-{
- return 0;
-}
-
int kvm_pit_in_kernel(void)
{
return 0;
#endif
extern int kvm_allowed;
+extern bool kvm_kernel_irqchip;
#if defined CONFIG_KVM || !defined NEED_CPU_H
-#define kvm_enabled() (kvm_allowed)
+#define kvm_enabled() (kvm_allowed)
+#define kvm_irqchip_in_kernel() (kvm_kernel_irqchip)
#else
-#define kvm_enabled() (0)
+#define kvm_enabled() (0)
+#define kvm_irqchip_in_kernel() (false)
#endif
struct kvm_run;
#endif
int kvm_pit_in_kernel(void);
-int kvm_irqchip_in_kernel(void);
int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr);
int kvm_on_sigbus(int code, void *addr);
.name = "kernel_irqchip",
.type = QEMU_OPT_BOOL,
.help = "use KVM in-kernel irqchip",
+ }, {
+ .name = "kvm_shadow_mem",
+ .type = QEMU_OPT_SIZE,
+ .help = "KVM shadow MMU size",
},
{ /* End of list */ }
},
" selects emulated machine (-machine ? for list)\n"
" property accel=accel1[:accel2[:...]] selects accelerator\n"
" supported accelerators are kvm, xen, tcg (default: tcg)\n"
- " kernel_irqchip=on|off controls accelerated irqchip support\n",
+ " kernel_irqchip=on|off controls accelerated irqchip support\n"
+ " kvm_shadow_mem=size of KVM shadow MMU\n",
QEMU_ARCH_ALL)
STEXI
@item -machine [type=]@var{name}[,prop=@var{value}[,...]]
to initialize.
@item kernel_irqchip=on|off
Enables in-kernel irqchip support for the chosen accelerator when available.
+@item kvm_shadow_mem=size
+Defines the size of the KVM shadow MMU.
@end table
ETEXI
int kvm_arch_init(KVMState *s)
{
+ QemuOptsList *list = qemu_find_opts("machine");
uint64_t identity_base = 0xfffbc000;
+ uint64_t shadow_mem;
int ret;
struct utsname utsname;
}
qemu_register_reset(kvm_unpoison_all, NULL);
+ if (!QTAILQ_EMPTY(&list->head)) {
+ shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head),
+ "kvm_shadow_mem", -1);
+ if (shadow_mem != -1) {
+ shadow_mem /= 4096;
+ ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
+ if (ret < 0) {
+ return ret;
+ }
+ }
+ }
return 0;
}
struct kvm_lapic_state kapic;
int ret;
- if (apic && kvm_enabled() && kvm_irqchip_in_kernel()) {
+ if (apic && kvm_irqchip_in_kernel()) {
ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, &kapic);
if (ret < 0) {
return ret;
DeviceState *apic = env->apic_state;
struct kvm_lapic_state kapic;
- if (apic && kvm_enabled() && kvm_irqchip_in_kernel()) {
+ if (apic && kvm_irqchip_in_kernel()) {
kvm_put_apic_state(apic, &kapic);
return kvm_vcpu_ioctl(env, KVM_SET_LAPIC, &kapic);