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397bdc99 OM |
1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r | |
4 | *\r | |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
60775c51 | 15 | #include <Base.h>\r |
397bdc99 | 16 | #include <Library/ArmGicLib.h>\r |
1b0ac0de | 17 | #include <Library/DebugLib.h>\r |
60775c51 | 18 | #include <Library/IoLib.h>\r |
397bdc99 | 19 | \r |
793ca69f OM |
20 | #include "GicV2/ArmGicV2Lib.h"\r |
21 | \r | |
397bdc99 OM |
22 | UINTN\r |
23 | EFIAPI\r | |
24 | ArmGicGetInterfaceIdentification (\r | |
25 | IN INTN GicInterruptInterfaceBase\r | |
26 | )\r | |
27 | {\r | |
28 | // Read the GIC Identification Register\r | |
29 | return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR);\r | |
30 | }\r | |
31 | \r | |
32 | UINTN\r | |
33 | EFIAPI\r | |
34 | ArmGicGetMaxNumInterrupts (\r | |
35 | IN INTN GicDistributorBase\r | |
36 | )\r | |
37 | {\r | |
38 | return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);\r | |
39 | }\r | |
40 | \r | |
41 | VOID\r | |
42 | EFIAPI\r | |
43 | ArmGicSendSgiTo (\r | |
44 | IN INTN GicDistributorBase,\r | |
45 | IN INTN TargetListFilter,\r | |
46 | IN INTN CPUTargetList,\r | |
47 | IN INTN SgiId\r | |
48 | )\r | |
49 | {\r | |
50 | MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);\r | |
51 | }\r | |
52 | \r | |
1b0ac0de OM |
53 | /*\r |
54 | * Acknowledge and return the value of the Interrupt Acknowledge Register\r | |
55 | *\r | |
56 | * InterruptId is returned separately from the register value because in\r | |
57 | * the GICv2 the register value contains the CpuId and InterruptId while\r | |
58 | * in the GICv3 the register value is only the InterruptId.\r | |
59 | *\r | |
60 | * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface\r | |
61 | * @param InterruptId InterruptId read from the Interrupt Acknowledge Register\r | |
62 | *\r | |
63 | * @retval value returned by the Interrupt Acknowledge Register\r | |
64 | *\r | |
65 | */\r | |
397bdc99 OM |
66 | UINTN\r |
67 | EFIAPI\r | |
68 | ArmGicAcknowledgeInterrupt (\r | |
1b0ac0de OM |
69 | IN UINTN GicInterruptInterfaceBase,\r |
70 | OUT UINTN *InterruptId\r | |
397bdc99 OM |
71 | )\r |
72 | {\r | |
1b0ac0de OM |
73 | UINTN Value;\r |
74 | \r | |
75 | Value = ArmGicV2AcknowledgeInterrupt (GicInterruptInterfaceBase);\r | |
76 | \r | |
77 | // InterruptId is required for the caller to know if a valid or spurious\r | |
78 | // interrupt has been read\r | |
79 | ASSERT (InterruptId != NULL);\r | |
80 | \r | |
81 | if (InterruptId != NULL) {\r | |
82 | *InterruptId = Value & ARM_GIC_ICCIAR_ACKINTID;\r | |
83 | }\r | |
84 | \r | |
85 | return Value;\r | |
397bdc99 OM |
86 | }\r |
87 | \r | |
88 | VOID\r | |
89 | EFIAPI\r | |
90 | ArmGicEndOfInterrupt (\r | |
91 | IN UINTN GicInterruptInterfaceBase,\r | |
92 | IN UINTN Source\r | |
93 | )\r | |
94 | {\r | |
793ca69f | 95 | ArmGicV2EndOfInterrupt (GicInterruptInterfaceBase, Source);\r |
397bdc99 OM |
96 | }\r |
97 | \r | |
98 | VOID\r | |
99 | EFIAPI\r | |
100 | ArmGicEnableInterrupt (\r | |
101 | IN UINTN GicDistributorBase,\r | |
102 | IN UINTN Source\r | |
103 | )\r | |
104 | {\r | |
105 | UINT32 RegOffset;\r | |
106 | UINTN RegShift;\r | |
107 | \r | |
108 | // Calculate enable register offset and bit position\r | |
109 | RegOffset = Source / 32;\r | |
110 | RegShift = Source % 32;\r | |
111 | \r | |
112 | // Write set-enable register\r | |
113 | MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);\r | |
114 | }\r | |
115 | \r | |
116 | VOID\r | |
117 | EFIAPI\r | |
118 | ArmGicDisableInterrupt (\r | |
119 | IN UINTN GicDistributorBase,\r | |
120 | IN UINTN Source\r | |
121 | )\r | |
122 | {\r | |
123 | UINT32 RegOffset;\r | |
124 | UINTN RegShift;\r | |
125 | \r | |
126 | // Calculate enable register offset and bit position\r | |
127 | RegOffset = Source / 32;\r | |
128 | RegShift = Source % 32;\r | |
129 | \r | |
130 | // Write clear-enable register\r | |
131 | MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);\r | |
132 | }\r | |
133 | \r | |
134 | BOOLEAN\r | |
135 | EFIAPI\r | |
136 | ArmGicIsInterruptEnabled (\r | |
137 | IN UINTN GicDistributorBase,\r | |
138 | IN UINTN Source\r | |
139 | )\r | |
140 | {\r | |
141 | UINT32 RegOffset;\r | |
142 | UINTN RegShift;\r | |
143 | \r | |
144 | // Calculate enable register offset and bit position\r | |
145 | RegOffset = Source / 32;\r | |
146 | RegShift = Source % 32;\r | |
147 | \r | |
148 | return ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);\r | |
149 | }\r | |
60775c51 OM |
150 | \r |
151 | VOID\r | |
152 | EFIAPI\r | |
153 | ArmGicDisableDistributor (\r | |
154 | IN INTN GicDistributorBase\r | |
155 | )\r | |
156 | {\r | |
157 | // Disable Gic Distributor\r | |
158 | MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0);\r | |
159 | }\r | |
62d441fb | 160 | \r |
793ca69f OM |
161 | VOID\r |
162 | EFIAPI\r | |
163 | ArmGicEnableInterruptInterface (\r | |
164 | IN INTN GicInterruptInterfaceBase\r | |
165 | )\r | |
166 | {\r | |
167 | return ArmGicV2EnableInterruptInterface (GicInterruptInterfaceBase);\r | |
168 | }\r | |
169 | \r | |
170 | VOID\r | |
171 | EFIAPI\r | |
172 | ArmGicDisableInterruptInterface (\r | |
173 | IN INTN GicInterruptInterfaceBase\r | |
174 | )\r | |
175 | {\r | |
176 | return ArmGicV2DisableInterruptInterface (GicInterruptInterfaceBase);\r | |
177 | }\r |