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2ef2b01e A |
1 | /** @file\r |
2 | \r | |
d6ebcab7 | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
8513037f | 4 | Copyright (c) 2011, ARM Limited. All rights reserved.\r |
3402aac7 | 5 | \r |
d6ebcab7 | 6 | This program and the accompanying materials\r |
2ef2b01e A |
7 | are licensed and made available under the terms and conditions of the BSD License\r |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include "CpuDxe.h"\r | |
17 | \r | |
8513037f | 18 | #include <Guid/IdleLoopEvent.h>\r |
19 | \r | |
f659880b A |
20 | \r |
21 | /**\r | |
3402aac7 RC |
22 | This function flushes the range of addresses from Start to Start+Length\r |
23 | from the processor's data cache. If Start is not aligned to a cache line\r | |
24 | boundary, then the bytes before Start to the preceding cache line boundary\r | |
25 | are also flushed. If Start+Length is not aligned to a cache line boundary,\r | |
26 | then the bytes past Start+Length to the end of the next cache line boundary\r | |
27 | are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be\r | |
28 | supported. If the data cache is fully coherent with all DMA operations, then\r | |
29 | this function can just return EFI_SUCCESS. If the processor does not support\r | |
f659880b A |
30 | flushing a range of the data cache, then the entire data cache can be flushed.\r |
31 | \r | |
32 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
33 | @param Start The beginning physical address to flush from the processor's data\r | |
34 | cache.\r | |
35 | @param Length The number of bytes to flush from the processor's data cache. This\r | |
36 | function may flush more bytes than Length specifies depending upon\r | |
37 | the granularity of the flush operation that the processor supports.\r | |
38 | @param FlushType Specifies the type of flush operation to perform.\r | |
39 | \r | |
40 | @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r | |
41 | the processor's data cache.\r | |
42 | @retval EFI_UNSUPPORTEDT The processor does not support the cache flush type specified\r | |
43 | by FlushType.\r | |
44 | @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r | |
45 | from the processor's data cache.\r | |
46 | \r | |
47 | **/\r | |
2ef2b01e A |
48 | EFI_STATUS\r |
49 | EFIAPI\r | |
50 | CpuFlushCpuDataCache (\r | |
51 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
52 | IN EFI_PHYSICAL_ADDRESS Start,\r | |
53 | IN UINT64 Length,\r | |
54 | IN EFI_CPU_FLUSH_TYPE FlushType\r | |
55 | )\r | |
56 | {\r | |
f659880b | 57 | \r |
2ef2b01e A |
58 | switch (FlushType) {\r |
59 | case EfiCpuFlushTypeWriteBack:\r | |
8a4d81e6 | 60 | WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
61 | break;\r |
62 | case EfiCpuFlushTypeInvalidate:\r | |
8a4d81e6 | 63 | InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
64 | break;\r |
65 | case EfiCpuFlushTypeWriteBackInvalidate:\r | |
8a4d81e6 | 66 | WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
67 | break;\r |
68 | default:\r | |
69 | return EFI_INVALID_PARAMETER;\r | |
70 | }\r | |
3402aac7 | 71 | \r |
2ef2b01e A |
72 | return EFI_SUCCESS;\r |
73 | }\r | |
74 | \r | |
f659880b A |
75 | \r |
76 | /**\r | |
3402aac7 | 77 | This function enables interrupt processing by the processor.\r |
f659880b A |
78 | \r |
79 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
80 | \r | |
81 | @retval EFI_SUCCESS Interrupts are enabled on the processor.\r | |
82 | @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.\r | |
83 | \r | |
84 | **/\r | |
2ef2b01e A |
85 | EFI_STATUS\r |
86 | EFIAPI\r | |
87 | CpuEnableInterrupt (\r | |
88 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
89 | )\r | |
90 | {\r | |
d213712d | 91 | ArmEnableInterrupts ();\r |
8a4d81e6 | 92 | \r |
2ef2b01e A |
93 | return EFI_SUCCESS;\r |
94 | }\r | |
95 | \r | |
96 | \r | |
f659880b A |
97 | /**\r |
98 | This function disables interrupt processing by the processor.\r | |
99 | \r | |
100 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
101 | \r | |
102 | @retval EFI_SUCCESS Interrupts are disabled on the processor.\r | |
103 | @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.\r | |
104 | \r | |
105 | **/\r | |
2ef2b01e A |
106 | EFI_STATUS\r |
107 | EFIAPI\r | |
108 | CpuDisableInterrupt (\r | |
109 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
110 | )\r | |
111 | {\r | |
d213712d | 112 | ArmDisableInterrupts ();\r |
8a4d81e6 | 113 | \r |
2ef2b01e A |
114 | return EFI_SUCCESS;\r |
115 | }\r | |
116 | \r | |
f659880b A |
117 | \r |
118 | /**\r | |
3402aac7 RC |
119 | This function retrieves the processor's current interrupt state a returns it in\r |
120 | State. If interrupts are currently enabled, then TRUE is returned. If interrupts\r | |
f659880b A |
121 | are currently disabled, then FALSE is returned.\r |
122 | \r | |
123 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
124 | @param State A pointer to the processor's current interrupt state. Set to TRUE if\r | |
125 | interrupts are enabled and FALSE if interrupts are disabled.\r | |
126 | \r | |
127 | @retval EFI_SUCCESS The processor's current interrupt state was returned in State.\r | |
128 | @retval EFI_INVALID_PARAMETER State is NULL.\r | |
129 | \r | |
130 | **/\r | |
2ef2b01e A |
131 | EFI_STATUS\r |
132 | EFIAPI\r | |
133 | CpuGetInterruptState (\r | |
134 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
135 | OUT BOOLEAN *State\r | |
136 | )\r | |
137 | {\r | |
138 | if (State == NULL) {\r | |
139 | return EFI_INVALID_PARAMETER;\r | |
140 | }\r | |
141 | \r | |
e3aa7252 | 142 | *State = ArmGetInterruptState();\r |
2ef2b01e A |
143 | return EFI_SUCCESS;\r |
144 | }\r | |
145 | \r | |
f659880b A |
146 | \r |
147 | /**\r | |
148 | This function generates an INIT on the processor. If this function succeeds, then the\r | |
3402aac7 RC |
149 | processor will be reset, and control will not be returned to the caller. If InitType is\r |
150 | not supported by this processor, or the processor cannot programmatically generate an\r | |
151 | INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error\r | |
f659880b A |
152 | occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r |
153 | \r | |
154 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
155 | @param InitType The type of processor INIT to perform.\r | |
156 | \r | |
157 | @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.\r | |
158 | @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported\r | |
159 | by this processor.\r | |
160 | @retval EFI_DEVICE_ERROR The processor INIT failed.\r | |
161 | \r | |
162 | **/\r | |
2ef2b01e A |
163 | EFI_STATUS\r |
164 | EFIAPI\r | |
165 | CpuInit (\r | |
166 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
167 | IN EFI_CPU_INIT_TYPE InitType\r | |
168 | )\r | |
169 | {\r | |
170 | return EFI_UNSUPPORTED;\r | |
171 | }\r | |
172 | \r | |
173 | EFI_STATUS\r | |
174 | EFIAPI\r | |
175 | CpuRegisterInterruptHandler (\r | |
176 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
177 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
178 | IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r | |
179 | )\r | |
180 | {\r | |
8a4d81e6 | 181 | return RegisterInterruptHandler (InterruptType, InterruptHandler);\r |
2ef2b01e A |
182 | }\r |
183 | \r | |
184 | EFI_STATUS\r | |
185 | EFIAPI\r | |
186 | CpuGetTimerValue (\r | |
187 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
188 | IN UINT32 TimerIndex,\r | |
189 | OUT UINT64 *TimerValue,\r | |
190 | OUT UINT64 *TimerPeriod OPTIONAL\r | |
191 | )\r | |
192 | {\r | |
193 | return EFI_UNSUPPORTED;\r | |
194 | }\r | |
195 | \r | |
8513037f | 196 | /**\r |
197 | Callback function for idle events.\r | |
3402aac7 | 198 | \r |
8513037f | 199 | @param Event Event whose notification function is being invoked.\r |
200 | @param Context The pointer to the notification function's context,\r | |
201 | which is implementation-dependent.\r | |
202 | \r | |
203 | **/\r | |
204 | VOID\r | |
205 | EFIAPI\r | |
206 | IdleLoopEventCallback (\r | |
207 | IN EFI_EVENT Event,\r | |
208 | IN VOID *Context\r | |
209 | )\r | |
210 | {\r | |
211 | CpuSleep ();\r | |
212 | }\r | |
2ef2b01e A |
213 | \r |
214 | //\r | |
215 | // Globals used to initialize the protocol\r | |
216 | //\r | |
217 | EFI_HANDLE mCpuHandle = NULL;\r | |
218 | EFI_CPU_ARCH_PROTOCOL mCpu = {\r | |
219 | CpuFlushCpuDataCache,\r | |
220 | CpuEnableInterrupt,\r | |
221 | CpuDisableInterrupt,\r | |
222 | CpuGetInterruptState,\r | |
223 | CpuInit,\r | |
224 | CpuRegisterInterruptHandler,\r | |
225 | CpuGetTimerValue,\r | |
226 | CpuSetMemoryAttributes,\r | |
227 | 0, // NumberOfTimers\r | |
228 | 4, // DmaBufferAlignment\r | |
229 | };\r | |
230 | \r | |
231 | EFI_STATUS\r | |
232 | CpuDxeInitialize (\r | |
233 | IN EFI_HANDLE ImageHandle,\r | |
234 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
235 | )\r | |
f659880b A |
236 | {\r |
237 | EFI_STATUS Status;\r | |
8513037f | 238 | EFI_EVENT IdleLoopEvent;\r |
f659880b | 239 | \r |
3402aac7 RC |
240 | InitializeExceptions (&mCpu);\r |
241 | \r | |
f659880b | 242 | Status = gBS->InstallMultipleProtocolInterfaces (\r |
3402aac7 RC |
243 | &mCpuHandle,\r |
244 | &gEfiCpuArchProtocolGuid, &mCpu,\r | |
f659880b A |
245 | &gVirtualUncachedPagesProtocolGuid, &gVirtualUncachedPages,\r |
246 | NULL\r | |
247 | );\r | |
3402aac7 | 248 | \r |
f659880b A |
249 | //\r |
250 | // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()\r | |
251 | // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go\r | |
252 | // after the protocol is installed\r | |
253 | //\r | |
254 | SyncCacheConfig (&mCpu);\r | |
3402aac7 | 255 | \r |
44788bae | 256 | // If the platform is a MPCore system then install the Configuration Table describing the\r |
257 | // secondary core states\r | |
886f97c8 | 258 | if (ArmIsMpCore()) {\r |
44788bae | 259 | PublishArmProcessorTable();\r |
260 | }\r | |
261 | \r | |
8513037f | 262 | //\r |
263 | // Setup a callback for idle events\r | |
264 | //\r | |
265 | Status = gBS->CreateEventEx (\r | |
266 | EVT_NOTIFY_SIGNAL,\r | |
267 | TPL_NOTIFY,\r | |
268 | IdleLoopEventCallback,\r | |
269 | NULL,\r | |
270 | &gIdleLoopEventGuid,\r | |
271 | &IdleLoopEvent\r | |
272 | );\r | |
273 | ASSERT_EFI_ERROR (Status);\r | |
274 | \r | |
f659880b | 275 | return Status;\r |
2ef2b01e | 276 | }\r |