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aeb61534 A |
1 | /*++\r |
2 | \r | |
d6ebcab7 HT |
3 | Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r |
4 | Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r | |
aeb61534 | 5 | \r |
d6ebcab7 | 6 | This program and the accompanying materials \r |
aeb61534 A |
7 | are licensed and made available under the terms and conditions of the BSD License \r |
8 | which accompanies this distribution. The full text of the license may be found at \r | |
9 | http://opensource.org/licenses/bsd-license.php \r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | \r | |
14 | \r | |
15 | --*/\r | |
16 | \r | |
17 | #include "CpuDxe.h"\r | |
1bfda055 | 18 | //FIXME: Remove this ARMv7 specific header\r |
19 | #include <Chipset/ArmV7.h>\r | |
aeb61534 A |
20 | \r |
21 | // First Level Descriptors\r | |
22 | typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;\r | |
23 | \r | |
aeb61534 A |
24 | // Second Level Descriptors\r |
25 | typedef UINT32 ARM_PAGE_TABLE_ENTRY;\r | |
26 | \r | |
aeb61534 A |
27 | EFI_STATUS \r |
28 | SectionToGcdAttributes (\r | |
29 | IN UINT32 SectionAttributes,\r | |
30 | OUT UINT64 *GcdAttributes\r | |
31 | )\r | |
32 | {\r | |
33 | *GcdAttributes = 0;\r | |
34 | \r | |
35 | // determine cacheability attributes\r | |
1bfda055 | 36 | switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {\r |
37 | case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED:\r | |
aeb61534 A |
38 | *GcdAttributes |= EFI_MEMORY_UC;\r |
39 | break;\r | |
1bfda055 | 40 | case TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE:\r |
aeb61534 A |
41 | *GcdAttributes |= EFI_MEMORY_UC;\r |
42 | break;\r | |
1bfda055 | 43 | case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:\r |
aeb61534 A |
44 | *GcdAttributes |= EFI_MEMORY_WT;\r |
45 | break;\r | |
1bfda055 | 46 | case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC:\r |
aeb61534 A |
47 | *GcdAttributes |= EFI_MEMORY_WB;\r |
48 | break;\r | |
1bfda055 | 49 | case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE:\r |
aeb61534 A |
50 | *GcdAttributes |= EFI_MEMORY_WC;\r |
51 | break;\r | |
1bfda055 | 52 | case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC:\r |
aeb61534 A |
53 | *GcdAttributes |= EFI_MEMORY_WB;\r |
54 | break;\r | |
1bfda055 | 55 | case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE:\r |
aeb61534 A |
56 | *GcdAttributes |= EFI_MEMORY_UC;\r |
57 | break;\r | |
58 | default:\r | |
59 | return EFI_UNSUPPORTED;\r | |
aeb61534 | 60 | }\r |
1bfda055 | 61 | \r |
aeb61534 | 62 | // determine protection attributes\r |
1bfda055 | 63 | switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {\r |
64 | case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write\r | |
f659880b | 65 | //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r |
aeb61534 A |
66 | break;\r |
67 | \r | |
1bfda055 | 68 | case TT_DESCRIPTOR_SECTION_AP_RW_NO:\r |
69 | case TT_DESCRIPTOR_SECTION_AP_RW_RW:\r | |
aeb61534 A |
70 | // normal read/write access, do not add additional attributes\r |
71 | break;\r | |
72 | \r | |
73 | // read only cases map to write-protect\r | |
1bfda055 | 74 | case TT_DESCRIPTOR_SECTION_AP_RO_NO:\r |
75 | case TT_DESCRIPTOR_SECTION_AP_RO_RO:\r | |
aeb61534 A |
76 | *GcdAttributes |= EFI_MEMORY_WP;\r |
77 | break;\r | |
78 | \r | |
79 | default:\r | |
80 | return EFI_UNSUPPORTED;\r | |
aeb61534 A |
81 | }\r |
82 | \r | |
83 | // now process eXectue Never attribute\r | |
1bfda055 | 84 | if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0 ) {\r |
aeb61534 A |
85 | *GcdAttributes |= EFI_MEMORY_XP;\r |
86 | }\r | |
87 | \r | |
88 | return EFI_SUCCESS;\r | |
89 | }\r | |
90 | \r | |
f659880b A |
91 | /**\r |
92 | Searches memory descriptors covered by given memory range.\r | |
93 | \r | |
94 | This function searches into the Gcd Memory Space for descriptors\r | |
95 | (from StartIndex to EndIndex) that contains the memory range\r | |
96 | specified by BaseAddress and Length.\r | |
97 | \r | |
98 | @param MemorySpaceMap Gcd Memory Space Map as array.\r | |
99 | @param NumberOfDescriptors Number of descriptors in map.\r | |
100 | @param BaseAddress BaseAddress for the requested range.\r | |
101 | @param Length Length for the requested range.\r | |
102 | @param StartIndex Start index into the Gcd Memory Space Map.\r | |
103 | @param EndIndex End index into the Gcd Memory Space Map.\r | |
104 | \r | |
105 | @retval EFI_SUCCESS Search successfully.\r | |
106 | @retval EFI_NOT_FOUND The requested descriptors does not exist.\r | |
107 | \r | |
108 | **/\r | |
109 | EFI_STATUS\r | |
110 | SearchGcdMemorySpaces (\r | |
111 | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r | |
112 | IN UINTN NumberOfDescriptors,\r | |
113 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
114 | IN UINT64 Length,\r | |
115 | OUT UINTN *StartIndex,\r | |
116 | OUT UINTN *EndIndex\r | |
117 | )\r | |
118 | {\r | |
119 | UINTN Index;\r | |
120 | \r | |
121 | *StartIndex = 0;\r | |
122 | *EndIndex = 0;\r | |
123 | for (Index = 0; Index < NumberOfDescriptors; Index++) {\r | |
124 | if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&\r | |
125 | BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
126 | *StartIndex = Index;\r | |
127 | }\r | |
128 | if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&\r | |
129 | BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
130 | *EndIndex = Index;\r | |
131 | return EFI_SUCCESS;\r | |
132 | }\r | |
133 | }\r | |
134 | return EFI_NOT_FOUND;\r | |
135 | }\r | |
136 | \r | |
137 | \r | |
138 | /**\r | |
139 | Sets the attributes for a specified range in Gcd Memory Space Map.\r | |
140 | \r | |
141 | This function sets the attributes for a specified range in\r | |
142 | Gcd Memory Space Map.\r | |
143 | \r | |
144 | @param MemorySpaceMap Gcd Memory Space Map as array\r | |
145 | @param NumberOfDescriptors Number of descriptors in map\r | |
146 | @param BaseAddress BaseAddress for the range\r | |
147 | @param Length Length for the range\r | |
148 | @param Attributes Attributes to set\r | |
149 | \r | |
150 | @retval EFI_SUCCESS Memory attributes set successfully\r | |
151 | @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space\r | |
152 | \r | |
153 | **/\r | |
154 | EFI_STATUS\r | |
155 | SetGcdMemorySpaceAttributes (\r | |
156 | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r | |
157 | IN UINTN NumberOfDescriptors,\r | |
158 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
159 | IN UINT64 Length,\r | |
160 | IN UINT64 Attributes\r | |
161 | )\r | |
162 | {\r | |
163 | EFI_STATUS Status;\r | |
164 | UINTN Index;\r | |
165 | UINTN StartIndex;\r | |
166 | UINTN EndIndex;\r | |
167 | EFI_PHYSICAL_ADDRESS RegionStart;\r | |
168 | UINT64 RegionLength;\r | |
169 | \r | |
170 | //\r | |
171 | // Get all memory descriptors covered by the memory range\r | |
172 | //\r | |
173 | Status = SearchGcdMemorySpaces (\r | |
174 | MemorySpaceMap,\r | |
175 | NumberOfDescriptors,\r | |
176 | BaseAddress,\r | |
177 | Length,\r | |
178 | &StartIndex,\r | |
179 | &EndIndex\r | |
180 | );\r | |
181 | if (EFI_ERROR (Status)) {\r | |
182 | return Status;\r | |
183 | }\r | |
184 | \r | |
185 | //\r | |
186 | // Go through all related descriptors and set attributes accordingly\r | |
187 | //\r | |
188 | for (Index = StartIndex; Index <= EndIndex; Index++) {\r | |
189 | if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r | |
190 | continue;\r | |
191 | }\r | |
192 | //\r | |
193 | // Calculate the start and end address of the overlapping range\r | |
194 | //\r | |
195 | if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {\r | |
196 | RegionStart = BaseAddress;\r | |
197 | } else {\r | |
198 | RegionStart = MemorySpaceMap[Index].BaseAddress;\r | |
199 | }\r | |
200 | if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
201 | RegionLength = BaseAddress + Length - RegionStart;\r | |
202 | } else {\r | |
203 | RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;\r | |
204 | }\r | |
205 | //\r | |
206 | // Set memory attributes according to MTRR attribute and the original attribute of descriptor\r | |
207 | //\r | |
208 | gDS->SetMemorySpaceAttributes (\r | |
209 | RegionStart,\r | |
210 | RegionLength,\r | |
211 | (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)\r | |
212 | );\r | |
213 | }\r | |
214 | \r | |
215 | return EFI_SUCCESS;\r | |
216 | }\r | |
aeb61534 A |
217 | \r |
218 | \r | |
219 | EFI_STATUS\r | |
220 | SyncCacheConfig (\r | |
221 | IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r | |
222 | )\r | |
223 | {\r | |
f659880b A |
224 | EFI_STATUS Status;\r |
225 | UINT32 i;\r | |
226 | UINT32 Descriptor;\r | |
227 | UINT32 SectionAttributes;\r | |
228 | EFI_PHYSICAL_ADDRESS NextRegionBase;\r | |
229 | UINT64 NextRegionLength;\r | |
230 | UINT64 GcdAttributes;\r | |
231 | UINT32 NextRegionAttributes = 0;\r | |
aeb61534 | 232 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r |
f659880b A |
233 | UINTN NumberOfDescriptors;\r |
234 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r | |
aeb61534 A |
235 | \r |
236 | \r | |
225290eb | 237 | DEBUG ((EFI_D_PAGE, "SyncCacheConfig()\n"));\r |
f659880b | 238 | \r |
aeb61534 A |
239 | // This code assumes MMU is enabled and filed with section translations\r |
240 | ASSERT (ArmMmuEnabled ());\r | |
241 | \r | |
f659880b A |
242 | //\r |
243 | // Get the memory space map from GCD\r | |
244 | //\r | |
245 | MemorySpaceMap = NULL;\r | |
246 | Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r | |
247 | ASSERT_EFI_ERROR (Status);\r | |
248 | \r | |
aeb61534 A |
249 | \r |
250 | // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs\r | |
251 | // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a\r | |
252 | // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were\r | |
253 | // a client) to update its copy of the attributes. This is bad architecture and should be replaced\r | |
254 | // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.\r | |
255 | \r | |
256 | // obtain page table base\r | |
1bfda055 | 257 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddress ());\r |
aeb61534 A |
258 | \r |
259 | \r | |
260 | // iterate through each 1MB descriptor\r | |
261 | NextRegionBase = NextRegionLength = 0;\r | |
1bfda055 | 262 | for (i=0; i< TRANSLATION_TABLE_SECTION_COUNT; i++) {\r |
aeb61534 | 263 | \r |
f659880b | 264 | // obtain existing descriptor and make sure it contains a valid Base Address even if it is a fault section\r |
1bfda055 | 265 | Descriptor = FirstLevelTable[i] | TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r |
aeb61534 A |
266 | \r |
267 | // extract attributes (cacheability and permissions)\r | |
1bfda055 | 268 | SectionAttributes = Descriptor & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);\r |
aeb61534 A |
269 | \r |
270 | // do we already have an existing region (or are we about to finish)?\r | |
271 | // Skip the first entry, and make sure we close on the last entry\r | |
1bfda055 | 272 | if ( (NextRegionLength > 0) || (i == (TRANSLATION_TABLE_SECTION_COUNT-1)) ) {\r |
aeb61534 A |
273 | // attributes are changing, update attributes in GCD\r |
274 | if (SectionAttributes != NextRegionAttributes) {\r | |
275 | \r | |
276 | // convert section entry attributes to GCD bitmask\r | |
277 | Status = SectionToGcdAttributes (NextRegionAttributes, &GcdAttributes);\r | |
f659880b | 278 | ASSERT_EFI_ERROR (Status);\r |
aeb61534 A |
279 | \r |
280 | // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r | |
f659880b A |
281 | SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r |
282 | \r | |
aeb61534 A |
283 | \r |
284 | // start on a new region\r | |
285 | NextRegionLength = 0;\r | |
1bfda055 | 286 | NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(Descriptor);\r |
aeb61534 A |
287 | }\r |
288 | }\r | |
289 | \r | |
290 | // starting a new region?\r | |
291 | if (NextRegionLength == 0) {\r | |
292 | NextRegionAttributes = SectionAttributes;\r | |
293 | }\r | |
294 | \r | |
1bfda055 | 295 | NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;\r |
aeb61534 A |
296 | \r |
297 | } // section entry loop\r | |
298 | \r | |
299 | return EFI_SUCCESS;\r | |
300 | }\r | |
301 | \r | |
302 | \r | |
303 | \r | |
304 | EFI_STATUS\r | |
305 | UpdatePageEntries (\r | |
306 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
307 | IN UINT64 Length,\r | |
308 | IN UINT64 Attributes,\r | |
309 | IN EFI_PHYSICAL_ADDRESS VirtualMask\r | |
310 | )\r | |
311 | {\r | |
312 | EFI_STATUS Status;\r | |
313 | UINT32 EntryValue;\r | |
314 | UINT32 EntryMask;\r | |
315 | UINT32 FirstLevelIdx;\r | |
316 | UINT32 Offset;\r | |
317 | UINT32 NumPageEntries;\r | |
318 | UINT32 Descriptor;\r | |
319 | UINT32 p;\r | |
320 | UINT32 PageTableIndex;\r | |
321 | UINT32 PageTableEntry;\r | |
bb02cb80 | 322 | UINT32 CurrentPageTableEntry;\r |
323 | VOID *Mva;\r | |
aeb61534 A |
324 | \r |
325 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r | |
326 | volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r | |
327 | \r | |
920cb926 A |
328 | Status = EFI_SUCCESS;\r |
329 | \r | |
aeb61534 A |
330 | // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r |
331 | // EntryValue: values at bit positions specified by EntryMask\r | |
1bfda055 | 332 | EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK;\r |
333 | EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r | |
aeb61534 A |
334 | // Although the PI spec is unclear on this the GCD guarantees that only\r |
335 | // one Attribute bit is set at a time, so we can safely use a switch statement\r | |
336 | switch (Attributes) {\r | |
337 | case EFI_MEMORY_UC:\r | |
338 | // modify cacheability attributes\r | |
1bfda055 | 339 | EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r |
340 | if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {\r | |
2ac288f9 | 341 | // map to strongly ordered\r |
342 | EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r | |
1bfda055 | 343 | } else {\r |
2ac288f9 | 344 | // map to normal non-cachable\r |
345 | EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r | |
1bfda055 | 346 | }\r |
aeb61534 A |
347 | break;\r |
348 | \r | |
349 | case EFI_MEMORY_WC:\r | |
350 | // modify cacheability attributes\r | |
1bfda055 | 351 | EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r |
aeb61534 | 352 | // map to normal non-cachable\r |
1bfda055 | 353 | EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r |
aeb61534 A |
354 | break;\r |
355 | \r | |
356 | case EFI_MEMORY_WT:\r | |
357 | // modify cacheability attributes\r | |
1bfda055 | 358 | EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r |
aeb61534 | 359 | // write through with no-allocate\r |
1bfda055 | 360 | EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0\r |
aeb61534 A |
361 | break;\r |
362 | \r | |
363 | case EFI_MEMORY_WB:\r | |
364 | // modify cacheability attributes\r | |
1bfda055 | 365 | EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r |
aeb61534 | 366 | // write back (with allocate)\r |
1bfda055 | 367 | EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1\r |
aeb61534 A |
368 | break;\r |
369 | \r | |
370 | case EFI_MEMORY_WP:\r | |
371 | case EFI_MEMORY_XP:\r | |
372 | case EFI_MEMORY_UCE:\r | |
373 | // cannot be implemented UEFI definition unclear for ARM\r | |
374 | // Cause a page fault if these ranges are accessed.\r | |
1bfda055 | 375 | EntryValue = TT_DESCRIPTOR_PAGE_TYPE_FAULT;\r |
225290eb | 376 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r |
aeb61534 A |
377 | break;\r |
378 | \r | |
379 | default:\r | |
380 | return EFI_UNSUPPORTED;\r | |
aeb61534 A |
381 | }\r |
382 | \r | |
383 | // obtain page table base\r | |
1bfda055 | 384 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r |
aeb61534 A |
385 | \r |
386 | // calculate number of 4KB page table entries to change\r | |
bb02cb80 | 387 | NumPageEntries = Length/SIZE_4KB;\r |
aeb61534 A |
388 | \r |
389 | // iterate for the number of 4KB pages to change\r | |
390 | Offset = 0;\r | |
391 | for(p=0; p<NumPageEntries; p++) {\r | |
392 | // calculate index into first level translation table for page table value\r | |
393 | \r | |
1bfda055 | 394 | FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r |
395 | ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r | |
aeb61534 A |
396 | \r |
397 | // read the descriptor from the first level page table\r | |
398 | Descriptor = FirstLevelTable[FirstLevelIdx];\r | |
399 | \r | |
400 | // does this descriptor need to be converted from section entry to 4K pages?\r | |
1bfda055 | 401 | if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {\r |
402 | Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r | |
aeb61534 A |
403 | if (EFI_ERROR(Status)) {\r |
404 | // exit for loop\r | |
405 | break; \r | |
406 | } \r | |
407 | \r | |
408 | // re-read descriptor\r | |
409 | Descriptor = FirstLevelTable[FirstLevelIdx];\r | |
410 | }\r | |
411 | \r | |
412 | // obtain page table base address\r | |
1bfda055 | 413 | PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);\r |
aeb61534 A |
414 | \r |
415 | // calculate index into the page table\r | |
1bfda055 | 416 | PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r |
417 | ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);\r | |
aeb61534 A |
418 | \r |
419 | // get the entry\r | |
bb02cb80 | 420 | CurrentPageTableEntry = PageTable[PageTableIndex];\r |
aeb61534 A |
421 | \r |
422 | // mask off appropriate fields\r | |
bb02cb80 | 423 | PageTableEntry = CurrentPageTableEntry & ~EntryMask;\r |
aeb61534 A |
424 | \r |
425 | // mask in new attributes and/or permissions\r | |
426 | PageTableEntry |= EntryValue;\r | |
427 | \r | |
428 | if (VirtualMask != 0) {\r | |
429 | // Make this virtual address point at a physical page\r | |
430 | PageTableEntry &= ~VirtualMask;\r | |
431 | }\r | |
aeb61534 | 432 | \r |
bb02cb80 | 433 | if (CurrentPageTableEntry != PageTableEntry) {\r |
1bfda055 | 434 | Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));\r |
435 | if ((CurrentPageTableEntry & TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) == TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) {\r | |
bb02cb80 | 436 | // The current section mapping is cacheable so Clean/Invalidate the MVA of the page\r |
437 | // Note assumes switch(Attributes), not ARMv7 possibilities\r | |
438 | WriteBackInvalidateDataCacheRange (Mva, SIZE_4KB);\r | |
439 | }\r | |
440 | \r | |
441 | // Only need to update if we are changing the entry \r | |
442 | PageTable[PageTableIndex] = PageTableEntry; \r | |
443 | ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);\r | |
444 | }\r | |
aeb61534 A |
445 | \r |
446 | Status = EFI_SUCCESS;\r | |
bb02cb80 | 447 | Offset += SIZE_4KB;\r |
aeb61534 A |
448 | \r |
449 | } // end first level translation table loop\r | |
450 | \r | |
451 | return Status;\r | |
452 | }\r | |
453 | \r | |
454 | \r | |
455 | \r | |
456 | EFI_STATUS\r | |
457 | UpdateSectionEntries (\r | |
458 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
459 | IN UINT64 Length,\r | |
460 | IN UINT64 Attributes,\r | |
461 | IN EFI_PHYSICAL_ADDRESS VirtualMask\r | |
462 | )\r | |
463 | {\r | |
464 | EFI_STATUS Status = EFI_SUCCESS;\r | |
465 | UINT32 EntryMask;\r | |
466 | UINT32 EntryValue;\r | |
467 | UINT32 FirstLevelIdx;\r | |
468 | UINT32 NumSections;\r | |
469 | UINT32 i;\r | |
bb02cb80 | 470 | UINT32 CurrentDescriptor;\r |
aeb61534 | 471 | UINT32 Descriptor;\r |
bb02cb80 | 472 | VOID *Mva;\r |
aeb61534 A |
473 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r |
474 | \r | |
475 | // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r | |
476 | // EntryValue: values at bit positions specified by EntryMask\r | |
477 | \r | |
f659880b | 478 | // Make sure we handle a section range that is unmapped \r |
1bfda055 | 479 | EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK;\r |
480 | EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;\r | |
f659880b | 481 | \r |
aeb61534 A |
482 | // Although the PI spec is unclear on this the GCD guarantees that only\r |
483 | // one Attribute bit is set at a time, so we can safely use a switch statement\r | |
484 | switch(Attributes) {\r | |
485 | case EFI_MEMORY_UC:\r | |
486 | // modify cacheability attributes\r | |
1bfda055 | 487 | EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r |
488 | if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {\r | |
2ac288f9 | 489 | // map to strongly ordered\r |
490 | EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r | |
1bfda055 | 491 | } else {\r |
2ac288f9 | 492 | // map to normal non-cachable\r |
493 | EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r | |
1bfda055 | 494 | }\r |
aeb61534 A |
495 | break;\r |
496 | \r | |
497 | case EFI_MEMORY_WC:\r | |
498 | // modify cacheability attributes\r | |
1bfda055 | 499 | EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r |
aeb61534 | 500 | // map to normal non-cachable\r |
1bfda055 | 501 | EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r |
aeb61534 A |
502 | break;\r |
503 | \r | |
504 | case EFI_MEMORY_WT:\r | |
505 | // modify cacheability attributes\r | |
1bfda055 | 506 | EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r |
aeb61534 | 507 | // write through with no-allocate\r |
1bfda055 | 508 | EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0\r |
aeb61534 A |
509 | break;\r |
510 | \r | |
511 | case EFI_MEMORY_WB:\r | |
512 | // modify cacheability attributes\r | |
1bfda055 | 513 | EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r |
aeb61534 | 514 | // write back (with allocate)\r |
1bfda055 | 515 | EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1\r |
aeb61534 A |
516 | break;\r |
517 | \r | |
518 | case EFI_MEMORY_WP:\r | |
519 | case EFI_MEMORY_XP:\r | |
520 | case EFI_MEMORY_RP:\r | |
521 | case EFI_MEMORY_UCE:\r | |
522 | // cannot be implemented UEFI definition unclear for ARM\r | |
523 | // Cause a page fault if these ranges are accessed.\r | |
1bfda055 | 524 | EntryValue = TT_DESCRIPTOR_SECTION_TYPE_FAULT;\r |
225290eb | 525 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r |
aeb61534 A |
526 | break;\r |
527 | \r | |
528 | \r | |
529 | default:\r | |
530 | return EFI_UNSUPPORTED;\r | |
aeb61534 A |
531 | }\r |
532 | \r | |
533 | // obtain page table base\r | |
1bfda055 | 534 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r |
aeb61534 A |
535 | \r |
536 | // calculate index into first level translation table for start of modification\r | |
1bfda055 | 537 | FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r |
538 | ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r | |
aeb61534 A |
539 | \r |
540 | // calculate number of 1MB first level entries this applies to\r | |
1bfda055 | 541 | NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;\r |
aeb61534 A |
542 | \r |
543 | // iterate through each descriptor\r | |
544 | for(i=0; i<NumSections; i++) {\r | |
bb02cb80 | 545 | CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];\r |
aeb61534 A |
546 | \r |
547 | // has this descriptor already been coverted to pages?\r | |
1bfda055 | 548 | if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {\r |
aeb61534 | 549 | // forward this 1MB range to page table function instead\r |
1bfda055 | 550 | Status = UpdatePageEntries ((FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT, TT_DESCRIPTOR_SECTION_SIZE, Attributes, VirtualMask);\r |
aeb61534 A |
551 | } else {\r |
552 | // still a section entry\r | |
553 | \r | |
554 | // mask off appropriate fields\r | |
bb02cb80 | 555 | Descriptor = CurrentDescriptor & ~EntryMask;\r |
aeb61534 A |
556 | \r |
557 | // mask in new attributes and/or permissions\r | |
558 | Descriptor |= EntryValue;\r | |
559 | if (VirtualMask != 0) {\r | |
560 | Descriptor &= ~VirtualMask;\r | |
561 | }\r | |
562 | \r | |
bb02cb80 | 563 | if (CurrentDescriptor != Descriptor) {\r |
1bfda055 | 564 | Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r |
565 | if ((CurrentDescriptor & TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) == TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) {\r | |
bb02cb80 | 566 | // The current section mapping is cacheable so Clean/Invalidate the MVA of the section\r |
567 | // Note assumes switch(Attributes), not ARMv7 possabilities\r | |
568 | WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);\r | |
569 | }\r | |
570 | \r | |
571 | // Only need to update if we are changing the descriptor \r | |
572 | FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r | |
573 | ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);\r | |
574 | }\r | |
aeb61534 A |
575 | \r |
576 | Status = EFI_SUCCESS;\r | |
577 | }\r | |
578 | }\r | |
579 | \r | |
580 | return Status;\r | |
581 | }\r | |
582 | \r | |
583 | EFI_STATUS \r | |
584 | ConvertSectionToPages (\r | |
585 | IN EFI_PHYSICAL_ADDRESS BaseAddress\r | |
586 | )\r | |
587 | {\r | |
588 | EFI_STATUS Status;\r | |
589 | EFI_PHYSICAL_ADDRESS PageTableAddr;\r | |
590 | UINT32 FirstLevelIdx;\r | |
591 | UINT32 SectionDescriptor;\r | |
592 | UINT32 PageTableDescriptor;\r | |
593 | UINT32 PageDescriptor;\r | |
594 | UINT32 i;\r | |
595 | \r | |
596 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r | |
597 | volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r | |
598 | \r | |
225290eb | 599 | DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r |
aeb61534 A |
600 | \r |
601 | // obtain page table base\r | |
1bfda055 | 602 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r |
aeb61534 A |
603 | \r |
604 | // calculate index into first level translation table for start of modification\r | |
1bfda055 | 605 | FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r |
606 | ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r | |
aeb61534 A |
607 | \r |
608 | // get section attributes and convert to page attributes\r | |
609 | SectionDescriptor = FirstLevelTable[FirstLevelIdx];\r | |
1bfda055 | 610 | PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r |
611 | PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(SectionDescriptor,0);\r | |
612 | PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(SectionDescriptor);\r | |
613 | PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(SectionDescriptor,0);\r | |
614 | PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(SectionDescriptor);\r | |
615 | PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S(SectionDescriptor);\r | |
aeb61534 A |
616 | \r |
617 | // allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)\r | |
618 | Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);\r | |
619 | if (EFI_ERROR(Status)) {\r | |
620 | return Status;\r | |
621 | }\r | |
622 | \r | |
623 | PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;\r | |
624 | \r | |
625 | // write the page table entries out\r | |
1bfda055 | 626 | for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {\r |
627 | PageTable[i] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (i << 12)) | PageDescriptor;\r | |
aeb61534 A |
628 | }\r |
629 | \r | |
630 | // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r | |
bb02cb80 | 631 | WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, SIZE_4KB);\r |
aeb61534 A |
632 | \r |
633 | // formulate page table entry, Domain=0, NS=0\r | |
1bfda055 | 634 | PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r |
aeb61534 A |
635 | \r |
636 | // write the page table entry out, repalcing section entry\r | |
637 | FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;\r | |
638 | \r | |
639 | return EFI_SUCCESS;\r | |
640 | }\r | |
641 | \r | |
642 | \r | |
643 | \r | |
644 | EFI_STATUS\r | |
645 | SetMemoryAttributes (\r | |
646 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
647 | IN UINT64 Length,\r | |
648 | IN UINT64 Attributes,\r | |
649 | IN EFI_PHYSICAL_ADDRESS VirtualMask\r | |
650 | )\r | |
651 | {\r | |
652 | EFI_STATUS Status;\r | |
653 | \r | |
654 | if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {\r | |
655 | // is the base and length a multiple of 1 MB?\r | |
225290eb | 656 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r |
aeb61534 A |
657 | Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);\r |
658 | } else {\r | |
659 | // base and/or length is not a multiple of 1 MB\r | |
225290eb | 660 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r |
aeb61534 A |
661 | Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);\r |
662 | }\r | |
663 | \r | |
664 | // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r | |
665 | // flush and invalidate pages\r | |
666 | ArmCleanInvalidateDataCache ();\r | |
667 | \r | |
668 | ArmInvalidateInstructionCache ();\r | |
669 | \r | |
670 | // invalidate all TLB entries so changes are synced\r | |
671 | ArmInvalidateTlb (); \r | |
672 | \r | |
673 | return Status;\r | |
674 | }\r | |
675 | \r | |
676 | \r | |
677 | /**\r | |
678 | This function modifies the attributes for the memory region specified by BaseAddress and\r | |
679 | Length from their current attributes to the attributes specified by Attributes.\r | |
680 | \r | |
681 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
682 | @param BaseAddress The physical address that is the start address of a memory region.\r | |
683 | @param Length The size in bytes of the memory region.\r | |
684 | @param Attributes The bit mask of attributes to set for the memory region.\r | |
685 | \r | |
686 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
687 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
688 | BaseAddress and Length cannot be modified.\r | |
689 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
690 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
691 | the memory resource range.\r | |
692 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
693 | resource range specified by BaseAddress and Length.\r | |
694 | The bit mask of attributes is not support for the memory resource\r | |
695 | range specified by BaseAddress and Length.\r | |
696 | \r | |
697 | **/\r | |
698 | EFI_STATUS\r | |
699 | EFIAPI\r | |
700 | CpuSetMemoryAttributes (\r | |
701 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
702 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
703 | IN UINT64 Length,\r | |
704 | IN UINT64 Attributes\r | |
705 | )\r | |
706 | {\r | |
225290eb | 707 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));\r |
bb02cb80 | 708 | if ( ((BaseAddress & (SIZE_4KB-1)) != 0) || ((Length & (SIZE_4KB-1)) != 0)){\r |
709 | // minimum granularity is SIZE_4KB (4KB on ARM)\r | |
710 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is SIZE_4KB\n", BaseAddress, Length, Attributes));\r | |
aeb61534 A |
711 | return EFI_UNSUPPORTED;\r |
712 | }\r | |
713 | \r | |
714 | return SetMemoryAttributes (BaseAddress, Length, Attributes, 0);\r | |
715 | }\r | |
716 | \r | |
717 | \r | |
718 | \r | |
719 | //\r | |
720 | // Add a new protocol to support \r | |
721 | //\r | |
722 | \r | |
723 | EFI_STATUS\r | |
724 | EFIAPI\r | |
725 | CpuConvertPagesToUncachedVirtualAddress (\r | |
726 | IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,\r | |
727 | IN EFI_PHYSICAL_ADDRESS Address,\r | |
728 | IN UINTN Length,\r | |
729 | IN EFI_PHYSICAL_ADDRESS VirtualMask,\r | |
730 | OUT UINT64 *Attributes OPTIONAL\r | |
731 | )\r | |
732 | {\r | |
733 | EFI_STATUS Status;\r | |
734 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;\r | |
735 | \r | |
736 | \r | |
737 | if (Attributes != NULL) {\r | |
738 | Status = gDS->GetMemorySpaceDescriptor (Address, &GcdDescriptor);\r | |
739 | if (!EFI_ERROR (Status)) {\r | |
740 | *Attributes = GcdDescriptor.Attributes;\r | |
741 | }\r | |
742 | }\r | |
225290eb | 743 | \r |
aeb61534 A |
744 | //\r |
745 | // Make this address range page fault if accessed. If it is a DMA buffer than this would \r | |
746 | // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask\r | |
747 | // to that address. \r | |
748 | //\r | |
f659880b | 749 | Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0);\r |
aeb61534 A |
750 | if (!EFI_ERROR (Status)) {\r |
751 | Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);\r | |
752 | }\r | |
753 | \r | |
6f72e28d | 754 | DEBUG ((DEBUG_INFO | DEBUG_LOAD, "ConvertPagesToUncachedVirtualAddress()\n Unmapped 0x%08lx Mapped 0x%08lx 0x%x bytes\n", Address, Address | VirtualMask, Length));\r |
755 | \r | |
aeb61534 A |
756 | return Status;\r |
757 | }\r | |
758 | \r | |
759 | \r | |
760 | EFI_STATUS\r | |
761 | EFIAPI\r | |
6f72e28d | 762 | CpuReconvertPages (\r |
aeb61534 A |
763 | IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,\r |
764 | IN EFI_PHYSICAL_ADDRESS Address,\r | |
765 | IN UINTN Length,\r | |
766 | IN EFI_PHYSICAL_ADDRESS VirtualMask,\r | |
767 | IN UINT64 Attributes\r | |
768 | )\r | |
769 | {\r | |
770 | EFI_STATUS Status;\r | |
6f72e28d | 771 | \r |
772 | DEBUG ((DEBUG_INFO | DEBUG_LOAD, "CpuReconvertPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes));\r | |
773 | \r | |
774 | //\r | |
aeb61534 A |
775 | // Unmap the alaised Address\r |
776 | //\r | |
f659880b | 777 | Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);\r |
aeb61534 A |
778 | if (!EFI_ERROR (Status)) {\r |
779 | //\r | |
780 | // Restore atttributes\r | |
781 | //\r | |
782 | Status = SetMemoryAttributes (Address, Length, Attributes, 0);\r | |
783 | }\r | |
784 | \r | |
785 | return Status;\r | |
786 | }\r | |
787 | \r | |
788 | \r | |
789 | VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages = {\r | |
790 | CpuConvertPagesToUncachedVirtualAddress,\r | |
6f72e28d | 791 | CpuReconvertPages\r |
aeb61534 | 792 | };\r |