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Commit | Line | Data |
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3402aac7 | 1 | #------------------------------------------------------------------------------\r |
bd6b9799 | 2 | #\r |
3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
d6dc67ba | 4 | # Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
0efaa42f | 5 | # Copyright (c) 2016, Linaro Limited. All rights reserved.\r |
bd6b9799 | 6 | #\r |
4059386c | 7 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
bd6b9799 | 8 | #\r |
9 | #------------------------------------------------------------------------------\r | |
10 | \r | |
11 | #include <AsmMacroIoLib.h>\r | |
12 | \r | |
0efaa42f | 13 | ASM_FUNC(ArmIsMpCore)\r |
bd6b9799 | 14 | mrc p15,0,R0,c0,c0,5\r |
15 | // Get Multiprocessing extension (bit31) & U bit (bit30)\r | |
16 | and R0, R0, #0xC0000000\r | |
5a539eb5 OM |
17 | // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system\r |
18 | cmp R0, #0x80000000\r | |
19 | moveq R0, #1\r | |
20 | movne R0, #0\r | |
bd6b9799 | 21 | bx LR\r |
22 | \r | |
0efaa42f | 23 | ASM_FUNC(ArmEnableAsynchronousAbort)\r |
bd6b9799 | 24 | cpsie a\r |
25 | isb\r | |
26 | bx LR\r | |
27 | \r | |
0efaa42f | 28 | ASM_FUNC(ArmDisableAsynchronousAbort)\r |
bd6b9799 | 29 | cpsid a\r |
30 | isb\r | |
31 | bx LR\r | |
32 | \r | |
0efaa42f | 33 | ASM_FUNC(ArmEnableIrq)\r |
bd6b9799 | 34 | cpsie i\r |
35 | isb\r | |
36 | bx LR\r | |
37 | \r | |
0efaa42f | 38 | ASM_FUNC(ArmDisableIrq)\r |
bd6b9799 | 39 | cpsid i\r |
40 | isb\r | |
41 | bx LR\r | |
42 | \r | |
0efaa42f | 43 | ASM_FUNC(ArmEnableFiq)\r |
bd6b9799 | 44 | cpsie f\r |
45 | isb\r | |
46 | bx LR\r | |
47 | \r | |
0efaa42f | 48 | ASM_FUNC(ArmDisableFiq)\r |
bd6b9799 | 49 | cpsid f\r |
50 | isb\r | |
51 | bx LR\r | |
52 | \r | |
0efaa42f | 53 | ASM_FUNC(ArmEnableInterrupts)\r |
bd6b9799 | 54 | cpsie if\r |
55 | isb\r | |
56 | bx LR\r | |
57 | \r | |
0efaa42f | 58 | ASM_FUNC(ArmDisableInterrupts)\r |
bd6b9799 | 59 | cpsid if\r |
60 | isb\r | |
61 | bx LR\r | |
3402aac7 | 62 | \r |
827a71cc RC |
63 | ASM_FUNC(ArmReadIdMmfr4)\r |
64 | mrc p15,0,r0,c0,c2,6 @ Read ID_MMFR4 Register\r | |
65 | bx lr\r | |
66 | \r | |
93ff7a4e | 67 | // UINTN\r |
bd6b9799 | 68 | // ReadCCSIDR (\r |
69 | // IN UINT32 CSSELR\r | |
3402aac7 | 70 | // )\r |
0efaa42f | 71 | ASM_FUNC(ReadCCSIDR)\r |
bd6b9799 | 72 | mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)\r |
73 | isb\r | |
74 | mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)\r | |
75 | bx lr\r | |
3402aac7 | 76 | \r |
84a6db75 RC |
77 | // UINT32\r |
78 | // ReadCCSIDR2 (\r | |
79 | // IN UINT32 CSSELR\r | |
80 | // )\r | |
81 | ASM_FUNC(ReadCCSIDR2)\r | |
82 | mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)\r | |
83 | isb\r | |
84 | mrc p15,1,r0,c0,c0,2 @ Read current CP15 Cache Size ID Register (CCSIDR2)\r | |
85 | bx lr\r | |
86 | \r | |
3402aac7 | 87 | // UINT32\r |
bd6b9799 | 88 | // ReadCLIDR (\r |
89 | // IN UINT32 CSSELR\r | |
3402aac7 | 90 | // )\r |
0efaa42f | 91 | ASM_FUNC(ReadCLIDR)\r |
bd6b9799 | 92 | mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register\r |
93 | bx lr\r | |
94 | \r | |
0efaa42f | 95 | ASM_FUNC(ArmReadNsacr)\r |
d6dc67ba OM |
96 | mrc p15, 0, r0, c1, c1, 2\r |
97 | bx lr\r | |
98 | \r | |
0efaa42f | 99 | ASM_FUNC(ArmWriteNsacr)\r |
d6dc67ba OM |
100 | mcr p15, 0, r0, c1, c1, 2\r |
101 | bx lr\r | |
102 | \r | |
bd6b9799 | 103 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |