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Commit | Line | Data |
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3402aac7 | 1 | //------------------------------------------------------------------------------\r |
bd6b9799 | 2 | //\r |
3 | // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
d6dc67ba | 4 | // Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
bd6b9799 | 5 | //\r |
4059386c | 6 | // SPDX-License-Identifier: BSD-2-Clause-Patent\r |
bd6b9799 | 7 | //\r |
8 | //------------------------------------------------------------------------------\r | |
9 | \r | |
10 | \r | |
efda1775 EC |
11 | \r |
12 | INCLUDE AsmMacroExport.inc\r | |
bd6b9799 | 13 | \r |
14 | \r | |
15 | //------------------------------------------------------------------------------\r | |
16 | \r | |
efda1775 | 17 | RVCT_ASM_EXPORT ArmIsMpCore\r |
bd6b9799 | 18 | mrc p15,0,R0,c0,c0,5\r |
19 | // Get Multiprocessing extension (bit31) & U bit (bit30)\r | |
20 | and R0, R0, #0xC0000000\r | |
5a539eb5 OM |
21 | // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system\r |
22 | cmp R0, #0x80000000\r | |
23 | moveq R0, #1\r | |
24 | movne R0, #0\r | |
bd6b9799 | 25 | bx LR\r |
26 | \r | |
efda1775 | 27 | RVCT_ASM_EXPORT ArmEnableAsynchronousAbort\r |
bd6b9799 | 28 | cpsie a\r |
29 | isb\r | |
30 | bx LR\r | |
31 | \r | |
efda1775 | 32 | RVCT_ASM_EXPORT ArmDisableAsynchronousAbort\r |
bd6b9799 | 33 | cpsid a\r |
34 | isb\r | |
35 | bx LR\r | |
36 | \r | |
efda1775 | 37 | RVCT_ASM_EXPORT ArmEnableIrq\r |
bd6b9799 | 38 | cpsie i\r |
39 | isb\r | |
40 | bx LR\r | |
41 | \r | |
efda1775 | 42 | RVCT_ASM_EXPORT ArmDisableIrq\r |
bd6b9799 | 43 | cpsid i\r |
44 | isb\r | |
45 | bx LR\r | |
46 | \r | |
efda1775 | 47 | RVCT_ASM_EXPORT ArmEnableFiq\r |
bd6b9799 | 48 | cpsie f\r |
49 | isb\r | |
50 | bx LR\r | |
51 | \r | |
efda1775 | 52 | RVCT_ASM_EXPORT ArmDisableFiq\r |
bd6b9799 | 53 | cpsid f\r |
54 | isb\r | |
55 | bx LR\r | |
56 | \r | |
efda1775 | 57 | RVCT_ASM_EXPORT ArmEnableInterrupts\r |
bd6b9799 | 58 | cpsie if\r |
59 | isb\r | |
60 | bx LR\r | |
61 | \r | |
efda1775 | 62 | RVCT_ASM_EXPORT ArmDisableInterrupts\r |
bd6b9799 | 63 | cpsid if\r |
64 | isb\r | |
65 | bx LR\r | |
3402aac7 | 66 | \r |
827a71cc RC |
67 | RVCT_ASM_EXPORT ArmReadIdMmfr4\r |
68 | mrc p15,0,r0,c0,c2,6 ; Read ID_MMFR4 Register\r | |
69 | bx LR\r | |
70 | \r | |
93ff7a4e | 71 | // UINTN\r |
bd6b9799 | 72 | // ReadCCSIDR (\r |
73 | // IN UINT32 CSSELR\r | |
3402aac7 | 74 | // )\r |
efda1775 | 75 | RVCT_ASM_EXPORT ReadCCSIDR\r |
bd6b9799 | 76 | mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)\r |
77 | isb\r | |
78 | mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)\r | |
79 | bx lr\r | |
3402aac7 | 80 | \r |
84a6db75 RC |
81 | // UINT32\r |
82 | // ReadCCSIDR2 (\r | |
83 | // IN UINT32 CSSELR\r | |
84 | // )\r | |
85 | RVCT_ASM_EXPORT ReadCCSIDR2\r | |
86 | mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)\r | |
87 | isb\r | |
88 | mrc p15,1,r0,c0,c0,2 ; Read current CP15 Cache Size ID Register (CCSIDR2)\r | |
89 | bx lr\r | |
90 | \r | |
3402aac7 | 91 | // UINT32\r |
bd6b9799 | 92 | // ReadCLIDR (\r |
93 | // IN UINT32 CSSELR\r | |
3402aac7 | 94 | // )\r |
efda1775 | 95 | RVCT_ASM_EXPORT ReadCLIDR\r |
bd6b9799 | 96 | mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register\r |
97 | bx lr\r | |
d6dc67ba | 98 | \r |
efda1775 | 99 | RVCT_ASM_EXPORT ArmReadNsacr\r |
d6dc67ba OM |
100 | mrc p15, 0, r0, c1, c1, 2\r |
101 | bx lr\r | |
102 | \r | |
efda1775 | 103 | RVCT_ASM_EXPORT ArmWriteNsacr\r |
d6dc67ba OM |
104 | mcr p15, 0, r0, c1, c1, 2\r |
105 | bx lr\r | |
106 | \r | |
2575b726 | 107 | END\r |