]>
Commit | Line | Data |
---|---|---|
2ef2b01e A |
1 | #------------------------------------------------------------------------------ |
2 | # | |
d6ebcab7 | 3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> |
2ef2b01e | 4 | # |
d6ebcab7 | 5 | # This program and the accompanying materials |
2ef2b01e A |
6 | # are licensed and made available under the terms and conditions of the BSD License |
7 | # which accompanies this distribution. The full text of the license may be found at | |
8 | # http://opensource.org/licenses/bsd-license.php | |
9 | # | |
10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | # | |
13 | #------------------------------------------------------------------------------ | |
14 | ||
15 | .text | |
16 | .align 2 | |
17 | .globl ASM_PFX(ArmCleanInvalidateDataCache) | |
63ca7402 | 18 | INTERWORK_FUNC(ArmCleanInvalidateDataCache) |
2ef2b01e | 19 | .globl ASM_PFX(ArmCleanDataCache) |
63ca7402 | 20 | INTERWORK_FUNC(ArmCleanDataCache) |
2ef2b01e | 21 | .globl ASM_PFX(ArmInvalidateDataCache) |
63ca7402 | 22 | INTERWORK_FUNC(ArmInvalidateDataCache) |
2ef2b01e | 23 | .globl ASM_PFX(ArmInvalidateInstructionCache) |
63ca7402 | 24 | INTERWORK_FUNC(ArmInvalidateInstructionCache) |
2ef2b01e | 25 | .globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA) |
63ca7402 | 26 | INTERWORK_FUNC(ArmInvalidateDataCacheEntryByMVA) |
2ef2b01e | 27 | .globl ASM_PFX(ArmCleanDataCacheEntryByMVA) |
63ca7402 | 28 | INTERWORK_FUNC(ArmCleanDataCacheEntryByMVA) |
2ef2b01e | 29 | .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA) |
63ca7402 | 30 | INTERWORK_FUNC(ArmCleanInvalidateDataCacheEntryByMVA) |
2ef2b01e | 31 | .globl ASM_PFX(ArmEnableMmu) |
63ca7402 | 32 | INTERWORK_FUNC(ArmEnableMmu) |
2ef2b01e | 33 | .globl ASM_PFX(ArmDisableMmu) |
63ca7402 | 34 | INTERWORK_FUNC(ArmDisableMmu) |
c2b5ca8b | 35 | .globl ASM_PFX(ArmMmuEnabled) |
63ca7402 | 36 | INTERWORK_FUNC(ArmMmuEnabled) |
2ef2b01e | 37 | .globl ASM_PFX(ArmEnableDataCache) |
63ca7402 | 38 | INTERWORK_FUNC(ArmEnableDataCache) |
2ef2b01e | 39 | .globl ASM_PFX(ArmDisableDataCache) |
63ca7402 | 40 | INTERWORK_FUNC(ArmDisableDataCache) |
2ef2b01e | 41 | .globl ASM_PFX(ArmEnableInstructionCache) |
63ca7402 | 42 | INTERWORK_FUNC(ArmEnableInstructionCache) |
2ef2b01e | 43 | .globl ASM_PFX(ArmDisableInstructionCache) |
63ca7402 | 44 | INTERWORK_FUNC(ArmDisableInstructionCache) |
2ef2b01e | 45 | .globl ASM_PFX(ArmEnableBranchPrediction) |
63ca7402 | 46 | INTERWORK_FUNC(ArmEnableBranchPrediction) |
2ef2b01e | 47 | .globl ASM_PFX(ArmDisableBranchPrediction) |
63ca7402 | 48 | INTERWORK_FUNC(ArmDisableBranchPrediction) |
4b9fa129 | 49 | .globl ASM_PFX(ArmDataMemoryBarrier) |
63ca7402 | 50 | INTERWORK_FUNC(ArmDataMemoryBarrier) |
4b9fa129 | 51 | .globl ASM_PFX(ArmDataSyncronizationBarrier) |
63ca7402 | 52 | INTERWORK_FUNC(ArmDataSyncronizationBarrier) |
4b9fa129 | 53 | .globl ASM_PFX(ArmInstructionSynchronizationBarrier) |
63ca7402 | 54 | INTERWORK_FUNC(ArmInstructionSynchronizationBarrier) |
4b9fa129 | 55 | |
2ef2b01e A |
56 | |
57 | .set DC_ON, (1<<2) | |
58 | .set IC_ON, (1<<12) | |
59 | ||
60 | #------------------------------------------------------------------------------ | |
61 | ||
62 | ASM_PFX(ArmInvalidateDataCacheEntryByMVA): | |
63 | mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line | |
64 | bx lr | |
65 | ||
66 | ASM_PFX(ArmCleanDataCacheEntryByMVA): | |
67 | mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line | |
68 | bx lr | |
69 | ||
70 | ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): | |
71 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line | |
72 | bx lr | |
73 | ||
74 | ASM_PFX(ArmEnableInstructionCache): | |
75 | ldr r1,=IC_ON | |
76 | mrc p15,0,r0,c1,c0,0 @Read control register configuration data | |
77 | orr r0,r0,r1 @Set I bit | |
78 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
79 | bx LR | |
80 | ||
81 | ASM_PFX(ArmDisableInstructionCache): | |
82 | ldr r1,=IC_ON | |
83 | mrc p15,0,r0,c1,c0,0 @Read control register configuration data | |
84 | bic r0,r0,r1 @Clear I bit. | |
85 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
86 | bx LR | |
87 | ||
88 | ASM_PFX(ArmInvalidateInstructionCache): | |
89 | mov r0,#0 | |
90 | mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache. | |
91 | @Also flushes the branch target cache. | |
92 | mov r0,#0 | |
93 | mcr p15,0,r0,c7,c10,4 @Data write buffer | |
94 | bx LR | |
95 | ||
96 | ASM_PFX(ArmEnableMmu): | |
97 | mrc p15,0,R0,c1,c0,0 | |
98 | orr R0,R0,#1 | |
99 | mcr p15,0,R0,c1,c0,0 | |
100 | bx LR | |
101 | ||
c2b5ca8b A |
102 | ASM_PFX(ArmMmuEnabled): |
103 | mrc p15,0,R0,c1,c0,0 | |
104 | and R0,R0,#1 | |
105 | bx LR | |
106 | ||
2ef2b01e A |
107 | ASM_PFX(ArmDisableMmu): |
108 | mrc p15,0,R0,c1,c0,0 | |
109 | bic R0,R0,#1 | |
110 | mcr p15,0,R0,c1,c0,0 | |
111 | mov R0,#0 | |
112 | mcr p15,0,R0,c7,c10,4 @Drain write buffer | |
113 | bx LR | |
114 | ||
115 | ASM_PFX(ArmEnableDataCache): | |
116 | ldr R1,=DC_ON | |
117 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
118 | orr R0,R0,R1 @Set C bit | |
119 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
120 | bx LR | |
121 | ||
122 | ASM_PFX(ArmDisableDataCache): | |
123 | ldr R1,=DC_ON | |
124 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
125 | bic R0,R0,R1 @Clear C bit | |
126 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
127 | bx LR | |
128 | ||
129 | ASM_PFX(ArmCleanDataCache): | |
130 | mrc p15,0,r15,c7,c10,3 | |
131 | bne ASM_PFX(ArmCleanDataCache) | |
132 | mov R0,#0 | |
133 | mcr p15,0,R0,c7,c10,4 @Drain write buffer | |
134 | bx LR | |
135 | ||
136 | ASM_PFX(ArmInvalidateDataCache): | |
137 | mov R0,#0 | |
138 | mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache | |
139 | mov R0,#0 | |
140 | mcr p15,0,R0,c7,c10,4 @Drain write buffer | |
141 | bx LR | |
142 | ||
143 | ASM_PFX(ArmCleanInvalidateDataCache): | |
144 | mrc p15,0,r15,c7,c14,3 | |
145 | bne ASM_PFX(ArmCleanInvalidateDataCache) | |
146 | mov R0,#0 | |
147 | mcr p15,0,R0,c7,c10,4 @Drain write buffer | |
148 | bx LR | |
149 | ||
150 | ASM_PFX(ArmEnableBranchPrediction): | |
151 | bx LR @Branch prediction is not supported. | |
152 | ||
153 | ASM_PFX(ArmDisableBranchPrediction): | |
154 | bx LR @Branch prediction is not supported. | |
155 | ||
4b9fa129 | 156 | ASM_PFX(ArmDataMemoryBarrier): |
157 | mov R0, #0 | |
158 | mcr P15, #0, R0, C7, C10, #5 @ check if this is OK? | |
159 | bx LR | |
160 | ||
161 | ASM_PFX(ArmDataSyncronizationBarrier): | |
162 | mov R0, #0 | |
163 | mcr P15, #0, R0, C7, C10, #4 @ check if this is OK? | |
164 | bx LR | |
165 | ||
166 | ASM_PFX(ArmInstructionSynchronizationBarrier): | |
167 | mov R0, #0 | |
168 | mcr P15, #0, R0, C7, C5, #4 @ check if this is OK? | |
169 | bx LR | |
170 | ||
2ef2b01e A |
171 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED |
172 |