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2ef2b01e A |
1 | #------------------------------------------------------------------------------ |
2 | # | |
d6ebcab7 | 3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> |
2ef2b01e | 4 | # |
d6ebcab7 | 5 | # This program and the accompanying materials |
2ef2b01e A |
6 | # are licensed and made available under the terms and conditions of the BSD License |
7 | # which accompanies this distribution. The full text of the license may be found at | |
8 | # http://opensource.org/licenses/bsd-license.php | |
9 | # | |
10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | # | |
13 | #------------------------------------------------------------------------------ | |
14 | ||
548af3e7 | 15 | .text |
16 | .align 2 | |
2ef2b01e | 17 | |
1bfda055 | 18 | GCC_ASM_EXPORT (ArmInvalidateInstructionCache) |
19 | GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA) | |
20 | GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA) | |
21 | GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA) | |
22 | GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay) | |
23 | GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay) | |
24 | GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay) | |
25 | GCC_ASM_EXPORT (ArmDrainWriteBuffer) | |
26 | GCC_ASM_EXPORT (ArmEnableMmu) | |
27 | GCC_ASM_EXPORT (ArmDisableMmu) | |
28 | GCC_ASM_EXPORT (ArmDisableCachesAndMmu) | |
29 | GCC_ASM_EXPORT (ArmMmuEnabled) | |
30 | GCC_ASM_EXPORT (ArmEnableDataCache) | |
31 | GCC_ASM_EXPORT (ArmDisableDataCache) | |
32 | GCC_ASM_EXPORT (ArmEnableInstructionCache) | |
33 | GCC_ASM_EXPORT (ArmDisableInstructionCache) | |
34 | GCC_ASM_EXPORT (ArmEnableSWPInstruction) | |
35 | GCC_ASM_EXPORT (ArmEnableBranchPrediction) | |
36 | GCC_ASM_EXPORT (ArmDisableBranchPrediction) | |
f0fef790 | 37 | GCC_ASM_EXPORT (ArmSetLowVectors) |
38 | GCC_ASM_EXPORT (ArmSetHighVectors) | |
1bfda055 | 39 | GCC_ASM_EXPORT (ArmV7AllDataCachesOperation) |
40 | GCC_ASM_EXPORT (ArmDataMemoryBarrier) | |
41 | GCC_ASM_EXPORT (ArmDataSyncronizationBarrier) | |
42 | GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier) | |
43 | GCC_ASM_EXPORT (ArmWriteNsacr) | |
44 | GCC_ASM_EXPORT (ArmWriteScr) | |
45 | GCC_ASM_EXPORT (ArmWriteVMBar) | |
46 | GCC_ASM_EXPORT (ArmWriteVBar) | |
47 | GCC_ASM_EXPORT (ArmWriteCPACR) | |
48 | GCC_ASM_EXPORT (ArmEnableVFP) | |
49 | GCC_ASM_EXPORT (ArmCallWFI) | |
50 | GCC_ASM_EXPORT (ArmWriteAuxCr) | |
51 | GCC_ASM_EXPORT (ArmReadAuxCr) | |
52 | GCC_ASM_EXPORT (ArmReadCbar) | |
53 | GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb) | |
54 | GCC_ASM_EXPORT (ArmReadMpidr) | |
55 | ||
2ef2b01e A |
56 | .set DC_ON, (0x1<<2) |
57 | .set IC_ON, (0x1<<12) | |
1bfda055 | 58 | .set CTRL_M_BIT, (1 << 0) |
59 | .set CTRL_C_BIT, (1 << 2) | |
60 | .set CTRL_B_BIT, (1 << 7) | |
61 | .set CTRL_I_BIT, (1 << 12) | |
2ef2b01e | 62 | |
7800c283 | 63 | |
2ef2b01e | 64 | ASM_PFX(ArmInvalidateDataCacheEntryByMVA): |
98bc0c8c | 65 | mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line |
66 | dsb | |
67 | isb | |
2ef2b01e A |
68 | bx lr |
69 | ||
2ef2b01e A |
70 | ASM_PFX(ArmCleanDataCacheEntryByMVA): |
71 | mcr p15, 0, r0, c7, c10, 1 @clean single data cache line | |
98bc0c8c | 72 | dsb |
73 | isb | |
2ef2b01e A |
74 | bx lr |
75 | ||
76 | ||
77 | ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): | |
78 | mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line | |
98bc0c8c | 79 | dsb |
80 | isb | |
2ef2b01e A |
81 | bx lr |
82 | ||
83 | ||
84 | ASM_PFX(ArmInvalidateDataCacheEntryBySetWay): | |
2ac288f9 | 85 | mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line |
98bc0c8c | 86 | dsb |
87 | isb | |
2ef2b01e A |
88 | bx lr |
89 | ||
90 | ||
91 | ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay): | |
2ac288f9 | 92 | mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line |
98bc0c8c | 93 | dsb |
94 | isb | |
2ef2b01e A |
95 | bx lr |
96 | ||
97 | ||
98 | ASM_PFX(ArmCleanDataCacheEntryBySetWay): | |
2ac288f9 | 99 | mcr p15, 0, r0, c7, c10, 2 @ Clean this line |
98bc0c8c | 100 | dsb |
101 | isb | |
2ef2b01e A |
102 | bx lr |
103 | ||
2ef2b01e | 104 | ASM_PFX(ArmInvalidateInstructionCache): |
2ef2b01e | 105 | mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache |
98bc0c8c | 106 | dsb |
107 | isb | |
2ef2b01e A |
108 | bx LR |
109 | ||
110 | ASM_PFX(ArmEnableMmu): | |
111 | mrc p15,0,R0,c1,c0,0 | |
112 | orr R0,R0,#1 | |
113 | mcr p15,0,R0,c1,c0,0 | |
548af3e7 | 114 | dsb |
115 | isb | |
2ef2b01e A |
116 | bx LR |
117 | ||
c2b5ca8b | 118 | |
2ef2b01e | 119 | ASM_PFX(ArmDisableMmu): |
2ef2b01e A |
120 | mrc p15,0,R0,c1,c0,0 |
121 | bic R0,R0,#1 | |
122 | mcr p15,0,R0,c1,c0,0 @Disable MMU | |
7800c283 | 123 | |
2ac288f9 | 124 | mcr p15,0,R0,c8,c7,0 @Invalidate TLB |
7800c283 | 125 | mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array |
98bc0c8c | 126 | dsb |
127 | isb | |
2ef2b01e A |
128 | bx LR |
129 | ||
1bfda055 | 130 | ASM_PFX(ArmDisableCachesAndMmu): |
131 | mrc p15, 0, r0, c1, c0, 0 @ Get control register | |
132 | bic r0, r0, #CTRL_M_BIT @ Disable MMU | |
133 | bic r0, r0, #CTRL_C_BIT @ Disable D Cache | |
134 | bic r0, r0, #CTRL_I_BIT @ Disable I Cache | |
135 | mcr p15, 0, r0, c1, c0, 0 @ Write control register | |
136 | dsb | |
137 | isb | |
138 | bx LR | |
139 | ||
140 | ASM_PFX(ArmMmuEnabled): | |
141 | mrc p15,0,R0,c1,c0,0 | |
142 | and R0,R0,#1 | |
143 | bx LR | |
144 | ||
2ef2b01e A |
145 | ASM_PFX(ArmEnableDataCache): |
146 | ldr R1,=DC_ON | |
147 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
148 | orr R0,R0,R1 @Set C bit | |
149 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
98bc0c8c | 150 | dsb |
151 | isb | |
2ef2b01e A |
152 | bx LR |
153 | ||
154 | ASM_PFX(ArmDisableDataCache): | |
155 | ldr R1,=DC_ON | |
156 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
157 | bic R0,R0,R1 @Clear C bit | |
158 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
98bc0c8c | 159 | dsb |
160 | isb | |
2ef2b01e A |
161 | bx LR |
162 | ||
163 | ASM_PFX(ArmEnableInstructionCache): | |
164 | ldr R1,=IC_ON | |
165 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
166 | orr R0,R0,R1 @Set I bit | |
167 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
98bc0c8c | 168 | dsb |
169 | isb | |
2ef2b01e A |
170 | bx LR |
171 | ||
172 | ASM_PFX(ArmDisableInstructionCache): | |
173 | ldr R1,=IC_ON | |
174 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
175 | bic R0,R0,R1 @Clear I bit. | |
176 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
98bc0c8c | 177 | dsb |
178 | isb | |
2ef2b01e A |
179 | bx LR |
180 | ||
1bfda055 | 181 | ASM_PFX(ArmEnableSWPInstruction): |
182 | mrc p15, 0, r0, c1, c0, 0 | |
183 | orr r0, r0, #0x00000400 | |
184 | mcr p15, 0, r0, c1, c0, 0 | |
185 | isb | |
186 | bx LR | |
187 | ||
2ef2b01e A |
188 | ASM_PFX(ArmEnableBranchPrediction): |
189 | mrc p15, 0, r0, c1, c0, 0 | |
190 | orr r0, r0, #0x00000800 | |
191 | mcr p15, 0, r0, c1, c0, 0 | |
98bc0c8c | 192 | dsb |
193 | isb | |
2ef2b01e A |
194 | bx LR |
195 | ||
196 | ASM_PFX(ArmDisableBranchPrediction): | |
197 | mrc p15, 0, r0, c1, c0, 0 | |
198 | bic r0, r0, #0x00000800 | |
199 | mcr p15, 0, r0, c1, c0, 0 | |
98bc0c8c | 200 | dsb |
201 | isb | |
2ef2b01e A |
202 | bx LR |
203 | ||
f0fef790 | 204 | ASM_PFX(ArmSetLowVectors): |
205 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) | |
206 | bic r0, r0, #0x00002000 @ clear V bit | |
207 | mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) | |
208 | isb | |
209 | bx LR | |
210 | ||
211 | ASM_PFX(ArmSetHighVectors): | |
212 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) | |
213 | orr r0, r0, #0x00002000 @ clear V bit | |
214 | mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) | |
215 | isb | |
216 | bx LR | |
98bc0c8c | 217 | |
218 | ASM_PFX(ArmV7AllDataCachesOperation): | |
219 | stmfd SP!,{r4-r12, LR} | |
220 | mov R1, R0 @ Save Function call in R1 | |
221 | mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR | |
222 | ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC) | |
223 | mov R3, R3, LSR #23 @ Cache level value (naturally aligned) | |
224 | beq L_Finished | |
225 | mov R10, #0 | |
226 | ||
227 | Loop1: | |
228 | add R2, R10, R10, LSR #1 @ Work out 3xcachelevel | |
229 | mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level | |
230 | and R12, R12, #7 @ get those 3 bits alone | |
231 | cmp R12, #2 | |
232 | blt L_Skip @ no cache or only instruction cache at this level | |
233 | mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction | |
548af3e7 | 234 | isb @ isb to sync the change to the CacheSizeID reg |
235 | mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR) | |
98bc0c8c | 236 | and R2, R12, #0x7 @ extract the line length field |
548af3e7 | 237 | add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes) |
238 | @ ldr R4, =0x3FF | |
98bc0c8c | 239 | mov R4, #0x400 |
240 | sub R4, R4, #1 | |
241 | ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned) | |
242 | clz R5, R4 @ R5 is the bit position of the way size increment | |
548af3e7 | 243 | @ ldr R7, =0x00007FFF |
98bc0c8c | 244 | mov R7, #0x00008000 |
245 | sub R7, R7, #1 | |
246 | ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned) | |
247 | ||
248 | Loop2: | |
249 | mov R9, R4 @ R9 working copy of the max way size (right aligned) | |
250 | ||
251 | Loop3: | |
252 | orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11 | |
253 | orr R0, R0, R7, LSL R2 @ factor in the index number | |
254 | ||
255 | blx R1 | |
256 | ||
257 | subs R9, R9, #1 @ decrement the way number | |
258 | bge Loop3 | |
259 | subs R7, R7, #1 @ decrement the index | |
260 | bge Loop2 | |
261 | L_Skip: | |
262 | add R10, R10, #2 @ increment the cache number | |
263 | cmp R3, R10 | |
264 | bgt Loop1 | |
265 | ||
266 | L_Finished: | |
7800c283 | 267 | dsb |
98bc0c8c | 268 | ldmfd SP!, {r4-r12, lr} |
269 | bx LR | |
270 | ||
026c3d34 | 271 | ASM_PFX(ArmDataMemoryBarrier): |
272 | dmb | |
273 | bx LR | |
274 | ||
275 | ASM_PFX(ArmDataSyncronizationBarrier): | |
7800c283 | 276 | ASM_PFX(ArmDrainWriteBuffer): |
026c3d34 | 277 | dsb |
278 | bx LR | |
279 | ||
280 | ASM_PFX(ArmInstructionSynchronizationBarrier): | |
281 | isb | |
282 | bx LR | |
283 | ||
1bfda055 | 284 | ASM_PFX(ArmWriteNsacr): |
285 | mcr p15, 0, r0, c1, c1, 2 | |
286 | bx lr | |
287 | ||
288 | ASM_PFX(ArmWriteScr): | |
289 | mcr p15, 0, r0, c1, c1, 0 | |
290 | bx lr | |
291 | ||
292 | ASM_PFX(ArmWriteAuxCr): | |
293 | mcr p15, 0, r0, c1, c0, 1 | |
294 | bx lr | |
295 | ||
296 | ASM_PFX(ArmReadAuxCr): | |
297 | mrc p15, 0, r0, c1, c0, 1 | |
298 | bx lr | |
299 | ||
300 | ASM_PFX(ArmWriteVMBar): | |
301 | mcr p15, 0, r0, c12, c0, 1 | |
302 | bx lr | |
303 | ||
304 | ASM_PFX(ArmWriteVBar): | |
f0fef790 | 305 | # Set the Address of the Vector Table in the VBAR register |
1bfda055 | 306 | mcr p15, 0, r0, c12, c0, 0 |
f0fef790 | 307 | # Ensure the SCTLR.V bit is clear |
308 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) | |
309 | bic r0, r0, #0x00002000 @ clear V bit | |
310 | mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) | |
311 | isb | |
1bfda055 | 312 | bx lr |
313 | ||
314 | ASM_PFX(ArmWriteCPACR): | |
315 | mcr p15, 0, r0, c1, c0, 2 | |
316 | bx lr | |
317 | ||
318 | ASM_PFX(ArmEnableVFP): | |
63adfb11 | 319 | # Enable VFP registers |
1bfda055 | 320 | mrc p15, 0, r0, c1, c0, 2 |
63adfb11 | 321 | orr r0, r0, #0x00f00000 @ Enable VPF access (V* instructions) |
1bfda055 | 322 | mcr p15, 0, r0, c1, c0, 2 |
63adfb11 | 323 | mov r0, #0x40000000 @ Set EN bit in FPEXC |
324 | mcr p10,#0x7,r0,c8,c0,#0 @ msr FPEXC,r0 in ARM assembly | |
1bfda055 | 325 | bx lr |
326 | ||
327 | ASM_PFX(ArmCallWFI): | |
328 | wfi | |
329 | bx lr | |
330 | ||
63adfb11 | 331 | #Note: Return 0 in Uniprocessor implementation |
1bfda055 | 332 | ASM_PFX(ArmReadCbar): |
63adfb11 | 333 | mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register |
1bfda055 | 334 | bx lr |
335 | ||
336 | ASM_PFX(ArmInvalidateInstructionAndDataTlb): | |
337 | mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB | |
338 | dsb | |
339 | bx lr | |
340 | ||
341 | ASM_PFX(ArmReadMpidr): | |
2ac288f9 | 342 | mrc p15, 0, r0, c0, c0, 5 @ read MPIDR |
1bfda055 | 343 | bx lr |
98bc0c8c | 344 | |
2ef2b01e | 345 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED |