ArmPkg: Introduce ArmSetLowVectors/ArmSetHighVectors functions

These functions set/clear the SCTLR.V bit that controls the location
of the Vector Table.
This commit also forces the SCTLR.V to be clear when the VBAR register
is set.

Note: The original fix has been proposed by Eugene Cohen (HP).

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11739 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Drivers/CpuDxe/Exception.c b/ArmPkg/Drivers/CpuDxe/Exception.c
index 17e463f97b7c3acf9d42853976500c159970755c..659b7137e16b5f46ecfacdbab41638be201a70f2 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/Exception.c
+++ b/ArmPkg/Drivers/CpuDxe/Exception.c
@@ -149,6 +149,14 @@ InitializeExceptions (
     //\r
     Length = (UINTN)ExceptionHandlersEnd - (UINTN)ExceptionHandlersStart;\r
 \r
+    // Check if the exception vector is in the low address\r
+    if (PcdGet32 (PcdCpuVectorBaseAddress) == 0x0) {\r
+      // Set SCTLR.V to 0 to enable VBAR to be used\r
+      ArmSetLowVectors ();\r
+    } else {\r
+      ArmSetHighVectors ();\r
+    }\r
+\r
     //\r
     // Reserve space for the exception handlers\r
     //\r

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 03ba548de257411fd58a299c978be649c28843b2..468e663989234fb42a6e0750c60846492a1cbcd0 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -346,7 +346,19 @@ EFIAPI
 ArmDisableBranchPrediction (
   VOID
   );
-  
+
+VOID
+EFIAPI
+ArmSetLowVectors (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmSetHighVectors (
+  VOID
+  );
+
 VOID
 EFIAPI
 ArmDataMemoryBarrier (

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
index 5b12d1dee253cdb78e0984498c24a4aae6727f90..b11c19dc59c863f9be10c6e5ff4acfb3df2ca8d5 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
@@ -34,6 +34,8 @@ GCC_ASM_EXPORT (ArmDisableInstructionCache)
 GCC_ASM_EXPORT (ArmEnableSWPInstruction)
 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
+GCC_ASM_EXPORT (ArmSetLowVectors)
+GCC_ASM_EXPORT (ArmSetHighVectors)
 GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
 GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
@@ -199,6 +201,19 @@ ASM_PFX(ArmDisableBranchPrediction):
   isb
   bx      LR
 
+ASM_PFX(ArmSetLowVectors):
+  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
+  bic     r0, r0, #0x00002000   @ clear V bit
+  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
+  isb
+  bx      LR
+
+ASM_PFX(ArmSetHighVectors):
+  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
+  orr     r0, r0, #0x00002000   @ clear V bit
+  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
+  isb
+  bx      LR
 
 ASM_PFX(ArmV7AllDataCachesOperation):
   stmfd SP!,{r4-r12, LR}
@@ -287,7 +302,13 @@ ASM_PFX(ArmWriteVMBar):
   bx      lr
 
 ASM_PFX(ArmWriteVBar):
+  # Set the Address of the Vector Table in the VBAR register
   mcr     p15, 0, r0, c12, c0, 0 
+  # Ensure the SCTLR.V bit is clear
+  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
+  bic     r0, r0, #0x00002000   @ clear V bit
+  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
+  isb
   bx      lr
 
 ASM_PFX(ArmWriteCPACR):

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
index 4c78c54674e1655053f9472ded168f68a6b09aea..75399cb0fc2fa683b9cf2ec2336abbb4e8c3a131 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
@@ -31,6 +31,8 @@
     EXPORT  ArmEnableSWPInstruction
     EXPORT  ArmEnableBranchPrediction
     EXPORT  ArmDisableBranchPrediction
+    EXPORT  ArmSetLowVectors
+    EXPORT  ArmSetHighVectors
     EXPORT  ArmV7AllDataCachesOperation
     EXPORT  ArmDataMemoryBarrier
     EXPORT  ArmDataSyncronizationBarrier
@@ -196,6 +198,19 @@ ArmDisableBranchPrediction
   isb
   bx      LR
 
+ArmSetLowVectors
+  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
+  bic     r0, r0, #0x00002000   ; clear V bit
+  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
+  isb
+  bx      LR
+
+ArmSetHighVectors
+  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
+  orr     r0, r0, #0x00002000   ; clear V bit
+  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
+  isb
+  bx      LR
 
 ArmV7AllDataCachesOperation
   stmfd SP!,{r4-r12, LR}
@@ -281,7 +296,13 @@ ArmWriteVMBar
   bx      lr
 
 ArmWriteVBar
+  // Set the Address of the Vector Table in the VBAR register
   mcr     p15, 0, r0, c12, c0, 0 
+  // Ensure the SCTLR.V bit is clear
+  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
+  bic     r0, r0, #0x00002000   ; clear V bit
+  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
+  isb
   bx      lr
 
 ArmReadVBar