1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
5 // This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
15 EXPORT ArmInvalidateInstructionCache
16 EXPORT ArmInvalidateDataCacheEntryByMVA
17 EXPORT ArmCleanDataCacheEntryByMVA
18 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
19 EXPORT ArmInvalidateDataCacheEntryBySetWay
20 EXPORT ArmCleanDataCacheEntryBySetWay
21 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
22 EXPORT ArmDrainWriteBuffer
25 EXPORT ArmDisableCachesAndMmu
27 EXPORT ArmEnableDataCache
28 EXPORT ArmDisableDataCache
29 EXPORT ArmEnableInstructionCache
30 EXPORT ArmDisableInstructionCache
31 EXPORT ArmEnableSWPInstruction
32 EXPORT ArmEnableBranchPrediction
33 EXPORT ArmDisableBranchPrediction
34 EXPORT ArmSetLowVectors
35 EXPORT ArmSetHighVectors
36 EXPORT ArmV7AllDataCachesOperation
37 EXPORT ArmDataMemoryBarrier
38 EXPORT ArmDataSyncronizationBarrier
39 EXPORT ArmInstructionSynchronizationBarrier
51 EXPORT ArmInvalidateInstructionAndDataTlb
54 AREA ArmCacheLib, CODE, READONLY
57 DC_ON EQU ( 0x1:SHL:2 )
58 IC_ON EQU ( 0x1:SHL:12 )
59 CTRL_M_BIT EQU (1 << 0)
60 CTRL_C_BIT EQU (1 << 2)
61 CTRL_B_BIT EQU (1 << 7)
62 CTRL_I_BIT EQU (1 << 12)
65 ArmInvalidateDataCacheEntryByMVA
66 mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
72 ArmCleanDataCacheEntryByMVA
73 mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
79 ArmCleanInvalidateDataCacheEntryByMVA
80 mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
86 ArmInvalidateDataCacheEntryBySetWay
87 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
93 ArmCleanInvalidateDataCacheEntryBySetWay
94 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
100 ArmCleanDataCacheEntryBySetWay
101 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
107 ArmInvalidateInstructionCache
108 mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
113 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
114 orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
115 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
121 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
126 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
127 bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
128 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
130 mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
131 mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
136 ArmDisableCachesAndMmu
137 mrc p15, 0, r0, c1, c0, 0 ; Get control register
138 bic r0, r0, #CTRL_M_BIT ; Disable MMU
139 bic r0, r0, #CTRL_C_BIT ; Disable D Cache
140 bic r0, r0, #CTRL_I_BIT ; Disable I Cache
141 mcr p15, 0, r0, c1, c0, 0 ; Write control register
147 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
148 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
149 orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
150 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
156 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
157 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
158 bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
159 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
163 ArmEnableInstructionCache
164 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
165 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
166 orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
167 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
172 ArmDisableInstructionCache
173 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
174 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
175 BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
176 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
180 ArmEnableSWPInstruction
181 mrc p15, 0, r0, c1, c0, 0
182 orr r0, r0, #0x00000400
183 mcr p15, 0, r0, c1, c0, 0
187 ArmEnableBranchPrediction
188 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
189 orr r0, r0, #0x00000800 ;
190 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
194 ArmDisableBranchPrediction
195 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
196 bic r0, r0, #0x00000800 ;
197 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
202 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
203 bic r0, r0, #0x00002000 ; clear V bit
204 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
209 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
210 orr r0, r0, #0x00002000 ; clear V bit
211 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
215 ArmV7AllDataCachesOperation
216 stmfd SP!,{r4-r12, LR}
217 mov R1, R0 ; Save Function call in R1
218 mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
219 ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
220 mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
225 add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
226 mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
227 and R12, R12, #7 ; get those 3 bits alone
229 blt Skip ; no cache or only instruction cache at this level
230 mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
231 isb ; isb to sync the change to the CacheSizeID reg
232 mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
233 and R2, R12, #&7 ; extract the line length field
234 add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
236 ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
237 clz R5, R4 ; R5 is the bit position of the way size increment
239 ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
242 mov R9, R4 ; R9 working copy of the max way size (right aligned)
245 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
246 orr R0, R0, R7, LSL R2 ; factor in the index number
250 subs R9, R9, #1 ; decrement the way number
252 subs R7, R7, #1 ; decrement the index
255 add R10, R10, #2 ; increment the cache number
261 ldmfd SP!, {r4-r12, lr}
269 ArmDataSyncronizationBarrier
274 ArmInstructionSynchronizationBarrier
279 mcr p15, 0, r0, c1, c1, 2
283 mcr p15, 0, r0, c1, c1, 0
287 mcr p15, 0, r0, c1, c0, 1
291 mrc p15, 0, r0, c1, c0, 1
295 mcr p15, 0, r0, c12, c0, 1
299 // Set the Address of the Vector Table in the VBAR register
300 mcr p15, 0, r0, c12, c0, 0
301 // Ensure the SCTLR.V bit is clear
302 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
303 bic r0, r0, #0x00002000 ; clear V bit
304 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
309 mrc p15, 0, r0, c12, c0, 0
313 mcr p15, 0, r0, c1, c0, 2
317 // Enable VFP registers
318 mrc p15, 0, r0, c1, c0, 2
319 orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
320 mcr p15, 0, r0, c1, c0, 2
321 mov r0, #0x40000000 // Set EN bit in FPEXC
322 mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly
329 //Note: Return 0 in Uniprocessor implementation
331 mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
334 ArmInvalidateInstructionAndDataTlb
335 mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB
340 mrc p15, 0, r0, c0, c0, 5 ; read MPIDR