[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.asm

//------------------------------------------------------------------------------ 
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution.  The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------

    EXPORT  ArmInvalidateInstructionCache
    EXPORT  ArmInvalidateDataCacheEntryByMVA
    EXPORT  ArmCleanDataCacheEntryByMVA
    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
    EXPORT  ArmInvalidateDataCacheEntryBySetWay
    EXPORT  ArmCleanDataCacheEntryBySetWay
    EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
    EXPORT  ArmDrainWriteBuffer
    EXPORT  ArmEnableMmu
    EXPORT  ArmDisableMmu
    EXPORT  ArmDisableCachesAndMmu
    EXPORT  ArmMmuEnabled
    EXPORT  ArmEnableDataCache
    EXPORT  ArmDisableDataCache
    EXPORT  ArmEnableInstructionCache
    EXPORT  ArmDisableInstructionCache
    EXPORT  ArmEnableSWPInstruction
    EXPORT  ArmEnableBranchPrediction
    EXPORT  ArmDisableBranchPrediction
    EXPORT  ArmSetLowVectors
    EXPORT  ArmSetHighVectors
    EXPORT  ArmV7AllDataCachesOperation
    EXPORT  ArmDataMemoryBarrier
    EXPORT  ArmDataSyncronizationBarrier
    EXPORT  ArmInstructionSynchronizationBarrier
    EXPORT  ArmWriteNsacr
    EXPORT  ArmWriteScr
    EXPORT  ArmWriteVMBar
    EXPORT  ArmWriteVBar
    EXPORT  ArmReadVBar
    EXPORT  ArmWriteCPACR
    EXPORT  ArmEnableVFP
    EXPORT  ArmCallWFI
    EXPORT  ArmWriteAuxCr
    EXPORT  ArmReadAuxCr
    EXPORT  ArmReadCbar
    EXPORT  ArmInvalidateInstructionAndDataTlb
    EXPORT  ArmReadMpidr

    AREA    ArmCacheLib, CODE, READONLY
    PRESERVE8

DC_ON           EQU     ( 0x1:SHL:2 )
IC_ON           EQU     ( 0x1:SHL:12 )
CTRL_M_BIT      EQU     (1 << 0)
CTRL_C_BIT      EQU     (1 << 2)
CTRL_B_BIT      EQU     (1 << 7)
CTRL_I_BIT      EQU     (1 << 12)


ArmInvalidateDataCacheEntryByMVA
  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line       
  dsb
  isb
  bx      lr


ArmCleanDataCacheEntryByMVA
  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
  dsb
  isb
  bx      lr


ArmCleanInvalidateDataCacheEntryByMVA
  mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  dsb
  isb
  bx      lr


ArmInvalidateDataCacheEntryBySetWay
  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line    
  dsb
  isb
  bx      lr


ArmCleanInvalidateDataCacheEntryBySetWay
  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line    
  dsb
  isb
  bx      lr


ArmCleanDataCacheEntryBySetWay
  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line    
  dsb
  isb
  bx      lr


ArmInvalidateInstructionCache
  mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
  isb
  bx      LR

ArmEnableMmu
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
  orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
  dsb
  isb
  bx      LR

ArmMmuEnabled
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
  and     R0,R0,#1
  bx      LR

ArmDisableMmu
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
  bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)

  mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB
  mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array
  dsb
  isb
  bx      LR

ArmDisableCachesAndMmu
  mrc   p15, 0, r0, c1, c0, 0           ; Get control register
  bic   r0, r0, #CTRL_M_BIT             ; Disable MMU
  bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache
  bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache
  mcr   p15, 0, r0, c1, c0, 0           ; Write control register
  dsb
  isb
  bx      LR

ArmEnableDataCache
  ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
  orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
  dsb
  isb
  bx      LR
    
ArmDisableDataCache
  ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
  bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
  isb
  bx      LR

ArmEnableInstructionCache
  ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
  orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
  dsb
  isb
  bx      LR
  
ArmDisableInstructionCache
  ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
  BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
  isb
  bx      LR

ArmEnableSWPInstruction
  mrc     p15, 0, r0, c1, c0, 0
  orr     r0, r0, #0x00000400
  mcr     p15, 0, r0, c1, c0, 0
  isb
  bx      LR

ArmEnableBranchPrediction
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
  orr     r0, r0, #0x00000800   ;
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
  isb
  bx      LR

ArmDisableBranchPrediction
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
  bic     r0, r0, #0x00000800   ;
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
  isb
  bx      LR

ArmSetLowVectors
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
  bic     r0, r0, #0x00002000   ; clear V bit
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
  isb
  bx      LR

ArmSetHighVectors
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
  orr     r0, r0, #0x00002000   ; clear V bit
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
  isb
  bx      LR

ArmV7AllDataCachesOperation
  stmfd SP!,{r4-r12, LR}
  mov   R1, R0                ; Save Function call in R1
  mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
  ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
  mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)
  beq   Finished
  mov   R10, #0

Loop1   
  add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
  mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
  and   R12, R12, #7            ; get those 3 bits alone
  cmp   R12, #2
  blt   Skip                    ; no cache or only instruction cache at this level
  mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
  isb                           ; isb to sync the change to the CacheSizeID reg 
  mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
  and   R2, R12, #&7            ; extract the line length field
  add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
  ldr   R4, =0x3FF
  ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
  clz   R5, R4                  ; R5 is the bit position of the way size increment
  ldr   R7, =0x00007FFF
  ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)

Loop2   
  mov   R9, R4                  ; R9 working copy of the max way size (right aligned)

Loop3   
  orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
  orr   R0, R0, R7, LSL R2      ; factor in the index number

  blx   R1

  subs  R9, R9, #1              ; decrement the way number
  bge   Loop3
  subs  R7, R7, #1              ; decrement the index
  bge   Loop2
Skip  
  add   R10, R10, #2            ; increment the cache number
  cmp   R3, R10
  bgt   Loop1
  
Finished
  dsb
  ldmfd SP!, {r4-r12, lr}
  bx    LR


ArmDataMemoryBarrier
  dmb
  bx      LR
  
ArmDataSyncronizationBarrier
ArmDrainWriteBuffer
  dsb
  bx      LR
  
ArmInstructionSynchronizationBarrier
  isb
  bx      LR

ArmWriteNsacr
  mcr     p15, 0, r0, c1, c1, 2
  bx      lr

ArmWriteScr
  mcr     p15, 0, r0, c1, c1, 0
  bx      lr

ArmWriteAuxCr
  mcr     p15, 0, r0, c1, c0, 1
  bx      lr

ArmReadAuxCr
  mrc     p15, 0, r0, c1, c0, 1
  bx      lr  

ArmWriteVMBar
  mcr     p15, 0, r0, c12, c0, 1
  bx      lr

ArmWriteVBar
  // Set the Address of the Vector Table in the VBAR register
  mcr     p15, 0, r0, c12, c0, 0 
  // Ensure the SCTLR.V bit is clear
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
  bic     r0, r0, #0x00002000   ; clear V bit
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
  isb
  bx      lr

ArmReadVBar
  mrc     p15, 0, r0, c12, c0, 0 
  bx      lr

ArmWriteCPACR
  mcr     p15, 0, r0, c1, c0, 2
  bx      lr

ArmEnableVFP
  // Enable VFP registers
  mrc     p15, 0, r0, c1, c0, 2
  orr     r0, r0, #0x00f00000   // Enable VPF access (V* instructions)
  mcr     p15, 0, r0, c1, c0, 2
  mov     r0, #0x40000000       // Set EN bit in FPEXC
  mcr     p10,#0x7,r0,c8,c0,#0  // msr     FPEXC,r0 in ARM assembly
  bx      lr

ArmCallWFI
  wfi
  bx      lr

//Note: Return 0 in Uniprocessor implementation
ArmReadCbar
  mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register
  bx      lr

ArmInvalidateInstructionAndDataTlb
  mcr     p15, 0, r0, c8, c7, 0      ; Invalidate Inst TLB and Data TLB
  dsb
  bx lr

ArmReadMpidr
  mrc     p15, 0, r0, c0, c0, 5    ; read MPIDR
  bx      lr

  END
Commit	Line	Data
2ef2b01e A	1	//------------------------------------------------------------------------------
2ef2b01e A	2	//
d6ebcab7	3	// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
2ef2b01e	4	//
d6ebcab7	5	// This program and the accompanying materials
2ef2b01e A	6	// are licensed and made available under the terms and conditions of the BSD License
	7	// which accompanies this distribution. The full text of the license may be found at
	8	// http://opensource.org/licenses/bsd-license.php
	9	//
	10	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
	11	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
	12	//
	13	//------------------------------------------------------------------------------
	14
	15	EXPORT ArmInvalidateInstructionCache
	16	EXPORT ArmInvalidateDataCacheEntryByMVA
	17	EXPORT ArmCleanDataCacheEntryByMVA
	18	EXPORT ArmCleanInvalidateDataCacheEntryByMVA
	19	EXPORT ArmInvalidateDataCacheEntryBySetWay
	20	EXPORT ArmCleanDataCacheEntryBySetWay
	21	EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
	22	EXPORT ArmDrainWriteBuffer
	23	EXPORT ArmEnableMmu
	24	EXPORT ArmDisableMmu
1bfda055	25	EXPORT ArmDisableCachesAndMmu
c2b5ca8b	26	EXPORT ArmMmuEnabled
2ef2b01e A	27	EXPORT ArmEnableDataCache
	28	EXPORT ArmDisableDataCache
	29	EXPORT ArmEnableInstructionCache
	30	EXPORT ArmDisableInstructionCache
1bfda055	31	EXPORT ArmEnableSWPInstruction
2ef2b01e A	32	EXPORT ArmEnableBranchPrediction
2ef2b01e A	33	EXPORT ArmDisableBranchPrediction
f0fef790	34	EXPORT ArmSetLowVectors
f0fef790	35	EXPORT ArmSetHighVectors
37b91c49	36	EXPORT ArmV7AllDataCachesOperation
026c3d34	37	EXPORT ArmDataMemoryBarrier
	38	EXPORT ArmDataSyncronizationBarrier
	39	EXPORT ArmInstructionSynchronizationBarrier
1bfda055	40	EXPORT ArmWriteNsacr
	41	EXPORT ArmWriteScr
	42	EXPORT ArmWriteVMBar
	43	EXPORT ArmWriteVBar
	44	EXPORT ArmReadVBar
	45	EXPORT ArmWriteCPACR
	46	EXPORT ArmEnableVFP
	47	EXPORT ArmCallWFI
	48	EXPORT ArmWriteAuxCr
	49	EXPORT ArmReadAuxCr
	50	EXPORT ArmReadCbar
	51	EXPORT ArmInvalidateInstructionAndDataTlb
	52	EXPORT ArmReadMpidr
026c3d34	53
548af3e7	54	AREA ArmCacheLib, CODE, READONLY
548af3e7	55	PRESERVE8
2ef2b01e	56
1bfda055	57	DC_ON EQU ( 0x1:SHL:2 )
	58	IC_ON EQU ( 0x1:SHL:12 )
	59	CTRL_M_BIT EQU (1 << 0)
	60	CTRL_C_BIT EQU (1 << 2)
	61	CTRL_B_BIT EQU (1 << 7)
	62	CTRL_I_BIT EQU (1 << 12)
2ef2b01e	63
2ef2b01e A	64
2ef2b01e A	65	ArmInvalidateDataCacheEntryByMVA
548af3e7	66	mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
	67	dsb
	68	isb
	69	bx lr
2ef2b01e A	70
	71
	72	ArmCleanDataCacheEntryByMVA
548af3e7	73	mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
	74	dsb
	75	isb
	76	bx lr
2ef2b01e A	77
	78
	79	ArmCleanInvalidateDataCacheEntryByMVA
548af3e7	80	mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
	81	dsb
	82	isb
	83	bx lr
2ef2b01e A	84
	85
	86	ArmInvalidateDataCacheEntryBySetWay
2ac288f9	87	mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
548af3e7	88	dsb
548af3e7	89	isb
2ef2b01e A	90	bx lr
	91
	92
	93	ArmCleanInvalidateDataCacheEntryBySetWay
2ac288f9	94	mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
548af3e7	95	dsb
548af3e7	96	isb
2ef2b01e A	97	bx lr
	98
	99
	100	ArmCleanDataCacheEntryBySetWay
2ac288f9	101	mcr p15, 0, r0, c7, c10, 2 ; Clean this line
548af3e7	102	dsb
548af3e7	103	isb
2ef2b01e A	104	bx lr
	105
	106
2ef2b01e	107	ArmInvalidateInstructionCache
548af3e7	108	mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
548af3e7	109	isb
548af3e7	110	bx LR
2ef2b01e A	111
2ef2b01e A	112	ArmEnableMmu
1bfda055	113	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
	114	orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
	115	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
548af3e7	116	dsb
548af3e7	117	isb
2ef2b01e A	118	bx LR
2ef2b01e A	119
c2b5ca8b	120	ArmMmuEnabled
1bfda055	121	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
c2b5ca8b A	122	and R0,R0,#1
	123	bx LR
	124
2ef2b01e	125	ArmDisableMmu
1bfda055	126	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
	127	bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
	128	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
7800c283	129
2ac288f9	130	mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
1bfda055	131	mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
548af3e7	132	dsb
548af3e7	133	isb
2ef2b01e A	134	bx LR
2ef2b01e A	135
1bfda055	136	ArmDisableCachesAndMmu
	137	mrc p15, 0, r0, c1, c0, 0 ; Get control register
	138	bic r0, r0, #CTRL_M_BIT ; Disable MMU
	139	bic r0, r0, #CTRL_C_BIT ; Disable D Cache
	140	bic r0, r0, #CTRL_I_BIT ; Disable I Cache
	141	mcr p15, 0, r0, c1, c0, 0 ; Write control register
	142	dsb
	143	isb
	144	bx LR
bb02cb80	145
2ef2b01e	146	ArmEnableDataCache
1bfda055	147	ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
	148	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
	149	orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
	150	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
548af3e7	151	dsb
	152	isb
	153	bx LR
2ef2b01e A	154
2ef2b01e A	155	ArmDisableDataCache
1bfda055	156	ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
	157	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
	158	bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
	159	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
548af3e7	160	isb
548af3e7	161	bx LR
2ef2b01e A	162
2ef2b01e A	163	ArmEnableInstructionCache
1bfda055	164	ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
	165	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
	166	orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
	167	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
548af3e7	168	dsb
	169	isb
	170	bx LR
2ef2b01e A	171
2ef2b01e A	172	ArmDisableInstructionCache
1bfda055	173	ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
	174	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
	175	BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
	176	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
548af3e7	177	isb
548af3e7	178	bx LR
2ef2b01e	179
1bfda055	180	ArmEnableSWPInstruction
2ef2b01e	181	mrc p15, 0, r0, c1, c0, 0
1bfda055	182	orr r0, r0, #0x00000400
2ef2b01e	183	mcr p15, 0, r0, c1, c0, 0
548af3e7	184	isb
2ef2b01e A	185	bx LR
2ef2b01e A	186
1bfda055	187	ArmEnableBranchPrediction
	188	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
	189	orr r0, r0, #0x00000800 ;
	190	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
	191	isb
	192	bx LR
	193
2ef2b01e	194	ArmDisableBranchPrediction
1bfda055	195	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
	196	bic r0, r0, #0x00000800 ;
	197	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
548af3e7	198	isb
2ef2b01e A	199	bx LR
2ef2b01e A	200
f0fef790	201	ArmSetLowVectors
	202	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
	203	bic r0, r0, #0x00002000 ; clear V bit
	204	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
	205	isb
	206	bx LR
	207
	208	ArmSetHighVectors
	209	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
	210	orr r0, r0, #0x00002000 ; clear V bit
	211	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
	212	isb
	213	bx LR
98bc0c8c	214
98bc0c8c	215	ArmV7AllDataCachesOperation
548af3e7	216	stmfd SP!,{r4-r12, LR}
	217	mov R1, R0 ; Save Function call in R1
	218	mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
	219	ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
	220	mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
	221	beq Finished
	222	mov R10, #0
98bc0c8c	223
98bc0c8c	224	Loop1
1bfda055	225	add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
	226	mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
	227	and R12, R12, #7 ; get those 3 bits alone
548af3e7	228	cmp R12, #2
	229	blt Skip ; no cache or only instruction cache at this level
	230	mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
	231	isb ; isb to sync the change to the CacheSizeID reg
	232	mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
	233	and R2, R12, #&7 ; extract the line length field
	234	add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
	235	ldr R4, =0x3FF
	236	ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
	237	clz R5, R4 ; R5 is the bit position of the way size increment
	238	ldr R7, =0x00007FFF
	239	ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
98bc0c8c	240
98bc0c8c	241	Loop2
548af3e7	242	mov R9, R4 ; R9 working copy of the max way size (right aligned)
98bc0c8c	243
98bc0c8c	244	Loop3
548af3e7	245	orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
548af3e7	246	orr R0, R0, R7, LSL R2 ; factor in the index number
98bc0c8c	247
548af3e7	248	blx R1
98bc0c8c	249
548af3e7	250	subs R9, R9, #1 ; decrement the way number
	251	bge Loop3
	252	subs R7, R7, #1 ; decrement the index
	253	bge Loop2
98bc0c8c	254	Skip
548af3e7	255	add R10, R10, #2 ; increment the cache number
	256	cmp R3, R10
	257	bgt Loop1
98bc0c8c	258
98bc0c8c	259	Finished
7800c283	260	dsb
548af3e7	261	ldmfd SP!, {r4-r12, lr}
548af3e7	262	bx LR
98bc0c8c	263
026c3d34	264
026c3d34	265	ArmDataMemoryBarrier
548af3e7	266	dmb
548af3e7	267	bx LR
026c3d34	268
026c3d34	269	ArmDataSyncronizationBarrier
7800c283	270	ArmDrainWriteBuffer
548af3e7	271	dsb
548af3e7	272	bx LR
026c3d34	273
026c3d34	274	ArmInstructionSynchronizationBarrier
548af3e7	275	isb
548af3e7	276	bx LR
026c3d34	277
1bfda055	278	ArmWriteNsacr
	279	mcr p15, 0, r0, c1, c1, 2
	280	bx lr
	281
	282	ArmWriteScr
	283	mcr p15, 0, r0, c1, c1, 0
	284	bx lr
	285
	286	ArmWriteAuxCr
	287	mcr p15, 0, r0, c1, c0, 1
	288	bx lr
	289
	290	ArmReadAuxCr
	291	mrc p15, 0, r0, c1, c0, 1
	292	bx lr
	293
	294	ArmWriteVMBar
	295	mcr p15, 0, r0, c12, c0, 1
	296	bx lr
	297
	298	ArmWriteVBar
f0fef790	299	// Set the Address of the Vector Table in the VBAR register
1bfda055	300	mcr p15, 0, r0, c12, c0, 0
f0fef790	301	// Ensure the SCTLR.V bit is clear
	302	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
	303	bic r0, r0, #0x00002000 ; clear V bit
	304	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
	305	isb
1bfda055	306	bx lr
	307
	308	ArmReadVBar
	309	mrc p15, 0, r0, c12, c0, 0
	310	bx lr
	311
	312	ArmWriteCPACR
	313	mcr p15, 0, r0, c1, c0, 2
	314	bx lr
	315
	316	ArmEnableVFP
	317	// Enable VFP registers
	318	mrc p15, 0, r0, c1, c0, 2
	319	orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
	320	mcr p15, 0, r0, c1, c0, 2
	321	mov r0, #0x40000000 // Set EN bit in FPEXC
	322	mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly
	323	bx lr
	324
	325	ArmCallWFI
	326	wfi
	327	bx lr
	328
	329	//Note: Return 0 in Uniprocessor implementation
	330	ArmReadCbar
2ac288f9	331	mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
1bfda055	332	bx lr
	333
	334	ArmInvalidateInstructionAndDataTlb
	335	mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB
	336	dsb
	337	bx lr
	338
	339	ArmReadMpidr
2ac288f9	340	mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
1bfda055	341	bx lr
	342
	343	END
e9fc14b6	344