Update gcc flags to armv7
[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.asm
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1//------------------------------------------------------------------------------
2//
3// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
4//
5// All rights reserved. This program and the accompanying materials
6// are licensed and made available under the terms and conditions of the BSD License
7// which accompanies this distribution. The full text of the license may be found at
8// http://opensource.org/licenses/bsd-license.php
9//
10// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12//
13//------------------------------------------------------------------------------
14
15 EXPORT ArmInvalidateInstructionCache
16 EXPORT ArmInvalidateDataCacheEntryByMVA
17 EXPORT ArmCleanDataCacheEntryByMVA
18 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
19 EXPORT ArmInvalidateDataCacheEntryBySetWay
20 EXPORT ArmCleanDataCacheEntryBySetWay
21 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
22 EXPORT ArmDrainWriteBuffer
23 EXPORT ArmEnableMmu
24 EXPORT ArmDisableMmu
c2b5ca8b 25 EXPORT ArmMmuEnabled
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26 EXPORT ArmEnableDataCache
27 EXPORT ArmDisableDataCache
28 EXPORT ArmEnableInstructionCache
29 EXPORT ArmDisableInstructionCache
30 EXPORT ArmEnableBranchPrediction
31 EXPORT ArmDisableBranchPrediction
32
33DC_ON EQU ( 0x1:SHL:2 )
34IC_ON EQU ( 0x1:SHL:12 )
35XP_ON EQU ( 0x1:SHL:23 )
36
37
38 AREA ArmCacheLib, CODE, READONLY
39 PRESERVE8
40
41
42ArmInvalidateDataCacheEntryByMVA
1a27eb48 43 DSB
44 ISB
2ef2b01e 45 MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
1a27eb48 46 DSB
47 ISB
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48 BX lr
49
50
51ArmCleanDataCacheEntryByMVA
1a27eb48 52 DSB
53 ISB
2ef2b01e 54 MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
1a27eb48 55 DSB
56 ISB
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57 BX lr
58
59
60ArmCleanInvalidateDataCacheEntryByMVA
1a27eb48 61 DSB
62 ISB
2ef2b01e 63 MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
1a27eb48 64 DSB
65 ISB
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66 BX lr
67
68
69ArmInvalidateDataCacheEntryBySetWay
1a27eb48 70 DSB
71 ISB
2ef2b01e 72 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
1a27eb48 73 DSB
74 ISB
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75 bx lr
76
77
78ArmCleanInvalidateDataCacheEntryBySetWay
1a27eb48 79 DSB
80 ISB
2ef2b01e 81 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
1a27eb48 82 DSB
83 ISB
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84 bx lr
85
86
87ArmCleanDataCacheEntryBySetWay
1a27eb48 88 DSB
89 ISB
2ef2b01e 90 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
1a27eb48 91 DSB
92 ISB
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93 bx lr
94
95
96ArmDrainWriteBuffer
1a27eb48 97 DSB
98 ISB
2ef2b01e 99 mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
1a27eb48 100 DSB
101 ISB
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102 bx lr
103
104
105ArmInvalidateInstructionCache
1a27eb48 106 DSB
107 ISB
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108 MOV R0,#0
109 MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
110 MOV R0,#0
111 MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
1a27eb48 112 DSB
113 ISB
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114 BX LR
115
116ArmEnableMmu
1a27eb48 117 DSB
118 ISB
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119 mrc p15,0,R0,c1,c0,0
120 orr R0,R0,#1
121 mcr p15,0,R0,c1,c0,0
1a27eb48 122 DSB
123 ISB
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124 bx LR
125
c2b5ca8b 126ArmMmuEnabled
1a27eb48 127 DSB
128 ISB
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129 mrc p15,0,R0,c1,c0,0
130 and R0,R0,#1
1a27eb48 131 DSB
132 ISB
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133 bx LR
134
2ef2b01e 135ArmDisableMmu
1a27eb48 136 DSB
137 ISB
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138 mov R0,#0
139 mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
140 mrc p15,0,R0,c1,c0,0
141 bic R0,R0,#1
142 mcr p15,0,R0,c1,c0,0 ;Disable MMU
143 mov R0,#0
144 mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
145 mov R0,#0
146 mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
1a27eb48 147 DSB
148 ISB
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149 bx LR
150
151ArmEnableDataCache
1a27eb48 152 DSB
153 ISB
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154 LDR R1,=DC_ON
155 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
156 ORR R0,R0,R1 ;Set C bit
157 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
1a27eb48 158 DSB
159 ISB
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160 BX LR
161
162ArmDisableDataCache
1a27eb48 163 DSB
164 ISB
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165 LDR R1,=DC_ON
166 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
167 BIC R0,R0,R1 ;Clear C bit
168 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
1a27eb48 169 DSB
170 ISB
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171 BX LR
172
173ArmEnableInstructionCache
1a27eb48 174 DSB
175 ISB
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176 LDR R1,=IC_ON
177 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
178 ORR R0,R0,R1 ;Set I bit
179 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
1a27eb48 180 DSB
181 ISB
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182 BX LR
183
184ArmDisableInstructionCache
1a27eb48 185 DSB
186 ISB
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187 LDR R1,=IC_ON
188 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
189 BIC R0,R0,R1 ;Clear I bit.
190 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
1a27eb48 191 DSB
192 ISB
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193 BX LR
194
195ArmEnableBranchPrediction
1a27eb48 196 DSB
197 ISB
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198 mrc p15, 0, r0, c1, c0, 0
199 orr r0, r0, #0x00000800
200 mcr p15, 0, r0, c1, c0, 0
1a27eb48 201 DSB
202 ISB
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203 bx LR
204
205ArmDisableBranchPrediction
1a27eb48 206 DSB
207 ISB
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208 mrc p15, 0, r0, c1, c0, 0
209 bic r0, r0, #0x00000800
210 mcr p15, 0, r0, c1, c0, 0
1a27eb48 211 DSB
212 ISB
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213 bx LR
214
215 END