Adding support for BeagleBoard.
[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmCortexA / ArmCortexASupport.asm
CommitLineData
2ef2b01e
A
1//------------------------------------------------------------------------------
2//
3// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
4//
5// All rights reserved. This program and the accompanying materials
6// are licensed and made available under the terms and conditions of the BSD License
7// which accompanies this distribution. The full text of the license may be found at
8// http://opensource.org/licenses/bsd-license.php
9//
10// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12//
13//------------------------------------------------------------------------------
14
15 EXPORT ArmInvalidateInstructionCache
16 EXPORT ArmInvalidateDataCacheEntryByMVA
17 EXPORT ArmCleanDataCacheEntryByMVA
18 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
19 EXPORT ArmInvalidateDataCacheEntryBySetWay
20 EXPORT ArmCleanDataCacheEntryBySetWay
21 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
22 EXPORT ArmDrainWriteBuffer
23 EXPORT ArmEnableMmu
24 EXPORT ArmDisableMmu
25 EXPORT ArmEnableDataCache
26 EXPORT ArmDisableDataCache
27 EXPORT ArmEnableInstructionCache
28 EXPORT ArmDisableInstructionCache
29 EXPORT ArmEnableBranchPrediction
30 EXPORT ArmDisableBranchPrediction
31
32DC_ON EQU ( 0x1:SHL:2 )
33IC_ON EQU ( 0x1:SHL:12 )
34XP_ON EQU ( 0x1:SHL:23 )
35
36
37 AREA ArmCacheLib, CODE, READONLY
38 PRESERVE8
39
40
41ArmInvalidateDataCacheEntryByMVA
42 MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
43 BX lr
44
45
46ArmCleanDataCacheEntryByMVA
47 MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
48 BX lr
49
50
51ArmCleanInvalidateDataCacheEntryByMVA
52 MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
53 BX lr
54
55
56ArmInvalidateDataCacheEntryBySetWay
57 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
58 bx lr
59
60
61ArmCleanInvalidateDataCacheEntryBySetWay
62 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
63 bx lr
64
65
66ArmCleanDataCacheEntryBySetWay
67 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
68 bx lr
69
70
71ArmDrainWriteBuffer
72 mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
73 bx lr
74
75
76ArmInvalidateInstructionCache
77 MOV R0,#0
78 MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
79 MOV R0,#0
80 MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
81 BX LR
82
83ArmEnableMmu
84 mrc p15,0,R0,c1,c0,0
85 orr R0,R0,#1
86 mcr p15,0,R0,c1,c0,0
87 bx LR
88
89ArmDisableMmu
90 mov R0,#0
91 mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
92 mrc p15,0,R0,c1,c0,0
93 bic R0,R0,#1
94 mcr p15,0,R0,c1,c0,0 ;Disable MMU
95 mov R0,#0
96 mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
97 mov R0,#0
98 mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
99 bx LR
100
101ArmEnableDataCache
102 LDR R1,=DC_ON
103 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
104 ORR R0,R0,R1 ;Set C bit
105 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
106 BX LR
107
108ArmDisableDataCache
109 LDR R1,=DC_ON
110 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
111 BIC R0,R0,R1 ;Clear C bit
112 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
113 BX LR
114
115ArmEnableInstructionCache
116 LDR R1,=IC_ON
117 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
118 ORR R0,R0,R1 ;Set I bit
119 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
120 BX LR
121
122ArmDisableInstructionCache
123 LDR R1,=IC_ON
124 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
125 BIC R0,R0,R1 ;Clear I bit.
126 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
127 BX LR
128
129ArmEnableBranchPrediction
130 mrc p15, 0, r0, c1, c0, 0
131 orr r0, r0, #0x00000800
132 mcr p15, 0, r0, c1, c0, 0
133 bx LR
134
135ArmDisableBranchPrediction
136 mrc p15, 0, r0, c1, c0, 0
137 bic r0, r0, #0x00000800
138 mcr p15, 0, r0, c1, c0, 0
139 bx LR
140
141 END