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11c20f4e | 1 | #/** @file\r |
2 | #\r | |
5c2d456b | 3 | # Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r |
ad7a56e5 | 4 | # Copyright (c) 2015, Intel Corporation. All rights reserved.\r |
11c20f4e | 5 | #\r |
3402aac7 RC |
6 | # This program and the accompanying materials\r |
7 | # are licensed and made available under the terms and conditions of the BSD License\r | |
8 | # which accompanies this distribution. The full text of the license may be found at\r | |
9 | # http://opensource.org/licenses/bsd-license.php\r | |
10 | #\r | |
11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11c20f4e | 13 | #\r |
14 | #**/\r | |
15 | \r | |
16 | [Defines]\r | |
17 | DEC_SPECIFICATION = 0x00010005\r | |
18 | PACKAGE_NAME = ArmPlatformPkg\r | |
3402aac7 | 19 | PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b\r |
11c20f4e | 20 | PACKAGE_VERSION = 0.1\r |
21 | \r | |
22 | ################################################################################\r | |
23 | #\r | |
24 | # Include Section - list of Include Paths that are provided by this package.\r | |
25 | # Comments are used for Keywords and Module Types.\r | |
26 | #\r | |
27 | # Supported Module Types:\r | |
28 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r | |
29 | #\r | |
30 | ################################################################################\r | |
31 | [Includes.common]\r | |
32 | Include # Root include for the package\r | |
33 | \r | |
34 | [Guids.common]\r | |
35 | gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r | |
36 | #\r | |
37 | # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r | |
38 | #\r | |
39 | gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r | |
40 | \r | |
8fc38a3f | 41 | ## Include/Guid/ArmGlobalVariableHob.h\r |
42 | gArmGlobalVariableGuid = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }\r | |
43 | \r | |
da5daf36 HL |
44 | gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }\r |
45 | \r | |
8fc38a3f | 46 | [Ppis]\r |
47 | ## Include/Ppi/ArmGlobalVariable.h\r | |
48 | gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }\r | |
49 | \r | |
11c20f4e | 50 | [PcdsFeatureFlag.common]\r |
51 | # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r | |
52 | gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012\r | |
3402aac7 | 53 | \r |
11c20f4e | 54 | gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001\r |
55 | gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002\r | |
56 | gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r | |
57 | \r | |
68dda854 | 58 | gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C\r |
d8c4bb9a OM |
59 | \r |
60 | # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r | |
61 | # we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r | |
62 | gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r | |
63 | \r | |
5d9e9d1a OM |
64 | # Enable Legacy Linux support in the BDS\r |
65 | gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|TRUE|BOOLEAN|0x0000002E\r | |
66 | \r | |
11c20f4e | 67 | [PcdsFixedAtBuild.common]\r |
695df8ba | 68 | gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r |
2dbcb8f0 | 69 | gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r |
3402aac7 | 70 | \r |
11c20f4e | 71 | # Stack for CPU Cores in Secure Mode\r |
72 | gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005\r | |
2dbcb8f0 | 73 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036\r |
74 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r | |
11c20f4e | 75 | \r |
11c20f4e | 76 | # Stack for CPU Cores in Non Secure Mode\r |
bb5420bb | 77 | gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009\r |
2dbcb8f0 | 78 | gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r |
79 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r | |
3402aac7 | 80 | \r |
11c20f4e | 81 | # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r |
82 | gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r | |
83 | \r | |
84 | # Size to reserve in the primary core stack for PEI Global Variables\r | |
85 | # = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */\r | |
86 | gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016\r | |
87 | # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list\r | |
3402aac7 | 88 | # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.\r |
11c20f4e | 89 | gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017\r |
90 | gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018\r | |
91 | \r | |
8fc38a3f | 92 | # Size to reserve in the primary core stack for SEC Global Variables\r |
93 | gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031\r | |
94 | \r | |
94e0955d OM |
95 | # Boot Monitor FileSystem\r |
96 | gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A\r | |
97 | \r | |
11c20f4e | 98 | #\r |
99 | # ARM Primecells\r | |
100 | #\r | |
101 | \r | |
102 | ## SP804 DualTimer\r | |
103 | gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D\r | |
104 | gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E\r | |
105 | gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A\r | |
106 | gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B\r | |
107 | gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C\r | |
108 | \r | |
109 | ## SP805 Watchdog\r | |
110 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023\r | |
111 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r | |
112 | \r | |
113 | ## PL011 UART\r | |
051e63bb | 114 | gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r |
115 | gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r | |
116 | gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r | |
11c20f4e | 117 | \r |
11c20f4e | 118 | ## PL061 GPIO\r |
119 | gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r | |
3402aac7 | 120 | \r |
98622390 | 121 | ## PL111 Lcd & HdLcd\r |
11c20f4e | 122 | gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026\r |
123 | gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027\r | |
3402aac7 | 124 | \r |
11c20f4e | 125 | ## PL180 MCI\r |
126 | gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028\r | |
127 | gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029\r | |
128 | \r | |
129 | #\r | |
130 | # BDS - Boot Manager\r | |
131 | #\r | |
132 | gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019\r | |
133 | gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C\r | |
134 | gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D\r | |
6bcedcec | 135 | gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F\r |
3402aac7 | 136 | \r |
11c20f4e | 137 | gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B\r |
138 | gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C\r | |
1bc83266 | 139 | \r |
b4e2799b AB |
140 | [PcdsFixedAtBuild.common,PcdsDynamic.common]\r |
141 | ## PL031 RealTimeClock\r | |
142 | gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r | |
143 | gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r | |
144 | \r | |
e48f1f15 LE |
145 | #\r |
146 | # Inclusive range of allowed PCI buses.\r | |
147 | #\r | |
148 | gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E\r | |
149 | gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F\r | |
150 | \r | |
151 | #\r | |
152 | # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r | |
153 | # Note that "IO" is just another MMIO range that simulates IO space; there\r | |
154 | # are no special instructions to access it.\r | |
155 | #\r | |
156 | # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r | |
157 | # specific to their containing address spaces. In order to get the physical\r | |
158 | # address for the CPU, for a given access, the respective translation value\r | |
159 | # has to be added.\r | |
160 | #\r | |
161 | # The translations always have to be initialized like this, using UINT64:\r | |
162 | #\r | |
163 | # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r | |
164 | # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r | |
165 | # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r | |
166 | #\r | |
167 | # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r | |
168 | # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r | |
169 | # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r | |
170 | #\r | |
171 | # because (a) the target address space (ie. the cpu-physical space) is\r | |
172 | # 64-bit, and (b) the translation values are meant as offsets for *modular*\r | |
173 | # arithmetic.\r | |
174 | #\r | |
175 | # Accordingly, the translation itself needs to be implemented as:\r | |
176 | #\r | |
177 | # UINT64 UntranslatedIoAddress; // input parameter\r | |
178 | # UINT32 UntranslatedMmio32Address; // input parameter\r | |
179 | # UINT64 UntranslatedMmio64Address; // input parameter\r | |
180 | #\r | |
181 | # UINT64 TranslatedIoAddress; // output parameter\r | |
182 | # UINT64 TranslatedMmio32Address; // output parameter\r | |
183 | # UINT64 TranslatedMmio64Address; // output parameter\r | |
184 | #\r | |
185 | # TranslatedIoAddress = UntranslatedIoAddress +\r | |
186 | # PcdPciIoTranslation;\r | |
187 | # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r | |
188 | # PcdPciMmio32Translation;\r | |
189 | # TranslatedMmio64Address = UntranslatedMmio64Address +\r | |
190 | # PcdPciMmio64Translation;\r | |
191 | #\r | |
192 | # The modular arithmetic performed in UINT64 ensures that the translation\r | |
193 | # works correctly regardless of the relation between IoCpuBase and\r | |
194 | # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r | |
195 | # PcdPciMmio64Base.\r | |
196 | #\r | |
197 | gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040\r | |
198 | gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041\r | |
199 | gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042\r | |
200 | gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043\r | |
201 | gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044\r | |
202 | gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045\r | |
203 | gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046\r | |
204 | gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047\r | |
205 | gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048\r | |
206 | \r | |
1bc83266 HL |
207 | [PcdsFixedAtBuild.ARM]\r |
208 | # Stack for CPU Cores in Secure Monitor Mode\r | |
209 | gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r | |
210 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r | |
211 | \r | |
212 | [PcdsFixedAtBuild.AARCH64]\r | |
213 | # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r | |
214 | # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r | |
215 | # and PcdCPUCoreSecSecondaryStackSize\r | |
216 | gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r | |
217 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008\r | |
218 | \r |