projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 76bc1743 | 1 | /** @file\r |
| 2 | * Header defining Versatile Express constants (Base addresses, sizes, flags)\r | |
| 3 | *\r | |
| d0c1d371 | 4 | * Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r |
| 76bc1743 | 5 | *\r |
| 6 | * This program and the accompanying materials\r | |
| 7 | * are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | * which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | * http://opensource.org/licenses/bsd-license.php\r | |
| 10 | *\r | |
| 11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | *\r | |
| 14 | **/\r | |
| 15 | \r | |
| 16 | #ifndef __VEXPRESSMOTHERBOARD_H_\r | |
| 17 | #define __VEXPRESSMOTHERBOARD_H_\r | |
| 18 | \r | |
| 19 | #include <ArmPlatform.h>\r | |
| 20 | \r | |
| 21 | /***********************************************************************************\r | |
| 22 | // Motherboard memory-mapped peripherals\r | |
| 23 | ************************************************************************************/\r | |
| 24 | \r | |
| 25 | // Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)\r | |
| 4463f706 | 26 | #define ARM_VE_SYS_ID_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00000)\r |
| ba8bd8ce | 27 | #define ARM_VE_SYS_SW_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00004)\r |
| 76bc1743 | 28 | #define ARM_VE_SYS_LED_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00008)\r |
| 29 | #define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r | |
| 30 | #define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r | |
| 31 | #define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)\r | |
| 32 | #define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r | |
| 33 | #define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r | |
| 34 | #define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)\r | |
| 35 | #define ARM_VE_SYS_FLASH (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)\r | |
| ba8bd8ce | 36 | #define ARM_VE_SYS_CFGSWR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00058)\r |
| 37 | #define ARM_VE_SYS_MISC (ARM_VE_BOARD_PERIPH_BASE + 0x00060)\r | |
| 76bc1743 | 38 | #define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)\r |
| 39 | #define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)\r | |
| 40 | #define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)\r | |
| 41 | #define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)\r | |
| 42 | #define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)\r | |
| 43 | \r | |
| 44 | // SP810 Controller\r | |
| ba8bd8ce | 45 | #ifndef SP810_CTRL_BASE\r |
| 76bc1743 | 46 | #define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x01000)\r |
| ba8bd8ce | 47 | #endif\r |
| 76bc1743 | 48 | \r |
| 76bc1743 | 49 | // PL111 Colour LCD Controller - motherboard\r |
| 50 | #define PL111_CLCD_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x1F000)\r | |
| 51 | #define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1\r | |
| 52 | \r | |
| 53 | // VRAM offset for the PL111 Colour LCD Controller on the motherboard\r | |
| 54 | #define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)\r | |
| 55 | \r | |
| ba8bd8ce | 56 | #define ARM_VE_SYS_PROC_ID_HBI 0xFFF\r |
| 2575b726 | 57 | #define ARM_VE_SYS_PROC_ID_MASK (UINT32)(0xFFU << 24)\r |
| 58 | #define ARM_VE_SYS_PROC_ID_UNSUPPORTED (UINT32)(0xFFU << 24)\r | |
| 59 | #define ARM_VE_SYS_PROC_ID_CORTEX_A9 (UINT32)(0x0CU << 24)\r | |
| 60 | #define ARM_VE_SYS_PROC_ID_CORTEX_A5 (UINT32)(0x12U << 24)\r | |
| 61 | #define ARM_VE_SYS_PROC_ID_CORTEX_A15 (UINT32)(0x14U << 24)\r | |
| ffcf1782 OM |
62 | #define ARM_VE_SYS_PROC_ID_CORTEX_A7 (UINT32)(0x18U << 24)\r |
| 63 | #define ARM_VE_SYS_PROC_ID_CORTEX_A12 (UINT32)(0x1CU << 24)\r | |
| 76bc1743 | 64 | \r |
| ba8bd8ce | 65 | // Boot Master Select:\r |
| 66 | // 0 = Site 1 boot master\r | |
| 67 | // 1 = Site 2 boot master\r | |
| 68 | #define ARM_VE_SYS_MISC_MASTERSITE (1 << 14)\r | |
| 76bc1743 | 69 | //\r |
| 70 | // Sites where the peripheral is fitted\r | |
| 71 | //\r | |
| 72 | #define ARM_VE_UNSUPPORTED ~0\r | |
| 73 | #define ARM_VE_MOTHERBOARD_SITE 0\r | |
| 74 | #define ARM_VE_DAUGHTERBOARD_1_SITE 1\r | |
| 75 | #define ARM_VE_DAUGHTERBOARD_2_SITE 2\r | |
| 76 | \r | |
| 7b80d1a3 | 77 | #define VIRTUAL_SYS_CFG(site,func) (((site) << 24) | (func))\r |
| 78 | \r | |
| 79 | //\r | |
| 80 | // System Configuration Control Functions\r | |
| 81 | //\r | |
| 82 | #define SYS_CFG_OSC 1\r | |
| 83 | #define SYS_CFG_VOLT 2\r | |
| 84 | #define SYS_CFG_AMP 3\r | |
| 85 | #define SYS_CFG_TEMP 4\r | |
| 86 | #define SYS_CFG_RESET 5\r | |
| 87 | #define SYS_CFG_SCC 6\r | |
| 88 | #define SYS_CFG_MUXFPGA 7\r | |
| 89 | #define SYS_CFG_SHUTDOWN 8\r | |
| 90 | #define SYS_CFG_REBOOT 9\r | |
| 91 | #define SYS_CFG_DVIMODE 11\r | |
| 92 | #define SYS_CFG_POWER 12\r | |
| 93 | // Oscillator for Site 1\r | |
| 94 | #define SYS_CFG_OSC_SITE1 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_1_SITE,SYS_CFG_OSC)\r | |
| 95 | // Oscillator for Site 2\r | |
| 96 | #define SYS_CFG_OSC_SITE2 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_2_SITE,SYS_CFG_OSC)\r | |
| 97 | // Can not access the battery backed-up hardware clock on the Versatile Express motherboard\r | |
| 98 | #define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_VE_UNSUPPORTED,1)\r | |
| 99 | \r | |
| 48999d26 OM |
100 | //\r |
| 101 | // System ID\r | |
| 102 | //\r | |
| 103 | // All RTSM VE models have the same System ID : 0x225F500\r | |
| 104 | //\r | |
| 105 | // FVP models have a different System ID.\r | |
| 106 | // Default Base model System ID : 0x00201100\r | |
| 107 | // [31:28] Rev - Board revision: 0x0 = Rev A\r | |
| 108 | // [27:16] HBI - HBI board number in BCD: 0x020 = v8 Base Platform\r | |
| 109 | // [15:12] Variant - Build variant of board: 0x1 = Variant B. (GIC 64k map)\r | |
| 110 | // [11:8] Plat - Platform type: 0x1 = Model\r | |
| 111 | // [7:0] FPGA - FPGA build, BCD coded: 0x00\r | |
| 112 | //\r | |
| 113 | //HBI = 010 = Foundation Model\r | |
| 114 | //HBI = 020 = Base Platform\r | |
| 115 | //\r | |
| 116 | // And specifically, the GIC register banks start at the following\r | |
| 117 | // addresses:\r | |
| 118 | // Variant = 0 Variant = 1\r | |
| 119 | //GICD 0x2c001000 0x2f000000\r | |
| 120 | //GICC 0x2c002000 0x2c000000\r | |
| 121 | //GICH 0x2c004000 0x2c010000\r | |
| 122 | //GICV 0x2c006000 0x2c020000\r | |
| 123 | \r | |
| d0c1d371 OM |
124 | #define ARM_FVP_BASE_BOARD_SYS_ID (0x00200100)\r |
| 125 | #define ARM_FVP_FOUNDATION_BOARD_SYS_ID (0x00100100)\r | |
| 126 | \r | |
| 127 | #define ARM_FVP_SYS_ID_REV_MASK (UINT32)(0xFUL << 28)\r | |
| 128 | #define ARM_FVP_SYS_ID_HBI_MASK (UINT32)(0xFFFUL << 16)\r | |
| 129 | #define ARM_FVP_SYS_ID_VARIANT_MASK (UINT32)(0xFUL << 12)\r | |
| 130 | #define ARM_FVP_SYS_ID_PLAT_MASK (UINT32)(0xFUL << 8 )\r | |
| 131 | #define ARM_FVP_SYS_ID_FPGA_MASK (UINT32)(0xFFUL << 0 )\r | |
| 132 | #define ARM_FVP_GIC_VE_MMAP 0x0\r | |
| 133 | #define ARM_FVP_GIC_BASE_MMAP (UINT32)(1 << 12)\r | |
| 134 | \r | |
| 48999d26 OM |
135 | // The default SYS_IDs. These can be changed when starting the model.\r |
| 136 | #define ARM_RTSM_SYS_ID (0x225F500)\r | |
| d0c1d371 OM |
137 | #define ARM_FVP_BASE_SYS_ID (ARM_FVP_BASE_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)\r |
| 138 | #define ARM_FVP_FOUNDATION_SYS_ID (ARM_FVP_FOUNDATION_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)\r | |
| 48999d26 | 139 | \r |
| 76bc1743 | 140 | #endif /* VEXPRESSMOTHERBOARD_H_ */\r |