projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 88d4f51d | 1 | #\r |
| bebda7ce | 2 | # Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
| 3402aac7 RC |
3 | #\r |
| 4 | # This program and the accompanying materials\r | |
| 5 | # are licensed and made available under the terms and conditions of the BSD License\r | |
| 6 | # which accompanies this distribution. The full text of the license may be found at\r | |
| bebda7ce | 7 | # http://opensource.org/licenses/bsd-license.php\r |
| 88d4f51d | 8 | #\r |
| 3402aac7 RC |
9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 88d4f51d | 11 | #\r |
| 12 | #\r | |
| 13 | \r | |
| 14 | #include <AsmMacroIoLib.h>\r | |
| 2d45f194 | 15 | #include <Library/ArmLib.h>\r |
| 88d4f51d | 16 | \r |
| 17 | #include <Chipset/ArmCortexA9.h>\r | |
| 18 | \r | |
| 04209b53 | 19 | ASM_FUNC(ArmPlatformPeiBootAction)\r |
| b5a57223 | 20 | bx lr\r |
| 21 | \r | |
| 88d4f51d | 22 | # IN None\r |
| 23 | # OUT r0 = SCU Base Address\r | |
| 04209b53 | 24 | ASM_FUNC(ArmGetScuBaseAddress)\r |
| 88d4f51d | 25 | # Read Configuration Base Address Register. ArmCBar cannot be called to get\r |
| 26 | # the Configuration BAR as a stack is not necessary setup. The SCU is at the\r | |
| 27 | # offset 0x0000 from the Private Memory Region.\r | |
| 28 | mrc p15, 4, r0, c15, c0, 0\r | |
| b5a57223 | 29 | bx lr\r |
| 88d4f51d | 30 | \r |
| d05ca26c | 31 | //UINTN\r |
| 32 | //ArmPlatformGetPrimaryCoreMpId (\r | |
| 33 | // VOID\r | |
| 34 | // );\r | |
| 04209b53 AB |
35 | ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)\r |
| 36 | MOV32 (r0, FixedPcdGet32 (PcdArmPrimaryCore))\r | |
| d05ca26c | 37 | bx lr\r |
| 38 | \r | |
| 88d4f51d | 39 | # IN None\r |
| 40 | # OUT r0 = number of cores present in the system\r | |
| 04209b53 | 41 | ASM_FUNC(ArmGetCpuCountPerCluster)\r |
| 88d4f51d | 42 | stmfd SP!, {r1-r2}\r |
| 43 | \r | |
| 44 | # Read CP15 MIDR\r | |
| 45 | mrc p15, 0, r1, c0, c0, 0\r | |
| 46 | \r | |
| 47 | # Check if the CPU is A15\r | |
| 48 | mov r1, r1, LSR #4\r | |
| 04209b53 | 49 | MOV32 (r0, ARM_CPU_TYPE_MASK)\r |
| 88d4f51d | 50 | and r1, r1, r0\r |
| 51 | \r | |
| 04209b53 | 52 | MOV32 (r0, ARM_CPU_TYPE_A15)\r |
| 88d4f51d | 53 | cmp r1, r0\r |
| 54 | beq _Read_cp15_reg\r | |
| 55 | \r | |
| 56 | _CPU_is_not_A15:\r | |
| 57 | mov r2, lr @ Save link register\r | |
| 58 | bl ArmGetScuBaseAddress @ Read SCU Base Address\r | |
| 59 | mov lr, r2 @ Restore link register val\r | |
| 60 | ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count\r | |
| 61 | b _Return\r | |
| 62 | \r | |
| 63 | _Read_cp15_reg:\r | |
| 64 | mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count\r | |
| 65 | lsr r0, #24\r | |
| 66 | \r | |
| 67 | _Return:\r | |
| 68 | and r0, r0, #3\r | |
| 69 | # Add '1' to the number of CPU on the Cluster\r | |
| 70 | add r0, r0, #1\r | |
| 71 | ldmfd SP!, {r1-r2}\r | |
| 72 | bx lr\r | |
| 73 | \r | |
| bebda7ce | 74 | //UINTN\r |
| 75 | //ArmPlatformIsPrimaryCore (\r | |
| 76 | // IN UINTN MpId\r | |
| 77 | // );\r | |
| 04209b53 AB |
78 | ASM_FUNC(ArmPlatformIsPrimaryCore)\r |
| 79 | MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCoreMask))\r | |
| bebda7ce | 80 | and r0, r0, r1\r |
| 04209b53 | 81 | MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCore))\r |
| bebda7ce | 82 | cmp r0, r1\r |
| 83 | moveq r0, #1\r | |
| 84 | movne r0, #0\r | |
| 91c38d4e | 85 | bx lr\r |
| bebda7ce | 86 | \r |
| 2d45f194 | 87 | //UINTN\r |
| 88 | //ArmPlatformGetCorePosition (\r | |
| 89 | // IN UINTN MpId\r | |
| 90 | // );\r | |
| 04209b53 | 91 | ASM_FUNC(ArmPlatformGetCorePosition)\r |
| 2d45f194 | 92 | and r1, r0, #ARM_CORE_MASK\r |
| 93 | and r0, r0, #ARM_CLUSTER_MASK\r | |
| 94 | add r0, r1, r0, LSR #7\r | |
| 95 | bx lr\r | |
| 96 | \r | |
| 3402aac7 | 97 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |