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88d4f51d | 1 | #\r |
bebda7ce | 2 | # Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
88d4f51d | 3 | # \r |
4 | # This program and the accompanying materials \r | |
5 | # are licensed and made available under the terms and conditions of the BSD License \r | |
6 | # which accompanies this distribution. The full text of the license may be found at \r | |
bebda7ce | 7 | # http://opensource.org/licenses/bsd-license.php\r |
88d4f51d | 8 | #\r |
9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | #\r | |
12 | #\r | |
13 | \r | |
14 | #include <AsmMacroIoLib.h>\r | |
15 | #include <Base.h>\r | |
2d45f194 | 16 | #include <Library/ArmLib.h>\r |
88d4f51d | 17 | #include <Library/PcdLib.h>\r |
18 | #include <AutoGen.h>\r | |
b5a57223 | 19 | #include "AsmMacroIoLib.inc"\r |
88d4f51d | 20 | \r |
21 | #include <Chipset/ArmCortexA9.h>\r | |
22 | \r | |
23 | .text\r | |
24 | .align 2\r | |
25 | \r | |
b5a57223 | 26 | GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r |
88d4f51d | 27 | GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)\r |
bebda7ce | 28 | GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r |
d05ca26c | 29 | GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r |
2d45f194 | 30 | GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r |
bebda7ce | 31 | \r |
32 | GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r | |
33 | GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r | |
88d4f51d | 34 | \r |
b5a57223 | 35 | ASM_PFX(ArmPlatformPeiBootAction):\r |
36 | bx lr\r | |
37 | \r | |
88d4f51d | 38 | # IN None\r |
39 | # OUT r0 = SCU Base Address\r | |
40 | ASM_PFX(ArmGetScuBaseAddress):\r | |
41 | # Read Configuration Base Address Register. ArmCBar cannot be called to get\r | |
42 | # the Configuration BAR as a stack is not necessary setup. The SCU is at the\r | |
43 | # offset 0x0000 from the Private Memory Region.\r | |
44 | mrc p15, 4, r0, c15, c0, 0\r | |
b5a57223 | 45 | bx lr\r |
88d4f51d | 46 | \r |
d05ca26c | 47 | //UINTN\r |
48 | //ArmPlatformGetPrimaryCoreMpId (\r | |
49 | // VOID\r | |
50 | // );\r | |
51 | ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r | |
99267097 | 52 | LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r |
d05ca26c | 53 | ldr r0, [r0]\r |
54 | bx lr\r | |
55 | \r | |
88d4f51d | 56 | # IN None\r |
57 | # OUT r0 = number of cores present in the system\r | |
58 | ASM_PFX(ArmGetCpuCountPerCluster):\r | |
59 | stmfd SP!, {r1-r2}\r | |
60 | \r | |
61 | # Read CP15 MIDR\r | |
62 | mrc p15, 0, r1, c0, c0, 0\r | |
63 | \r | |
64 | # Check if the CPU is A15\r | |
65 | mov r1, r1, LSR #4\r | |
66 | LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)\r | |
67 | and r1, r1, r0\r | |
68 | \r | |
69 | LoadConstantToReg (ARM_CPU_TYPE_A15, r0)\r | |
70 | cmp r1, r0\r | |
71 | beq _Read_cp15_reg\r | |
72 | \r | |
73 | _CPU_is_not_A15:\r | |
74 | mov r2, lr @ Save link register\r | |
75 | bl ArmGetScuBaseAddress @ Read SCU Base Address\r | |
76 | mov lr, r2 @ Restore link register val\r | |
77 | ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count\r | |
78 | b _Return\r | |
79 | \r | |
80 | _Read_cp15_reg:\r | |
81 | mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count\r | |
82 | lsr r0, #24\r | |
83 | \r | |
84 | _Return:\r | |
85 | and r0, r0, #3\r | |
86 | # Add '1' to the number of CPU on the Cluster\r | |
87 | add r0, r0, #1\r | |
88 | ldmfd SP!, {r1-r2}\r | |
89 | bx lr\r | |
90 | \r | |
bebda7ce | 91 | //UINTN\r |
92 | //ArmPlatformIsPrimaryCore (\r | |
93 | // IN UINTN MpId\r | |
94 | // );\r | |
95 | ASM_PFX(ArmPlatformIsPrimaryCore):\r | |
96 | LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r | |
97 | ldr r1, [r1]\r | |
98 | and r0, r0, r1\r | |
99 | LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r | |
100 | ldr r1, [r1]\r | |
101 | cmp r0, r1\r | |
102 | moveq r0, #1\r | |
103 | movne r0, #0\r | |
104 | bx lr\r | |
105 | \r | |
2d45f194 | 106 | //UINTN\r |
107 | //ArmPlatformGetCorePosition (\r | |
108 | // IN UINTN MpId\r | |
109 | // );\r | |
110 | ASM_PFX(ArmPlatformGetCorePosition):\r | |
111 | and r1, r0, #ARM_CORE_MASK\r | |
112 | and r0, r0, #ARM_CLUSTER_MASK\r | |
113 | add r0, r1, r0, LSR #7\r | |
114 | bx lr\r | |
115 | \r | |
88d4f51d | 116 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED \r |