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1 | //\r |
2 | // Copyright (c) 2013, ARM Limited. All rights reserved.\r | |
3 | //\r | |
4 | // This program and the accompanying materials\r | |
5 | // are licensed and made available under the terms and conditions of the BSD License\r | |
6 | // which accompanies this distribution. The full text of the license may be found at\r | |
7 | // http://opensource.org/licenses/bsd-license.php\r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | //\r | |
12 | //\r | |
13 | \r | |
14 | #include <AsmMacroIoLib.h>\r | |
15 | \r | |
16 | // Register definitions used by GCC for GICv3 access.\r | |
17 | // These are defined by ARMCC, so keep them in the GCC specific code for now.\r | |
18 | #define ICC_SRE_EL2 S3_4_C12_C9_5\r | |
19 | #define ICC_SRE_EL3 S3_6_C12_C12_5\r | |
20 | #define ICC_CTLR_EL1 S3_0_C12_C12_4\r | |
21 | #define ICC_CTLR_EL3 S3_6_C12_C12_4\r | |
22 | #define ICC_PMR_EL1 S3_0_C4_C6_0\r | |
23 | \r | |
24 | .text\r | |
25 | .align 3\r | |
26 | \r | |
27 | GCC_ASM_EXPORT(InitializeGicV3)\r | |
28 | \r | |
29 | /* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */\r | |
30 | ASM_PFX(InitializeGicV3):\r | |
31 | // We have a GICv3. UEFI still uses the GICv2 mode. We must do enough setup\r | |
32 | // to allow Linux to use GICv3 if it chooses.\r | |
33 | \r | |
34 | // In order to setup NS side we need to enable it first.\r | |
35 | mrs x0, scr_el3\r | |
36 | orr x0, x0, #1\r | |
37 | msr scr_el3, x0\r | |
38 | \r | |
39 | // Enable SRE at EL3 and ICC_SRE_EL2 access\r | |
40 | mov x0, #((1 << 3) | (1 << 0)) // Enable | SRE\r | |
41 | mrs x1, ICC_SRE_EL3\r | |
42 | orr x1, x1, x0\r | |
43 | msr ICC_SRE_EL3, x1\r | |
44 | isb\r | |
45 | \r | |
46 | // Enable SRE at EL2 and ICC_SRE_EL1 access..\r | |
47 | mrs x1, ICC_SRE_EL2\r | |
48 | orr x1, x1, x0\r | |
49 | msr ICC_SRE_EL2, x1\r | |
50 | isb\r | |
51 | \r | |
52 | // Configure CPU interface\r | |
53 | msr ICC_CTLR_EL3, xzr\r | |
54 | isb\r | |
55 | msr ICC_CTLR_EL1, xzr\r | |
56 | isb\r | |
57 | \r | |
58 | // The MemoryMap view and Register view may not be consistent, So Set PMR again.\r | |
59 | mov w1, #1 << 7 // allow NS access to GICC_PMR\r | |
60 | msr ICC_PMR_EL1, x1\r | |
61 | isb\r | |
62 | \r | |
63 | // Remove the SCR.NS bit\r | |
64 | mrs x0, scr_el3\r | |
65 | bic x0, x0, #1\r | |
66 | msr scr_el3, x0\r | |
67 | ret\r |