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633724f4 | 1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | * \r | |
5 | * This program and the accompanying materials \r | |
6 | * are licensed and made available under the terms and conditions of the BSD License \r | |
7 | * which accompanies this distribution. The full text of the license may be found at \r | |
8 | * http://opensource.org/licenses/bsd-license.php \r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
06a89733 | 15 | #include <Uefi.h>\r |
16 | \r | |
633724f4 | 17 | #include <Library/IoLib.h>\r |
18 | #include <Library/DebugLib.h>\r | |
06a89733 | 19 | \r |
633724f4 | 20 | #include <Drivers/PL341Dmc.h>\r |
21 | \r | |
22 | // Macros for writing to DDR2 controller.\r | |
23 | #define DmcWriteReg(reg,val) MmioWrite32(DmcBase + reg, val)\r | |
24 | #define DmcReadReg(reg) MmioRead32(DmcBase + reg)\r | |
25 | \r | |
26 | // Macros for writing/reading to DDR2 PHY controller\r | |
27 | #define DmcPhyWriteReg(reg,val) MmioWrite32(DmcPhyBase + reg, val)\r | |
28 | #define DmcPhyReadReg(reg) MmioRead32(DmcPhyBase + reg)\r | |
29 | \r | |
30 | // Initialise PL341 Dynamic Memory Controller\r | |
31 | VOID\r | |
32 | PL341DmcInit (\r | |
06a89733 | 33 | IN UINTN DmcBase,\r |
34 | IN PL341_DMC_CONFIG* DmcConfig\r | |
633724f4 | 35 | )\r |
36 | {\r | |
633724f4 | 37 | UINTN Index;\r |
38 | UINT32 Chip;\r | |
39 | \r | |
633724f4 | 40 | // Set config mode\r |
41 | DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_CONFIGURE);\r | |
42 | \r | |
43 | //\r | |
44 | // Setup the QoS AXI ID bits\r | |
45 | //\r | |
46 | if (DmcConfig->HasQos) {\r | |
47 | // CLCD AXIID = 000\r | |
48 | DmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE | DMC_ID_CFG_QOS_MIN);\r | |
49 | \r | |
50 | // Default disable QoS\r | |
51 | DmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
52 | DmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
53 | DmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
54 | DmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
55 | DmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
56 | DmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
57 | DmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
58 | DmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
59 | DmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
60 | DmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
61 | DmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
62 | DmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
63 | DmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
64 | DmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
65 | DmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r | |
66 | }\r | |
67 | \r | |
68 | //\r | |
69 | // Initialise memory controlller\r | |
70 | //\r | |
06a89733 | 71 | DmcWriteReg(DMC_REFRESH_PRD_REG, DmcConfig->RefreshPeriod);\r |
72 | DmcWriteReg(DMC_CAS_LATENCY_REG, DmcConfig->CasLatency);\r | |
73 | DmcWriteReg(DMC_WRITE_LATENCY_REG, DmcConfig->WriteLatency);\r | |
633724f4 | 74 | DmcWriteReg(DMC_T_MRD_REG, DmcConfig->t_mrd);\r |
75 | DmcWriteReg(DMC_T_RAS_REG, DmcConfig->t_ras);\r | |
76 | DmcWriteReg(DMC_T_RC_REG, DmcConfig->t_rc);\r | |
77 | DmcWriteReg(DMC_T_RCD_REG, DmcConfig->t_rcd);\r | |
78 | DmcWriteReg(DMC_T_RFC_REG, DmcConfig->t_rfc);\r | |
79 | DmcWriteReg(DMC_T_RP_REG, DmcConfig->t_rp);\r | |
80 | DmcWriteReg(DMC_T_RRD_REG, DmcConfig->t_rrd);\r | |
81 | DmcWriteReg(DMC_T_WR_REG, DmcConfig->t_wr);\r | |
82 | DmcWriteReg(DMC_T_WTR_REG, DmcConfig->t_wtr);\r | |
83 | DmcWriteReg(DMC_T_XP_REG, DmcConfig->t_xp);\r | |
84 | DmcWriteReg(DMC_T_XSR_REG, DmcConfig->t_xsr);\r | |
85 | DmcWriteReg(DMC_T_ESR_REG, DmcConfig->t_esr);\r | |
86 | DmcWriteReg(DMC_T_FAW_REG, DmcConfig->t_faw);\r | |
87 | DmcWriteReg(DMC_T_WRLAT_DIFF, DmcConfig->t_wdata_en);\r | |
88 | DmcWriteReg(DMC_T_RDATA_EN, DmcConfig->t_data_en);\r | |
89 | \r | |
90 | //\r | |
91 | // Initialise PL341 Mem Config Registers\r | |
92 | //\r | |
93 | \r | |
94 | // Set PL341 Memory Config\r | |
95 | DmcWriteReg(DMC_MEMORY_CONFIG_REG, DmcConfig->MemoryCfg);\r | |
96 | \r | |
97 | // Set PL341 Memory Config 2\r | |
98 | DmcWriteReg(DMC_MEMORY_CFG2_REG, DmcConfig->MemoryCfg2);\r | |
99 | \r | |
06a89733 | 100 | // Set PL341 Memory Config 3\r |
101 | DmcWriteReg(DMC_MEMORY_CFG3_REG, DmcConfig->MemoryCfg3);\r | |
102 | \r | |
633724f4 | 103 | // Set PL341 Chip Select <n>\r |
104 | DmcWriteReg(DMC_CHIP_0_CFG_REG, DmcConfig->ChipCfg0);\r | |
105 | DmcWriteReg(DMC_CHIP_1_CFG_REG, DmcConfig->ChipCfg1);\r | |
106 | DmcWriteReg(DMC_CHIP_2_CFG_REG, DmcConfig->ChipCfg2);\r | |
107 | DmcWriteReg(DMC_CHIP_3_CFG_REG, DmcConfig->ChipCfg3);\r | |
108 | \r | |
109 | // Delay\r | |
110 | for (Index = 0; Index < 10; Index++) {\r | |
111 | DmcReadReg(DMC_STATUS_REG);\r | |
112 | }\r | |
113 | \r | |
633724f4 | 114 | if (DmcConfig->IsUserCfg) {\r |
115 | //\r | |
116 | // Set Test Chip PHY Registers via PL341 User Config Reg\r | |
117 | // Note that user_cfgX registers are Write Only\r | |
118 | //\r | |
119 | // DLL Freq set = 250MHz - 266MHz\r | |
120 | //\r | |
121 | DmcWriteReg(DMC_USER_0_CFG_REG, DmcConfig->User0Cfg);\r | |
122 | \r | |
123 | // user_config2\r | |
124 | // ------------\r | |
125 | // Set defaults before calibrating the DDR2 buffer impendence\r | |
126 | // - Disable ODT\r | |
127 | // - Default drive strengths\r | |
128 | DmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198);\r | |
129 | \r | |
130 | //\r | |
131 | // Auto calibrate the DDR2 buffers impendence\r | |
132 | //\r | |
133 | while (!(DmcReadReg(DMC_USER_STATUS_REG) & 0x100));\r | |
134 | \r | |
135 | // Set the output driven strength\r | |
136 | DmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 | DmcConfig->User2Cfg);\r | |
137 | \r | |
138 | //\r | |
139 | // Set PL341 Feature Control Register\r | |
140 | //\r | |
141 | // Disable early BRESP - use to optimise CLCD performance\r | |
142 | DmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001);\r | |
143 | }\r | |
144 | \r | |
145 | //\r | |
146 | // Config memories\r | |
147 | //\r | |
148 | for (Chip = 0; Chip < DmcConfig->MaxChip; Chip++) {\r | |
149 | // Send nop\r | |
150 | DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_NOP);\r | |
151 | \r | |
152 | // Pre-charge all\r | |
153 | DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r | |
154 | \r | |
155 | // Delay\r | |
156 | for (Index = 0; Index < 10; Index++) {\r | |
157 | DmcReadReg(DMC_STATUS_REG);\r | |
158 | }\r | |
159 | \r | |
160 | // Set (EMR2) extended mode register 2\r | |
161 | DmcWriteReg(DMC_DIRECT_CMD_REG,\r | |
162 | DMC_DIRECT_CMD_CHIP_ADDR(Chip) |\r | |
163 | DMC_DIRECT_CMD_BANKADDR(2) |\r | |
164 | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r | |
165 | \r | |
166 | // Set (EMR3) extended mode register 3\r | |
167 | DmcWriteReg(DMC_DIRECT_CMD_REG,\r | |
168 | DMC_DIRECT_CMD_CHIP_ADDR(Chip) |\r | |
169 | DMC_DIRECT_CMD_BANKADDR(3) |\r | |
170 | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r | |
171 | \r | |
172 | //\r | |
173 | // Set (EMR) Extended Mode Register\r | |
174 | //\r | |
175 | // Put into OCD default state\r | |
176 | DmcWriteReg(DMC_DIRECT_CMD_REG,DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_BANKADDR(1) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r | |
177 | \r | |
178 | //\r | |
179 | // Set (MR) mode register - With DLL reset\r | |
180 | //\r | |
181 | DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG | DmcConfig->ModeReg | DDR2_MR_DLL_RESET);\r | |
182 | \r | |
183 | // Pre-charge all\r | |
184 | DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r | |
185 | // Auto-refresh\r | |
186 | DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r | |
187 | // Auto-refresh\r | |
188 | DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r | |
189 | \r | |
190 | //\r | |
191 | // Set (MR) mode register - Without DLL reset\r | |
192 | //\r | |
193 | DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG | DmcConfig->ModeReg);\r | |
194 | \r | |
195 | // Delay\r | |
196 | for (Index = 0; Index < 10; Index++) {\r | |
197 | DmcReadReg(DMC_STATUS_REG);\r | |
198 | }\r | |
199 | \r | |
200 | //\r | |
201 | // Set (EMR) extended mode register - Enable OCD defaults\r | |
202 | //\r | |
203 | DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |\r | |
204 | (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);\r | |
205 | \r | |
206 | // Delay\r | |
207 | for (Index = 0; Index < 10; Index++) {\r | |
208 | DmcReadReg(DMC_STATUS_REG);\r | |
209 | }\r | |
210 | \r | |
211 | // Set (EMR) extended mode register - OCD Exit\r | |
212 | DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |\r | |
213 | (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);\r | |
06a89733 | 214 | \r |
215 | // Delay\r | |
216 | for (Index = 0; Index < 10; Index++) {\r | |
217 | DmcReadReg(DMC_STATUS_REG);\r | |
218 | }\r | |
633724f4 | 219 | }\r |
220 | \r | |
221 | // Move DDR2 Controller to Ready state by issueing GO command\r | |
222 | DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_GO);\r | |
223 | \r | |
224 | // wait for ready\r | |
225 | while (!(DmcReadReg(DMC_STATUS_REG) & DMC_STATUS_READY));\r | |
226 | \r | |
227 | }\r |