[mirror_edk2.git] / ArmPlatformPkg / Drivers / PL35xSmc / InitializeSMC.asm

//\r
//  Copyright (c) 2011, ARM Limited. All rights reserved.\r
//  \r
//  This program and the accompanying materials                          \r
//  are licensed and made available under the terms and conditions of the BSD License         \r
//  which accompanies this distribution.  The full text of the license may be found at        \r
//  http://opensource.org/licenses/bsd-license.php                                            \r
//\r
//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
//\r
//\r
\r
#include <AsmMacroIoLib.h>\r
#include <Library/PcdLib.h>\r
#include <Drivers/PL35xSmc.h>\r
#include <AutoGen.h>\r
\r
  INCLUDE AsmMacroIoLib.inc\r
  \r
  EXPORT  SMCInitializeNOR\r
  EXPORT  SMCInitializeSRAM\r
  EXPORT  SMCInitializePeripherals\r
  EXPORT  SMCInitializeVRAM\r
\r
  PRESERVE8\r
  AREA    ModuleInitializeSMC, CODE, READONLY\r
  \r
// CS0  CS0-Interf0     NOR1 flash on the motherboard\r
// CS1  CS1-Interf0     Reserved for the motherboard\r
// CS2  CS2-Interf0     SRAM on the motherboard\r
// CS3  CS3-Interf0     memory-mapped Ethernet and USB controllers on the motherboard\r
// CS4  CS0-Interf1     NOR2 flash on the motherboard\r
// CS5  CS1-Interf1     memory-mapped peripherals\r
// CS6  CS2-Interf1     memory-mapped peripherals\r
// CS7  CS3-Interf1     system memory-mapped peripherals on the motherboard.\r
\r
// IN r1 SmcBase\r
// IN r2 ChipSelect\r
// NOTE: This code is been called before any stack has been setup. It means some registers\r
//       could be overwritten (case of 'r0')\r
SMCInitializeNOR\r
  // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
  //   - Read cycle timeout  = 0xA (0:3)\r
  //   - Write cycle timeout = 0x3(7:4)\r
  //   - OE Assertion Delay  = 0x9(11:8)\r
  //   - WE Assertion delay  = 0x3(15:12)\r
  //   - Page cycle timeout  = 0x2(19:16)\r
  ldr     r0, = 0x0002393A\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
  \r
  // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
  ldr     r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_ADV)\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
\r
  // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
  ldr     r0, =PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r
  orr     r0, r0, r2\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
  \r
  bx    lr\r
\r
\r
//\r
// Setup SRAM (CS2-Interface0)\r
//\r
SMCInitializeSRAM\r
  ldr     r0, = 0x00027158\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
\r
  ldr     r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_ADV)\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
  \r
  ldr     r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,2))\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
\r
  bx    lr\r
\r
SMCInitializePeripherals\r
//\r
// USB/Eth/VRAM (CS3-Interface0)\r
//\r
  ldr     r0, = 0x000CD2AA\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
  ldr     r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
        \r
  ldr     r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,3))\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
\r
\r
//\r
// Setup Peripherals (CS3-Interface1)\r
//\r
  ldr     r0, = 0x00025156\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
  ldr     r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
        \r
  ldr     r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(1,3))\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
\r
  bx    lr\r
\r
\r
// IN r1 SmcBase\r
// IN r2 VideoSRamBase\r
// NOTE: This code is been called before any stack has been setup. It means some registers\r
//       could be overwritten (case of 'r0')\r
SMCInitializeVRAM\r
  //\r
  // Setup VRAM (CS1-Interface0)\r
  //\r
  ldr     r0, =  0x00049249\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
  ldr     r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
        \r
  ldr     r0, = (PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,1))\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
  \r
  //\r
  // Page mode setup for VRAM\r
  //\r
\r
  // Read current state\r
  ldr     r0, [r2, #0]  \r
  ldr     r0, [r2, #0]  \r
  ldr     r0, = 0x00000000\r
  str     r0, [r2, #0] \r
  ldr     r0, [r2, #0]  \r
\r
  // Enable page mode\r
  ldr     r0, [r2, #0]  \r
  ldr     r0, [r2, #0]  \r
  ldr     r0, = 0x00000000\r
  str     r0, [r2, #0] \r
  ldr     r0, = 0x00900090\r
  str     r0, [r2, #0] \r
\r
  // Confirm page mode enabled\r
  ldr     r0, [r2, #0]  \r
  ldr     r0, [r2, #0]  \r
  ldr     r0, = 0x00000000\r
  str     r0, [r2, #0] \r
  ldr     r0, [r2, #0]  \r
  \r
  bx    lr\r
  \r
  END\r
Commit	Line	Data
633724f4	1	//\r
	2	// Copyright (c) 2011, ARM Limited. All rights reserved.\r
	3	// \r
	4	// This program and the accompanying materials \r
	5	// are licensed and made available under the terms and conditions of the BSD License \r
	6	// which accompanies this distribution. The full text of the license may be found at \r
	7	// http://opensource.org/licenses/bsd-license.php \r
	8	//\r
	9	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	//\r
	12	//\r
	13	\r
	14	#include <AsmMacroIoLib.h>\r
	15	#include <Library/PcdLib.h>\r
	16	#include <Drivers/PL35xSmc.h>\r
	17	#include <AutoGen.h>\r
	18	\r
	19	INCLUDE AsmMacroIoLib.inc\r
	20	\r
	21	EXPORT SMCInitializeNOR\r
	22	EXPORT SMCInitializeSRAM\r
	23	EXPORT SMCInitializePeripherals\r
	24	EXPORT SMCInitializeVRAM\r
	25	\r
	26	PRESERVE8\r
	27	AREA ModuleInitializeSMC, CODE, READONLY\r
	28	\r
	29	// CS0 CS0-Interf0 NOR1 flash on the motherboard\r
	30	// CS1 CS1-Interf0 Reserved for the motherboard\r
	31	// CS2 CS2-Interf0 SRAM on the motherboard\r
	32	// CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard\r
	33	// CS4 CS0-Interf1 NOR2 flash on the motherboard\r
	34	// CS5 CS1-Interf1 memory-mapped peripherals\r
	35	// CS6 CS2-Interf1 memory-mapped peripherals\r
	36	// CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.\r
	37	\r
	38	// IN r1 SmcBase\r
	39	// IN r2 ChipSelect\r
	40	// NOTE: This code is been called before any stack has been setup. It means some registers\r
	41	// could be overwritten (case of 'r0')\r
	42	SMCInitializeNOR\r
	43	// Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
	44	// - Read cycle timeout = 0xA (0:3)\r
	45	// - Write cycle timeout = 0x3(7:4)\r
	46	// - OE Assertion Delay = 0x9(11:8)\r
	47	// - WE Assertion delay = 0x3(15:12)\r
	48	// - Page cycle timeout = 0x2(19:16)\r
	49	ldr r0, = 0x0002393A\r
	50	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
	51	\r
	52	// Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
	53	ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_ADV)\r
	54	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
	55	\r
	56	// Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
	57	ldr r0, =PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r
	58	orr r0, r0, r2\r
	59	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
	60	\r
	61	bx lr\r
	62	\r
	63	\r
	64	//\r
65	// Setup SRAM (CS2-Interface0)\r
66	//\r
67	SMCInitializeSRAM\r
68	ldr r0, = 0x00027158\r
69	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
70	\r
71	ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_ADV)\r
72	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
73	\r
74	ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,2))\r
75	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
76	\r
77	bx lr\r
78	\r
79	SMCInitializePeripherals\r
80	//\r
81	// USB/Eth/VRAM (CS3-Interface0)\r
82	//\r
83	ldr r0, = 0x000CD2AA\r
84	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
85	\r
86	ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
87	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
88	\r
89	ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,3))\r
90	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
91	\r
92	\r
93	//\r
94	// Setup Peripherals (CS3-Interface1)\r
95	//\r
96	ldr r0, = 0x00025156\r
97	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
98	\r
99	ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
100	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
101	\r
102	ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(1,3))\r
103	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
104	\r
105	bx lr\r
106	\r
107	\r
108	// IN r1 SmcBase\r
109	// IN r2 VideoSRamBase\r
110	// NOTE: This code is been called before any stack has been setup. It means some registers\r
111	// could be overwritten (case of 'r0')\r
112	SMCInitializeVRAM\r
113	//\r
114	// Setup VRAM (CS1-Interface0)\r
115	//\r
116	ldr r0, = 0x00049249\r
117	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
118	\r
119	ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
120	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
121	\r
122	ldr r0, = (PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,1))\r
123	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
124	\r
125	//\r
126	// Page mode setup for VRAM\r
127	//\r
128	\r
129	// Read current state\r
130	ldr r0, [r2, #0] \r
131	ldr r0, [r2, #0] \r
132	ldr r0, = 0x00000000\r
133	str r0, [r2, #0] \r
134	ldr r0, [r2, #0] \r
135	\r
136	// Enable page mode\r
137	ldr r0, [r2, #0] \r
138	ldr r0, [r2, #0] \r
139	ldr r0, = 0x00000000\r
140	str r0, [r2, #0] \r
141	ldr r0, = 0x00900090\r
142	str r0, [r2, #0] \r
143	\r
144	// Confirm page mode enabled\r
145	ldr r0, [r2, #0] \r
146	ldr r0, [r2, #0] \r
147	ldr r0, = 0x00000000\r
148	str r0, [r2, #0] \r
149	ldr r0, [r2, #0] \r
150	\r
151	bx lr\r
152	\r
153	END\r