[mirror_edk2.git] / ArmPlatformPkg / Drivers / PL35xSmc / InitializeSMC.asm

//\r
//  Copyright (c) 2011, ARM Limited. All rights reserved.\r
//  \r
//  This program and the accompanying materials                          \r
//  are licensed and made available under the terms and conditions of the BSD License         \r
//  which accompanies this distribution.  The full text of the license may be found at        \r
//  http://opensource.org/licenses/bsd-license.php                                            \r
//\r
//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
//\r
//\r
\r
#include <AsmMacroIoLib.h>\r
#include <Library/PcdLib.h>\r
#include <Drivers/PL35xSmc.h>\r
#include <AutoGen.h>\r
\r
  INCLUDE AsmMacroIoLib.inc\r
  \r
  EXPORT  PL35xSmcInitialize\r
\r
  PRESERVE8\r
  AREA    ModuleInitializeSMC, CODE, READONLY\r
  \r
// IN r1 Smc Base Address\r
// IN r2 Smc Configuration Start Address\r
// IN r3 Smc Configuration End Address\r
// NOTE: This code is been called before any stack has been setup. It means some registers\r
//       could be overwritten (case of 'r0')\r
PL35xSmcInitialize\r
  // While (SmcConfigurationStart < SmcConfigurationEnd)\r
  cmp   r2, r3\r
  blxge lr\r
\r
  // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
  ldr   r0, [r2, #0x4]\r
  str   r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]\r
\r
  // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
  ldr   r0, [r2, #0x8]\r
  str   r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]\r
\r
  // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
  ldr   r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r
  ldr   r4, [r2, #0x0]\r
  orr   r0, r0, r4\r
  str   r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]\r
\r
  add   r2, #0xC\r
  b     PL35xSmcInitialize\r
\r
Commit	Line	Data
633724f4	1	//\r
	2	// Copyright (c) 2011, ARM Limited. All rights reserved.\r
	3	// \r
	4	// This program and the accompanying materials \r
	5	// are licensed and made available under the terms and conditions of the BSD License \r
	6	// which accompanies this distribution. The full text of the license may be found at \r
	7	// http://opensource.org/licenses/bsd-license.php \r
	8	//\r
	9	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	//\r
	12	//\r
	13	\r
	14	#include <AsmMacroIoLib.h>\r
	15	#include <Library/PcdLib.h>\r
	16	#include <Drivers/PL35xSmc.h>\r
	17	#include <AutoGen.h>\r
	18	\r
	19	INCLUDE AsmMacroIoLib.inc\r
	20	\r
c52e2dca	21	EXPORT PL35xSmcInitialize\r
633724f4	22	\r
	23	PRESERVE8\r
	24	AREA ModuleInitializeSMC, CODE, READONLY\r
	25	\r
c52e2dca	26	// IN r1 Smc Base Address\r
	27	// IN r2 Smc Configuration Start Address\r
	28	// IN r3 Smc Configuration End Address\r
633724f4	29	// NOTE: This code is been called before any stack has been setup. It means some registers\r
633724f4	30	// could be overwritten (case of 'r0')\r
c52e2dca	31	PL35xSmcInitialize\r
	32	// While (SmcConfigurationStart < SmcConfigurationEnd)\r
	33	cmp r2, r3\r
	34	blxge lr\r
	35	\r
633724f4	36	// Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
c52e2dca	37	ldr r0, [r2, #0x4]\r
	38	str r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]\r
	39	\r
633724f4	40	// Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
c52e2dca	41	ldr r0, [r2, #0x8]\r
c52e2dca	42	str r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]\r
633724f4	43	\r
633724f4	44	// Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
c52e2dca	45	ldr r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r
	46	ldr r4, [r2, #0x0]\r
	47	orr r0, r0, r4\r
	48	str r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]\r
633724f4	49	\r
c52e2dca	50	add r2, #0xC\r
c52e2dca	51	b PL35xSmcInitialize\r
633724f4	52	\r