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33e7c2ab | 1 | /** @file\r |
2 | *\r | |
a12da33b | 3 | * Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
33e7c2ab | 4 | *\r |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | \r | |
16 | #ifndef __SP805_WATCHDOG_H__\r | |
17 | #define __SP805_WATCHDOG_H__\r | |
18 | \r | |
33e7c2ab | 19 | // SP805 Watchdog Registers\r |
5cc45b70 | 20 | #define SP805_WDOG_LOAD_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x000)\r |
21 | #define SP805_WDOG_CURRENT_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x004)\r | |
22 | #define SP805_WDOG_CONTROL_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x008)\r | |
23 | #define SP805_WDOG_INT_CLR_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x00C)\r | |
24 | #define SP805_WDOG_RAW_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x010)\r | |
25 | #define SP805_WDOG_MSK_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x014)\r | |
26 | #define SP805_WDOG_LOCK_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xC00)\r | |
33e7c2ab | 27 | \r |
5cc45b70 | 28 | #define SP805_WDOG_PERIPH_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE0)\r |
29 | #define SP805_WDOG_PERIPH_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE4)\r | |
30 | #define SP805_WDOG_PERIPH_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE8)\r | |
31 | #define SP805_WDOG_PERIPH_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFEC)\r | |
33e7c2ab | 32 | \r |
5cc45b70 | 33 | #define SP805_WDOG_PCELL_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF0)\r |
34 | #define SP805_WDOG_PCELL_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF4)\r | |
35 | #define SP805_WDOG_PCELL_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF8)\r | |
36 | #define SP805_WDOG_PCELL_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFFC)\r | |
33e7c2ab | 37 | \r |
38 | // Timer control register bit definitions\r | |
39 | #define SP805_WDOG_CTRL_INTEN BIT0\r | |
40 | #define SP805_WDOG_CTRL_RESEN BIT1\r | |
41 | #define SP805_WDOG_RAW_INT_STS_WDOGRIS BIT0\r | |
42 | #define SP805_WDOG_MSK_INT_STS_WDOGMIS BIT0\r | |
43 | \r | |
44 | #define SP805_WDOG_LOCK_IS_UNLOCKED 0x00000000\r | |
45 | #define SP805_WDOG_LOCK_IS_LOCKED 0x00000001\r | |
46 | #define SP805_WDOG_SPECIAL_UNLOCK_CODE 0x1ACCE551\r | |
47 | \r | |
33e7c2ab | 48 | #endif // __SP805_WATCHDOG_H__\r |