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1e57a462 | 1 | /** @file\r |
2 | Serial I/O Port library functions with no library constructor/destructor\r | |
3 | \r | |
4 | Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
9f08a052 | 5 | Copyright (c) 2012 - 2016, ARM Ltd. All rights reserved.<BR>\r |
921e987b | 6 | Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r |
3402aac7 | 7 | \r |
1e57a462 | 8 | This program and the accompanying materials\r |
9 | are licensed and made available under the terms and conditions of the BSD License\r | |
10 | which accompanies this distribution. The full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
12 | \r | |
13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
15 | \r | |
16 | **/\r | |
17 | \r | |
18 | #include <Base.h>\r | |
19 | \r | |
20 | #include <Library/IoLib.h>\r | |
21 | #include <Library/PcdLib.h>\r | |
22 | #include <Library/SerialPortLib.h>\r | |
1e57a462 | 23 | \r |
24 | #include <Drivers/PL011Uart.h>\r | |
25 | \r | |
26 | \r | |
27 | /**\r | |
28 | \r | |
29 | Programmed hardware of Serial port.\r | |
30 | \r | |
31 | @return Always return RETURN_UNSUPPORTED.\r | |
32 | \r | |
33 | **/\r | |
34 | RETURN_STATUS\r | |
35 | EFIAPI\r | |
36 | SerialPortInitialize (\r | |
37 | VOID\r | |
38 | )\r | |
39 | {\r | |
15e277d5 | 40 | UINT64 BaudRate;\r |
41 | UINT32 ReceiveFifoDepth;\r | |
42 | EFI_PARITY_TYPE Parity;\r | |
43 | UINT8 DataBits;\r | |
44 | EFI_STOP_BITS_TYPE StopBits;\r | |
45 | \r | |
aadc64e6 | 46 | BaudRate = (UINTN)FixedPcdGet64 (PcdUartDefaultBaudRate);\r |
9f08a052 | 47 | ReceiveFifoDepth = 0; // Use default FIFO depth\r |
aadc64e6 EL |
48 | Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);\r |
49 | DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);\r | |
50 | StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);\r | |
15e277d5 | 51 | \r |
1e57a462 | 52 | return PL011UartInitializePort (\r |
f6300528 EL |
53 | (UINTN)FixedPcdGet64 (PcdSerialRegisterBase),\r |
54 | FixedPcdGet32 (PL011UartClkInHz),\r | |
55 | &BaudRate,\r | |
56 | &ReceiveFifoDepth,\r | |
57 | &Parity,\r | |
58 | &DataBits,\r | |
59 | &StopBits\r | |
60 | );\r | |
1e57a462 | 61 | }\r |
62 | \r | |
63 | /**\r | |
64 | Write data to serial device.\r | |
65 | \r | |
66 | @param Buffer Point of data buffer which need to be written.\r | |
67 | @param NumberOfBytes Number of output bytes which are cached in Buffer.\r | |
68 | \r | |
69 | @retval 0 Write data failed.\r | |
70 | @retval !0 Actual number of bytes written to serial device.\r | |
71 | \r | |
72 | **/\r | |
73 | UINTN\r | |
74 | EFIAPI\r | |
75 | SerialPortWrite (\r | |
76 | IN UINT8 *Buffer,\r | |
77 | IN UINTN NumberOfBytes\r | |
78 | )\r | |
79 | {\r | |
aadc64e6 | 80 | return PL011UartWrite ((UINTN)FixedPcdGet64 (PcdSerialRegisterBase), Buffer, NumberOfBytes);\r |
1e57a462 | 81 | }\r |
82 | \r | |
83 | /**\r | |
84 | Read data from serial device and save the data in buffer.\r | |
85 | \r | |
86 | @param Buffer Point of data buffer which need to be written.\r | |
87 | @param NumberOfBytes Number of output bytes which are cached in Buffer.\r | |
88 | \r | |
89 | @retval 0 Read data failed.\r | |
90 | @retval !0 Actual number of bytes read from serial device.\r | |
91 | \r | |
92 | **/\r | |
93 | UINTN\r | |
94 | EFIAPI\r | |
95 | SerialPortRead (\r | |
96 | OUT UINT8 *Buffer,\r | |
97 | IN UINTN NumberOfBytes\r | |
98 | )\r | |
99 | {\r | |
aadc64e6 | 100 | return PL011UartRead ((UINTN)FixedPcdGet64 (PcdSerialRegisterBase), Buffer, NumberOfBytes);\r |
1e57a462 | 101 | }\r |
102 | \r | |
103 | /**\r | |
104 | Check to see if any data is available to be read from the debug device.\r | |
105 | \r | |
106 | @retval EFI_SUCCESS At least one byte of data is available to be read\r | |
107 | @retval EFI_NOT_READY No data is available to be read\r | |
108 | @retval EFI_DEVICE_ERROR The serial device is not functioning properly\r | |
109 | \r | |
110 | **/\r | |
111 | BOOLEAN\r | |
112 | EFIAPI\r | |
113 | SerialPortPoll (\r | |
114 | VOID\r | |
115 | )\r | |
116 | {\r | |
aadc64e6 | 117 | return PL011UartPoll ((UINTN)FixedPcdGet64 (PcdSerialRegisterBase));\r |
1e57a462 | 118 | }\r |
921e987b SZ |
119 | /**\r |
120 | Set new attributes to PL011.\r | |
121 | \r | |
9f08a052 EL |
122 | @param BaudRate The baud rate of the serial device. If the\r |
123 | baud rate is not supported, the speed will\r | |
124 | be reduced down to the nearest supported one\r | |
125 | and the variable's value will be updated\r | |
126 | accordingly.\r | |
127 | @param ReceiveFifoDepth The number of characters the device will\r | |
128 | buffer on input. If the specified value is\r | |
129 | not supported, the variable's value will\r | |
130 | be reduced down to the nearest supported one.\r | |
131 | @param Timeout If applicable, the number of microseconds the\r | |
132 | device will wait before timing out a Read or\r | |
133 | a Write operation.\r | |
134 | @param Parity If applicable, this is the EFI_PARITY_TYPE\r | |
135 | that is computed or checked as each character\r | |
136 | is transmitted or received. If the device\r | |
137 | does not support parity, the value is the\r | |
138 | default parity value.\r | |
921e987b | 139 | @param DataBits The number of data bits in each character\r |
9f08a052 EL |
140 | @param StopBits If applicable, the EFI_STOP_BITS_TYPE number\r |
141 | of stop bits per character. If the device\r | |
142 | does not support stop bits, the value is the\r | |
143 | default stop bit value.\r | |
921e987b | 144 | \r |
9f08a052 EL |
145 | @retval EFI_SUCCESS All attributes were set correctly.\r |
146 | @retval EFI_INVALID_PARAMETERS One or more attributes has an unsupported\r | |
147 | value.\r | |
921e987b SZ |
148 | \r |
149 | **/\r | |
150 | RETURN_STATUS\r | |
151 | EFIAPI\r | |
152 | SerialPortSetAttributes (\r | |
153 | IN OUT UINT64 *BaudRate,\r | |
154 | IN OUT UINT32 *ReceiveFifoDepth,\r | |
155 | IN OUT UINT32 *Timeout,\r | |
156 | IN OUT EFI_PARITY_TYPE *Parity,\r | |
157 | IN OUT UINT8 *DataBits,\r | |
158 | IN OUT EFI_STOP_BITS_TYPE *StopBits\r | |
159 | )\r | |
160 | {\r | |
161 | return PL011UartInitializePort (\r | |
f6300528 EL |
162 | (UINTN)FixedPcdGet64 (PcdSerialRegisterBase),\r |
163 | FixedPcdGet32 (PL011UartClkInHz),\r | |
164 | BaudRate,\r | |
165 | ReceiveFifoDepth,\r | |
166 | Parity,\r | |
167 | DataBits,\r | |
168 | StopBits\r | |
169 | );\r | |
921e987b SZ |
170 | }\r |
171 | \r | |
172 | /**\r | |
173 | \r | |
174 | Assert or deassert the control signals on a serial port.\r | |
175 | The following control signals are set according their bit settings :\r | |
176 | . Request to Send\r | |
177 | . Data Terminal Ready\r | |
178 | \r | |
179 | @param[in] Control The following bits are taken into account :\r | |
180 | . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the\r | |
181 | "Request To Send" control signal if this bit is\r | |
182 | equal to one/zero.\r | |
183 | . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert\r | |
184 | the "Data Terminal Ready" control signal if this\r | |
185 | bit is equal to one/zero.\r | |
186 | . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable\r | |
187 | the hardware loopback if this bit is equal to\r | |
188 | one/zero.\r | |
189 | . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.\r | |
190 | . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/\r | |
191 | disable the hardware flow control based on CTS (Clear\r | |
192 | To Send) and RTS (Ready To Send) control signals.\r | |
193 | \r | |
9f08a052 EL |
194 | @retval RETURN_SUCCESS The new control bits were set on the device.\r |
195 | @retval RETURN_UNSUPPORTED The device does not support this operation.\r | |
921e987b SZ |
196 | \r |
197 | **/\r | |
198 | RETURN_STATUS\r | |
199 | EFIAPI\r | |
200 | SerialPortSetControl (\r | |
201 | IN UINT32 Control\r | |
202 | )\r | |
203 | {\r | |
aadc64e6 | 204 | return PL011UartSetControl ((UINTN)FixedPcdGet64 (PcdSerialRegisterBase), Control);\r |
921e987b SZ |
205 | }\r |
206 | \r | |
207 | /**\r | |
1e57a462 | 208 | \r |
921e987b SZ |
209 | Retrieve the status of the control bits on a serial device.\r |
210 | \r | |
211 | @param[out] Control Status of the control bits on a serial device :\r | |
212 | \r | |
9f08a052 EL |
213 | . EFI_SERIAL_DATA_CLEAR_TO_SEND,\r |
214 | EFI_SERIAL_DATA_SET_READY,\r | |
215 | EFI_SERIAL_RING_INDICATE,\r | |
216 | EFI_SERIAL_CARRIER_DETECT,\r | |
217 | EFI_SERIAL_REQUEST_TO_SEND,\r | |
218 | EFI_SERIAL_DATA_TERMINAL_READY\r | |
219 | are all related to the DTE (Data Terminal Equipment)\r | |
220 | and DCE (Data Communication Equipment) modes of\r | |
221 | operation of the serial device.\r | |
222 | . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the\r | |
223 | receive buffer is empty, 0 otherwise.\r | |
224 | . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the\r | |
225 | transmit buffer is empty, 0 otherwise.\r | |
226 | . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if\r | |
227 | the hardware loopback is enabled (the output feeds\r | |
228 | the receive buffer), 0 otherwise.\r | |
229 | . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one\r | |
230 | if a loopback is accomplished by software, else 0.\r | |
231 | . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to\r | |
232 | one if the hardware flow control based on CTS (Clear\r | |
233 | To Send) and RTS (Ready To Send) control signals is\r | |
234 | enabled, 0 otherwise.\r | |
235 | \r | |
236 | @retval RETURN_SUCCESS The control bits were read from the device.\r | |
921e987b SZ |
237 | \r |
238 | **/\r | |
239 | RETURN_STATUS\r | |
240 | EFIAPI\r | |
241 | SerialPortGetControl (\r | |
242 | OUT UINT32 *Control\r | |
243 | )\r | |
244 | {\r | |
aadc64e6 | 245 | return PL011UartGetControl ((UINTN)FixedPcdGet64 (PcdSerialRegisterBase), Control);\r |
921e987b | 246 | }\r |