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b1b69d26 | 1 | /** @file\r |
27f9f349 | 2 | \r |
b1b69d26 | 3 | Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>\r |
27f9f349 AB |
4 | \r |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | #include <Library/DebugLib.h>\r | |
15 | #include <Library/IoLib.h>\r | |
16 | #include <Library/LcdHwLib.h>\r | |
17 | #include <Library/LcdPlatformLib.h>\r | |
18 | #include <Library/MemoryAllocationLib.h>\r | |
19 | \r | |
20 | #include "PL111Lcd.h"\r | |
21 | \r | |
b1b69d26 GP |
22 | /** This file contains all the bits of the PL111 that are\r |
23 | platform independent.\r | |
27f9f349 | 24 | \r |
b1b69d26 | 25 | **/\r |
27f9f349 AB |
26 | EFI_STATUS\r |
27 | LcdIdentify (\r | |
28 | VOID\r | |
29 | )\r | |
30 | {\r | |
31 | DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL111\n",\r | |
32 | PL111_REG_CLCD_PERIPH_ID_0));\r | |
33 | \r | |
34 | // Check if this is a PL111\r | |
35 | if (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0 &&\r | |
36 | MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1 &&\r | |
37 | (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2 &&\r | |
38 | MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3 &&\r | |
39 | MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0 &&\r | |
40 | MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1 &&\r | |
41 | MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2 &&\r | |
42 | MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3) {\r | |
43 | return EFI_SUCCESS;\r | |
44 | }\r | |
45 | return EFI_NOT_FOUND;\r | |
46 | }\r | |
47 | \r | |
48 | EFI_STATUS\r | |
49 | LcdInitialize (\r | |
50 | IN EFI_PHYSICAL_ADDRESS VramBaseAddress\r | |
51 | )\r | |
52 | {\r | |
53 | // Define start of the VRAM. This never changes for any graphics mode\r | |
b1b69d26 GP |
54 | MmioWrite32 (PL111_REG_LCD_UP_BASE, (UINT32)VramBaseAddress);\r |
55 | MmioWrite32 (PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer\r | |
27f9f349 AB |
56 | \r |
57 | // Disable all interrupts from the PL111\r | |
b1b69d26 | 58 | MmioWrite32 (PL111_REG_LCD_IMSC, 0);\r |
27f9f349 AB |
59 | \r |
60 | return EFI_SUCCESS;\r | |
61 | }\r | |
62 | \r | |
63 | EFI_STATUS\r | |
64 | LcdSetMode (\r | |
65 | IN UINT32 ModeNumber\r | |
66 | )\r | |
67 | {\r | |
68 | EFI_STATUS Status;\r | |
69 | UINT32 HRes;\r | |
70 | UINT32 HSync;\r | |
71 | UINT32 HBackPorch;\r | |
72 | UINT32 HFrontPorch;\r | |
73 | UINT32 VRes;\r | |
74 | UINT32 VSync;\r | |
75 | UINT32 VBackPorch;\r | |
76 | UINT32 VFrontPorch;\r | |
77 | UINT32 LcdControl;\r | |
78 | LCD_BPP LcdBpp;\r | |
79 | \r | |
80 | // Set the video mode timings and other relevant information\r | |
b1b69d26 GP |
81 | Status = LcdPlatformGetTimings (\r |
82 | ModeNumber,\r | |
83 | &HRes,\r | |
84 | &HSync,\r | |
85 | &HBackPorch,\r | |
86 | &HFrontPorch,\r | |
87 | &VRes,\r | |
88 | &VSync,\r | |
89 | &VBackPorch,\r | |
90 | &VFrontPorch\r | |
91 | );\r | |
27f9f349 | 92 | ASSERT_EFI_ERROR (Status);\r |
b1b69d26 | 93 | if (EFI_ERROR (Status)) {\r |
27f9f349 AB |
94 | return EFI_DEVICE_ERROR;\r |
95 | }\r | |
96 | \r | |
b1b69d26 | 97 | Status = LcdPlatformGetBpp (ModeNumber, &LcdBpp);\r |
27f9f349 | 98 | ASSERT_EFI_ERROR (Status);\r |
b1b69d26 | 99 | if (EFI_ERROR (Status)) {\r |
27f9f349 AB |
100 | return EFI_DEVICE_ERROR;\r |
101 | }\r | |
102 | \r | |
103 | // Disable the CLCD_LcdEn bit\r | |
b1b69d26 GP |
104 | LcdControl = MmioRead32 (PL111_REG_LCD_CONTROL);\r |
105 | MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl & ~1);\r | |
27f9f349 AB |
106 | \r |
107 | // Set Timings\r | |
b1b69d26 GP |
108 | MmioWrite32 (\r |
109 | PL111_REG_LCD_TIMING_0,\r | |
110 | HOR_AXIS_PANEL (HBackPorch, HFrontPorch, HSync, HRes)\r | |
111 | );\r | |
112 | \r | |
113 | MmioWrite32 (\r | |
114 | PL111_REG_LCD_TIMING_1,\r | |
115 | VER_AXIS_PANEL (VBackPorch, VFrontPorch, VSync, VRes)\r | |
116 | );\r | |
117 | \r | |
118 | MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY (HRes));\r | |
27f9f349 AB |
119 | MmioWrite32 (PL111_REG_LCD_TIMING_3, 0);\r |
120 | \r | |
121 | // PL111_REG_LCD_CONTROL\r | |
b1b69d26 GP |
122 | LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP (LcdBpp) |\r |
123 | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR;\r | |
124 | MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl);\r | |
27f9f349 AB |
125 | \r |
126 | // Turn on power to the LCD Panel\r | |
127 | LcdControl |= PL111_CTRL_LCD_PWR;\r | |
b1b69d26 | 128 | MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl);\r |
27f9f349 AB |
129 | \r |
130 | return EFI_SUCCESS;\r | |
131 | }\r | |
132 | \r | |
133 | VOID\r | |
134 | LcdShutdown (\r | |
135 | VOID\r | |
136 | )\r | |
137 | {\r | |
138 | // Disable the controller\r | |
139 | MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN);\r | |
140 | }\r |