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b1b69d26 | 1 | /** @file\r |
4257dfaa | 2 | This file contains the platform independent parts of PL111Lcd\r |
27f9f349 | 3 | \r |
b1b69d26 | 4 | Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>\r |
27f9f349 AB |
5 | \r |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | #include <Library/DebugLib.h>\r | |
16 | #include <Library/IoLib.h>\r | |
17 | #include <Library/LcdHwLib.h>\r | |
18 | #include <Library/LcdPlatformLib.h>\r | |
19 | #include <Library/MemoryAllocationLib.h>\r | |
20 | \r | |
21 | #include "PL111Lcd.h"\r | |
22 | \r | |
4257dfaa | 23 | /** Check for presence of PL111.\r |
27f9f349 | 24 | \r |
4257dfaa GP |
25 | @retval EFI_SUCCESS Returns success if platform implements a\r |
26 | PL111 controller.\r | |
27 | \r | |
28 | @retval EFI_NOT_FOUND PL111 display controller not found the plaform.\r | |
b1b69d26 | 29 | **/\r |
27f9f349 AB |
30 | EFI_STATUS\r |
31 | LcdIdentify (\r | |
32 | VOID\r | |
33 | )\r | |
34 | {\r | |
35 | DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL111\n",\r | |
36 | PL111_REG_CLCD_PERIPH_ID_0));\r | |
37 | \r | |
38 | // Check if this is a PL111\r | |
39 | if (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0 &&\r | |
40 | MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1 &&\r | |
41 | (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2 &&\r | |
42 | MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3 &&\r | |
43 | MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0 &&\r | |
44 | MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1 &&\r | |
45 | MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2 &&\r | |
46 | MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3) {\r | |
47 | return EFI_SUCCESS;\r | |
48 | }\r | |
49 | return EFI_NOT_FOUND;\r | |
50 | }\r | |
51 | \r | |
4257dfaa GP |
52 | /** Initialize display.\r |
53 | \r | |
54 | @param[in] VramBaseAddress Address of the framebuffer.\r | |
55 | \r | |
56 | @retval EFI_SUCCESS Initialization of display successful.\r | |
57 | **/\r | |
27f9f349 AB |
58 | EFI_STATUS\r |
59 | LcdInitialize (\r | |
60 | IN EFI_PHYSICAL_ADDRESS VramBaseAddress\r | |
61 | )\r | |
62 | {\r | |
63 | // Define start of the VRAM. This never changes for any graphics mode\r | |
b1b69d26 GP |
64 | MmioWrite32 (PL111_REG_LCD_UP_BASE, (UINT32)VramBaseAddress);\r |
65 | MmioWrite32 (PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer\r | |
27f9f349 AB |
66 | \r |
67 | // Disable all interrupts from the PL111\r | |
b1b69d26 | 68 | MmioWrite32 (PL111_REG_LCD_IMSC, 0);\r |
27f9f349 AB |
69 | \r |
70 | return EFI_SUCCESS;\r | |
71 | }\r | |
72 | \r | |
4257dfaa GP |
73 | /** Set requested mode of the display.\r |
74 | \r | |
75 | @param[in] ModeNumbe Display mode number.\r | |
76 | \r | |
77 | @retval EFI_SUCCESS Display mode set successfuly.\r | |
3da4193b GP |
78 | @retval !(EFI_SUCCESS) Other errors.\r |
79 | \r | |
4257dfaa | 80 | **/\r |
27f9f349 AB |
81 | EFI_STATUS\r |
82 | LcdSetMode (\r | |
83 | IN UINT32 ModeNumber\r | |
84 | )\r | |
85 | {\r | |
86 | EFI_STATUS Status;\r | |
87 | UINT32 HRes;\r | |
88 | UINT32 HSync;\r | |
89 | UINT32 HBackPorch;\r | |
90 | UINT32 HFrontPorch;\r | |
91 | UINT32 VRes;\r | |
92 | UINT32 VSync;\r | |
93 | UINT32 VBackPorch;\r | |
94 | UINT32 VFrontPorch;\r | |
95 | UINT32 LcdControl;\r | |
96 | LCD_BPP LcdBpp;\r | |
97 | \r | |
98 | // Set the video mode timings and other relevant information\r | |
b1b69d26 GP |
99 | Status = LcdPlatformGetTimings (\r |
100 | ModeNumber,\r | |
101 | &HRes,\r | |
102 | &HSync,\r | |
103 | &HBackPorch,\r | |
104 | &HFrontPorch,\r | |
105 | &VRes,\r | |
106 | &VSync,\r | |
107 | &VBackPorch,\r | |
108 | &VFrontPorch\r | |
109 | );\r | |
b1b69d26 | 110 | if (EFI_ERROR (Status)) {\r |
3da4193b GP |
111 | ASSERT_EFI_ERROR (Status);\r |
112 | return Status;\r | |
27f9f349 AB |
113 | }\r |
114 | \r | |
b1b69d26 | 115 | Status = LcdPlatformGetBpp (ModeNumber, &LcdBpp);\r |
b1b69d26 | 116 | if (EFI_ERROR (Status)) {\r |
3da4193b GP |
117 | ASSERT_EFI_ERROR (Status);\r |
118 | return Status;\r | |
27f9f349 AB |
119 | }\r |
120 | \r | |
121 | // Disable the CLCD_LcdEn bit\r | |
d1ee57e5 | 122 | MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN);\r |
27f9f349 AB |
123 | \r |
124 | // Set Timings\r | |
b1b69d26 GP |
125 | MmioWrite32 (\r |
126 | PL111_REG_LCD_TIMING_0,\r | |
127 | HOR_AXIS_PANEL (HBackPorch, HFrontPorch, HSync, HRes)\r | |
128 | );\r | |
129 | \r | |
130 | MmioWrite32 (\r | |
131 | PL111_REG_LCD_TIMING_1,\r | |
132 | VER_AXIS_PANEL (VBackPorch, VFrontPorch, VSync, VRes)\r | |
133 | );\r | |
134 | \r | |
135 | MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY (HRes));\r | |
27f9f349 AB |
136 | MmioWrite32 (PL111_REG_LCD_TIMING_3, 0);\r |
137 | \r | |
138 | // PL111_REG_LCD_CONTROL\r | |
b1b69d26 | 139 | LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP (LcdBpp) |\r |
b5daabdc | 140 | PL111_CTRL_LCD_TFT | PL111_CTRL_LCD_PWR | PL111_CTRL_BGR;\r |
b1b69d26 | 141 | MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl);\r |
27f9f349 AB |
142 | \r |
143 | return EFI_SUCCESS;\r | |
144 | }\r | |
145 | \r | |
4257dfaa GP |
146 | /** De-initializes the display.\r |
147 | */\r | |
27f9f349 AB |
148 | VOID\r |
149 | LcdShutdown (\r | |
150 | VOID\r | |
151 | )\r | |
152 | {\r | |
153 | // Disable the controller\r | |
154 | MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN);\r | |
155 | }\r |