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1 | /** @file PL111Lcd.h\r |
2 | \r | |
3 | Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r | |
4 | This program and the accompanying materials\r | |
5 | are licensed and made available under the terms and conditions of the BSD License\r | |
6 | which accompanies this distribution. The full text of the license may be found at\r | |
7 | http://opensource.org/licenses/bsd-license.php\r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | \r | |
12 | **/\r | |
13 | \r | |
14 | #ifndef _PL111LCD_H__\r | |
15 | #define _PL111LCD_H__\r | |
16 | \r | |
17 | /**********************************************************************\r | |
18 | *\r | |
19 | * This header file contains all the bits of the PL111 that are\r | |
20 | * platform independent.\r | |
21 | *\r | |
22 | **********************************************************************/\r | |
23 | \r | |
24 | // Controller Register Offsets\r | |
25 | #define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)\r | |
26 | #define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)\r | |
27 | #define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)\r | |
28 | #define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)\r | |
29 | #define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)\r | |
30 | #define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)\r | |
31 | #define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)\r | |
32 | #define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)\r | |
33 | #define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)\r | |
34 | #define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)\r | |
35 | #define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)\r | |
36 | #define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)\r | |
37 | #define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)\r | |
38 | #define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)\r | |
39 | \r | |
40 | // Identification Register Offsets\r | |
41 | #define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)\r | |
42 | #define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)\r | |
43 | #define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)\r | |
44 | #define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)\r | |
45 | #define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)\r | |
46 | #define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)\r | |
47 | #define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)\r | |
48 | #define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)\r | |
49 | \r | |
50 | #define PL111_CLCD_PERIPH_ID_0 0x11\r | |
51 | #define PL111_CLCD_PERIPH_ID_1 0x11\r | |
52 | #define PL111_CLCD_PERIPH_ID_2 0x04\r | |
53 | #define PL111_CLCD_PERIPH_ID_3 0x00\r | |
54 | #define PL111_CLCD_P_CELL_ID_0 0x0D\r | |
55 | #define PL111_CLCD_P_CELL_ID_1 0xF0\r | |
56 | #define PL111_CLCD_P_CELL_ID_2 0x05\r | |
57 | #define PL111_CLCD_P_CELL_ID_3 0xB1\r | |
58 | \r | |
59 | /**********************************************************************/\r | |
60 | \r | |
61 | // Register components (register bits)\r | |
62 | \r | |
63 | // This should make life easier to program specific settings in the different registers\r | |
64 | // by simplifying the setting up of the individual bits of each register\r | |
65 | // and then assembling the final register value.\r | |
66 | \r | |
67 | /**********************************************************************/\r | |
68 | \r | |
69 | // Register: PL111_REG_LCD_TIMING_0\r | |
70 | #define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))\r | |
71 | \r | |
72 | // Register: PL111_REG_LCD_TIMING_1\r | |
73 | #define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))\r | |
74 | \r | |
75 | // Register: PL111_REG_LCD_TIMING_2\r | |
76 | #define PL111_BIT_SHIFT_PCD_HI 27\r | |
77 | #define PL111_BIT_SHIFT_BCD 26\r | |
78 | #define PL111_BIT_SHIFT_CPL 16\r | |
79 | #define PL111_BIT_SHIFT_IOE 14\r | |
80 | #define PL111_BIT_SHIFT_IPC 13\r | |
81 | #define PL111_BIT_SHIFT_IHS 12\r | |
82 | #define PL111_BIT_SHIFT_IVS 11\r | |
83 | #define PL111_BIT_SHIFT_ACB 6\r | |
84 | #define PL111_BIT_SHIFT_CLKSEL 5\r | |
85 | #define PL111_BIT_SHIFT_PCD_LO 0\r | |
86 | \r | |
87 | #define PL111_BCD (1 << 26)\r | |
88 | #define PL111_IPC (1 << 13)\r | |
89 | #define PL111_IHS (1 << 12)\r | |
90 | #define PL111_IVS (1 << 11)\r | |
91 | \r | |
92 | #define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))\r | |
93 | \r | |
94 | // Register: PL111_REG_LCD_TIMING_3\r | |
95 | #define PL111_BIT_SHIFT_LEE 16\r | |
96 | #define PL111_BIT_SHIFT_LED 0\r | |
97 | \r | |
98 | #define PL111_CTRL_WATERMARK (1 << 16)\r | |
99 | #define PL111_CTRL_LCD_V_COMP (1 << 12)\r | |
100 | #define PL111_CTRL_LCD_PWR (1 << 11)\r | |
101 | #define PL111_CTRL_BEPO (1 << 10)\r | |
102 | #define PL111_CTRL_BEBO (1 << 9)\r | |
103 | #define PL111_CTRL_BGR (1 << 8)\r | |
104 | #define PL111_CTRL_LCD_DUAL (1 << 7)\r | |
105 | #define PL111_CTRL_LCD_MONO_8 (1 << 6)\r | |
106 | #define PL111_CTRL_LCD_TFT (1 << 5)\r | |
107 | #define PL111_CTRL_LCD_BW (1 << 4)\r | |
108 | #define PL111_CTRL_LCD_1BPP (0 << 1)\r | |
109 | #define PL111_CTRL_LCD_2BPP (1 << 1)\r | |
110 | #define PL111_CTRL_LCD_4BPP (2 << 1)\r | |
111 | #define PL111_CTRL_LCD_8BPP (3 << 1)\r | |
112 | #define PL111_CTRL_LCD_16BPP (4 << 1)\r | |
113 | #define PL111_CTRL_LCD_24BPP (5 << 1)\r | |
114 | #define PL111_CTRL_LCD_16BPP_565 (6 << 1)\r | |
115 | #define PL111_CTRL_LCD_12BPP_444 (7 << 1)\r | |
116 | #define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1)\r | |
117 | #define PL111_CTRL_LCD_EN 1\r | |
118 | \r | |
119 | /**********************************************************************/\r | |
120 | \r | |
121 | // Register: PL111_REG_LCD_TIMING_0\r | |
122 | #define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24)\r | |
123 | #define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16)\r | |
124 | #define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8)\r | |
125 | #define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)\r | |
126 | \r | |
127 | // Register: PL111_REG_LCD_TIMING_1\r | |
128 | #define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24)\r | |
129 | #define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16)\r | |
130 | #define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10)\r | |
131 | #define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC)\r | |
132 | \r | |
133 | // Register: PL111_REG_LCD_TIMING_2\r | |
134 | #define PL111_BIT_MASK_PCD_HI 0xF8000000\r | |
135 | #define PL111_BIT_MASK_BCD 0x04000000\r | |
136 | #define PL111_BIT_MASK_CPL 0x03FF0000\r | |
137 | #define PL111_BIT_MASK_IOE 0x00004000\r | |
138 | #define PL111_BIT_MASK_IPC 0x00002000\r | |
139 | #define PL111_BIT_MASK_IHS 0x00001000\r | |
140 | #define PL111_BIT_MASK_IVS 0x00000800\r | |
141 | #define PL111_BIT_MASK_ACB 0x000007C0\r | |
142 | #define PL111_BIT_MASK_CLKSEL 0x00000020\r | |
143 | #define PL111_BIT_MASK_PCD_LO 0x0000001F\r | |
144 | \r | |
145 | // Register: PL111_REG_LCD_TIMING_3\r | |
146 | #define PL111_BIT_MASK_LEE 0x00010000\r | |
147 | #define PL111_BIT_MASK_LED 0x0000007F\r | |
148 | \r | |
149 | #endif /* _PL111LCD_H__ */\r |