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1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
ec6b8eda OM |
4 | Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
5 | \r | |
1e57a462 | 6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include <Base.h>\r | |
17 | \r | |
18 | #include <Library/BaseLib.h>\r | |
19 | #include <Library/TimerLib.h>\r | |
20 | #include <Library/DebugLib.h>\r | |
21 | #include <Library/PcdLib.h>\r | |
22 | #include <Library/IoLib.h>\r | |
23 | #include <Drivers/SP804Timer.h>\r | |
24 | \r | |
25 | #define SP804_TIMER_METRONOME_BASE ((UINTN)PcdGet32 (PcdSP804TimerMetronomeBase))\r | |
26 | #define SP804_TIMER_PERFORMANCE_BASE ((UINTN)PcdGet32 (PcdSP804TimerPerformanceBase))\r | |
27 | \r | |
28 | // Setup SP810's Timer2 for managing delay functions. And Timer3 for Performance counter\r | |
29 | // Note: ArmVE's Timer0 and Timer1 are used by TimerDxe.\r | |
30 | RETURN_STATUS\r | |
31 | EFIAPI\r | |
32 | TimerConstructor (\r | |
33 | VOID\r | |
34 | )\r | |
35 | {\r | |
36 | // Check if the Metronome Timer is already initialized\r | |
ec6b8eda | 37 | if ((MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) == 0) {\r |
1e57a462 | 38 | // Configure the Metronome Timer for free running operation, 32 bits, no prescaler, and interrupt disabled\r |
39 | MmioWrite32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);\r | |
40 | \r | |
41 | // Start the Metronome Timer ticking\r | |
42 | MmioOr32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);\r | |
43 | }\r | |
44 | \r | |
45 | // Check if the Performance Timer is already initialized\r | |
ec6b8eda | 46 | if ((MmioRead32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) == 0) {\r |
1e57a462 | 47 | // Configure the Performance timer for free running operation, 32 bits, no prescaler, interrupt disabled\r |
48 | MmioWrite32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);\r | |
49 | \r | |
50 | // Start the Performance Timer ticking\r | |
51 | MmioOr32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);\r | |
52 | }\r | |
53 | \r | |
54 | return RETURN_SUCCESS;\r | |
55 | }\r | |
56 | \r | |
57 | /**\r | |
58 | Stalls the CPU for at least the given number of microseconds.\r | |
59 | \r | |
60 | Stalls the CPU for the number of microseconds specified by MicroSeconds.\r | |
61 | The hardware timer is 32 bits.\r | |
62 | The maximum possible delay is (0xFFFFFFFF / TimerFrequencyMHz), i.e. ([32bits] / FreqInMHz)\r | |
63 | For example:\r | |
64 | +----------------+------------+----------+----------+\r | |
65 | | TimerFrequency | MaxDelay | MaxDelay | MaxDelay |\r | |
66 | | (MHz) | (us) | (s) | (min) |\r | |
67 | +----------------+------------+----------+----------+\r | |
68 | | 1 | 0xFFFFFFFF | 4294 | 71.5 |\r | |
69 | | 5 | 0x33333333 | 859 | 14.3 |\r | |
70 | | 10 | 0x19999999 | 429 | 7.2 |\r | |
71 | | 50 | 0x051EB851 | 86 | 1.4 |\r | |
72 | +----------------+------------+----------+----------+\r | |
73 | If it becomes necessary to support higher delays, then consider using the\r | |
74 | real time clock.\r | |
75 | \r | |
76 | During this delay, the cpu is not yielded to any other process, with one exception:\r | |
77 | events that are triggered off a timer and which execute at a higher TPL than\r | |
78 | this function. These events may call MicroSecondDelay (or NanoSecondDelay) to\r | |
79 | fulfil their own needs.\r | |
80 | Therefore, this function must be re-entrant, as it may be interrupted and re-started.\r | |
81 | \r | |
82 | @param MicroSeconds The minimum number of microseconds to delay.\r | |
83 | \r | |
84 | @return The value of MicroSeconds inputted.\r | |
85 | \r | |
86 | **/\r | |
87 | UINTN\r | |
88 | EFIAPI\r | |
89 | MicroSecondDelay (\r | |
90 | IN UINTN MicroSeconds\r | |
91 | )\r | |
92 | {\r | |
93 | UINT64 DelayTicks64; // Convert from microseconds to timer ticks, more bits to detect over-range conditions.\r | |
94 | UINTN DelayTicks; // Convert from microseconds to timer ticks, native size for general calculations.\r | |
95 | UINTN StartTicks; // Timer value snapshot at the start of the delay\r | |
96 | UINTN TargetTicks; // Timer value to signal the end of the delay\r | |
97 | UINTN CurrentTicks; // Current value of the 64-bit timer value at any given moment\r | |
98 | \r | |
99 | // If we snapshot the timer at the start of the delay function then we minimise unaccounted overheads.\r | |
100 | StartTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG);\r | |
101 | \r | |
102 | // We are operating at the limit of 32bits. For the range checking work in 64 bits to avoid overflows.\r | |
103 | DelayTicks64 = MultU64x32((UINT64)MicroSeconds, PcdGet32(PcdSP804TimerFrequencyInMHz));\r | |
104 | \r | |
105 | // We are limited to 32 bits.\r | |
106 | // If the specified delay is exactly equal to the max range of the timer,\r | |
107 | // then the start will be equal to the stop plus one timer overflow (wrap-around).\r | |
108 | // To avoid having to check for that, reduce the maximum acceptable range by 1 tick,\r | |
109 | // i.e. reject delays equal or greater than the max range of the timer.\r | |
110 | if (DelayTicks64 >= (UINT64)SP804_MAX_TICKS) {\r | |
111 | DEBUG((EFI_D_ERROR,"MicroSecondDelay: ERROR: MicroSeconds=%d exceed SP804 count range. Max MicroSeconds=%d\n",\r | |
112 | MicroSeconds,\r | |
113 | ((UINTN)SP804_MAX_TICKS/PcdGet32(PcdSP804TimerFrequencyInMHz))));\r | |
114 | }\r | |
115 | ASSERT(DelayTicks64 < (UINT64)SP804_MAX_TICKS);\r | |
116 | \r | |
117 | // From now on do calculations only in native bit size.\r | |
118 | DelayTicks = (UINTN)DelayTicks64;\r | |
119 | \r | |
120 | // Calculate the target value of the timer.\r | |
121 | \r | |
122 | //Note: SP804 timer is counting down\r | |
123 | if (StartTicks >= DelayTicks) {\r | |
124 | // In this case we do not expect a wrap-around of the timer to occur.\r | |
125 | // CurrentTicks must be less than StartTicks and higher than TargetTicks.\r | |
126 | // If this is not the case, then the delay has been reached and may even have been exceeded if this\r | |
127 | // function was suspended by a higher priority interrupt.\r | |
128 | \r | |
129 | TargetTicks = StartTicks - DelayTicks;\r | |
130 | \r | |
131 | do {\r | |
132 | CurrentTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG);\r | |
133 | } while ((CurrentTicks > TargetTicks) && (CurrentTicks <= StartTicks));\r | |
134 | \r | |
135 | } else {\r | |
136 | // In this case TargetTicks is larger than StartTicks.\r | |
137 | // This means we expect a wrap-around of the timer to occur and we must wait for it.\r | |
138 | // Before the wrap-around, CurrentTicks must be less than StartTicks and less than TargetTicks.\r | |
139 | // After the wrap-around, CurrentTicks must be larger than StartTicks and larger than TargetTicks.\r | |
140 | // If this is not the case, then the delay has been reached and may even have been exceeded if this\r | |
141 | // function was suspended by a higher priority interrupt.\r | |
142 | \r | |
143 | // The order of operations is essential to avoid arithmetic overflow problems\r | |
144 | TargetTicks = ((UINTN)SP804_MAX_TICKS - DelayTicks) + StartTicks;\r | |
145 | \r | |
146 | // First wait for the wrap-around to occur\r | |
147 | do {\r | |
148 | CurrentTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG);\r | |
149 | } while (CurrentTicks <= StartTicks);\r | |
150 | \r | |
151 | // Then wait for the target\r | |
152 | do {\r | |
153 | CurrentTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG);\r | |
154 | } while (CurrentTicks > TargetTicks);\r | |
155 | }\r | |
156 | \r | |
157 | return MicroSeconds;\r | |
158 | }\r | |
159 | \r | |
160 | /**\r | |
161 | Stalls the CPU for at least the given number of nanoseconds.\r | |
162 | \r | |
163 | Stalls the CPU for the number of nanoseconds specified by NanoSeconds.\r | |
164 | \r | |
165 | When the timer frequency is 1MHz, each tick corresponds to 1 microsecond.\r | |
166 | Therefore, the nanosecond delay will be rounded up to the nearest 1 microsecond.\r | |
167 | \r | |
168 | @param NanoSeconds The minimum number of nanoseconds to delay.\r | |
169 | \r | |
170 | @return The value of NanoSeconds inputted.\r | |
171 | \r | |
172 | **/\r | |
173 | UINTN\r | |
174 | EFIAPI\r | |
175 | NanoSecondDelay (\r | |
176 | IN UINTN NanoSeconds\r | |
177 | )\r | |
178 | {\r | |
179 | UINTN MicroSeconds;\r | |
180 | \r | |
181 | // Round up to 1us Tick Number\r | |
182 | MicroSeconds = NanoSeconds / 1000;\r | |
183 | MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1;\r | |
184 | \r | |
185 | MicroSecondDelay (MicroSeconds);\r | |
186 | \r | |
187 | return NanoSeconds;\r | |
188 | }\r | |
189 | \r | |
190 | /**\r | |
191 | Retrieves the current value of a 64-bit free running performance counter.\r | |
192 | \r | |
193 | The counter can either count up by 1 or count down by 1. If the physical\r | |
194 | performance counter counts by a larger increment, then the counter values\r | |
195 | must be translated. The properties of the counter can be retrieved from\r | |
196 | GetPerformanceCounterProperties().\r | |
197 | \r | |
198 | @return The current value of the free running performance counter.\r | |
199 | \r | |
200 | **/\r | |
201 | UINT64\r | |
202 | EFIAPI\r | |
203 | GetPerformanceCounter (\r | |
204 | VOID\r | |
205 | )\r | |
3402aac7 | 206 | {\r |
1e57a462 | 207 | // Free running 64-bit/32-bit counter is needed here.\r |
208 | // Don't think we need this to boot, just to do performance profile\r | |
209 | UINT64 Value;\r | |
210 | Value = MmioRead32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CURRENT_REG);\r | |
211 | return Value;\r | |
212 | }\r | |
213 | \r | |
214 | \r | |
215 | /**\r | |
216 | Retrieves the 64-bit frequency in Hz and the range of performance counter\r | |
217 | values.\r | |
218 | \r | |
219 | If StartValue is not NULL, then the value that the performance counter starts\r | |
220 | with immediately after is it rolls over is returned in StartValue. If\r | |
221 | EndValue is not NULL, then the value that the performance counter end with\r | |
222 | immediately before it rolls over is returned in EndValue. The 64-bit\r | |
223 | frequency of the performance counter in Hz is always returned. If StartValue\r | |
224 | is less than EndValue, then the performance counter counts up. If StartValue\r | |
225 | is greater than EndValue, then the performance counter counts down. For\r | |
226 | example, a 64-bit free running counter that counts up would have a StartValue\r | |
227 | of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter\r | |
228 | that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.\r | |
229 | \r | |
230 | @param StartValue The value the performance counter starts with when it\r | |
231 | rolls over.\r | |
232 | @param EndValue The value that the performance counter ends with before\r | |
233 | it rolls over.\r | |
234 | \r | |
235 | @return The frequency in Hz.\r | |
236 | \r | |
237 | **/\r | |
238 | UINT64\r | |
239 | EFIAPI\r | |
240 | GetPerformanceCounterProperties (\r | |
241 | OUT UINT64 *StartValue, OPTIONAL\r | |
242 | OUT UINT64 *EndValue OPTIONAL\r | |
243 | )\r | |
244 | {\r | |
245 | if (StartValue != NULL) {\r | |
246 | // Timer starts with the reload value\r | |
247 | *StartValue = 0xFFFFFFFF;\r | |
248 | }\r | |
3402aac7 | 249 | \r |
1e57a462 | 250 | if (EndValue != NULL) {\r |
251 | // Timer counts down to 0x0\r | |
252 | *EndValue = (UINT64)0ULL;\r | |
253 | }\r | |
3402aac7 | 254 | \r |
1e57a462 | 255 | return PcdGet64 (PcdEmbeddedPerformanceCounterFrequencyInHz);\r |
256 | }\r |