projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 1bc83266 | 1 | #\r |
| eaa84fd5 | 2 | # Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
| 1bc83266 | 3 | #\r |
| f4dfad05 | 4 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 1bc83266 HL |
5 | #\r |
| 6 | #\r | |
| 7 | \r | |
| d855b261 | 8 | #include <Chipset/AArch64.h>\r |
| 1bc83266 HL |
9 | #include <AsmMacroIoLibV8.h>\r |
| 10 | #include <Base.h>\r | |
| 11 | #include <AutoGen.h>\r | |
| 12 | \r | |
| 13 | .text\r | |
| 1bc83266 HL |
14 | \r |
| 15 | //============================================================\r | |
| 16 | //Default Exception Handlers\r | |
| 17 | //============================================================\r | |
| 18 | \r | |
| 1bc83266 HL |
19 | #define TO_HANDLER \\r |
| 20 | EL1_OR_EL2(x1) \\r | |
| 21 | 1: mrs x1, elr_el1 /* EL1 Exception Link Register */ ;\\r | |
| 22 | b 3f ;\\r | |
| 23 | 2: mrs x1, elr_el2 /* EL2 Exception Link Register */ ;\\r | |
| 24 | 3: bl ASM_PFX(PeiCommonExceptionEntry) ;\r | |
| 25 | \r | |
| 26 | \r | |
| 27 | //\r | |
| 28 | // Default Exception handlers: There is no plan to return from any of these exceptions.\r | |
| 29 | // No context saving at all.\r | |
| 30 | //\r | |
| 31 | \r | |
| d855b261 MR |
32 | VECTOR_BASE(PeiVectorTable)\r |
| 33 | \r | |
| 34 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SYNC)\r | |
| 1bc83266 HL |
35 | _DefaultSyncExceptHandler_t:\r |
| 36 | mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r | |
| 37 | TO_HANDLER\r | |
| 38 | \r | |
| d855b261 | 39 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_IRQ)\r |
| 1bc83266 HL |
40 | _DefaultIrq_t:\r |
| 41 | mov x0, #EXCEPT_AARCH64_IRQ\r | |
| 42 | TO_HANDLER\r | |
| 43 | \r | |
| d855b261 | 44 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_FIQ)\r |
| 1bc83266 HL |
45 | _DefaultFiq_t:\r |
| 46 | mov x0, #EXCEPT_AARCH64_FIQ\r | |
| 47 | TO_HANDLER\r | |
| 48 | \r | |
| d855b261 | 49 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SERR)\r |
| 1bc83266 HL |
50 | _DefaultSError_t:\r |
| 51 | mov x0, #EXCEPT_AARCH64_SERROR\r | |
| 52 | TO_HANDLER\r | |
| 53 | \r | |
| d855b261 | 54 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SYNC)\r |
| 1bc83266 HL |
55 | _DefaultSyncExceptHandler_h:\r |
| 56 | mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r | |
| 57 | TO_HANDLER\r | |
| 58 | \r | |
| d855b261 | 59 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_IRQ)\r |
| 1bc83266 HL |
60 | _DefaultIrq_h:\r |
| 61 | mov x0, #EXCEPT_AARCH64_IRQ\r | |
| 62 | TO_HANDLER\r | |
| 63 | \r | |
| d855b261 | 64 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_FIQ)\r |
| 1bc83266 HL |
65 | _DefaultFiq_h:\r |
| 66 | mov x0, #EXCEPT_AARCH64_FIQ\r | |
| 67 | TO_HANDLER\r | |
| 68 | \r | |
| d855b261 | 69 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SERR)\r |
| 1bc83266 HL |
70 | _DefaultSError_h:\r |
| 71 | mov x0, #EXCEPT_AARCH64_SERROR\r | |
| 72 | TO_HANDLER\r | |
| d855b261 | 73 | \r |
| 83886d74 AB |
74 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SYNC)\r |
| 75 | _DefaultSyncExceptHandler_LowerA64:\r | |
| 76 | mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r | |
| 77 | TO_HANDLER\r | |
| 78 | \r | |
| 79 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_IRQ)\r | |
| 80 | _DefaultIrq_LowerA64:\r | |
| 81 | mov x0, #EXCEPT_AARCH64_IRQ\r | |
| 82 | TO_HANDLER\r | |
| 83 | \r | |
| 84 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_FIQ)\r | |
| 85 | _DefaultFiq_LowerA64:\r | |
| 86 | mov x0, #EXCEPT_AARCH64_FIQ\r | |
| 87 | TO_HANDLER\r | |
| 88 | \r | |
| 89 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SERR)\r | |
| 90 | _DefaultSError_LowerA64:\r | |
| 91 | mov x0, #EXCEPT_AARCH64_SERROR\r | |
| 92 | TO_HANDLER\r | |
| 93 | \r | |
| 94 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SYNC)\r | |
| 95 | _DefaultSyncExceptHandler_LowerA32:\r | |
| 96 | mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r | |
| 97 | TO_HANDLER\r | |
| 98 | \r | |
| 99 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_IRQ)\r | |
| 100 | _DefaultIrq_LowerA32:\r | |
| 101 | mov x0, #EXCEPT_AARCH64_IRQ\r | |
| 102 | TO_HANDLER\r | |
| 103 | \r | |
| 104 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_FIQ)\r | |
| 105 | _DefaultFiq_LowerA32:\r | |
| 106 | mov x0, #EXCEPT_AARCH64_FIQ\r | |
| 107 | TO_HANDLER\r | |
| 108 | \r | |
| 109 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SERR)\r | |
| 110 | _DefaultSError_LowerA32:\r | |
| 111 | mov x0, #EXCEPT_AARCH64_SERROR\r | |
| 112 | TO_HANDLER\r | |
| 113 | \r | |
| d855b261 | 114 | VECTOR_END(PeiVectorTable)\r |