projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 1bc83266 | 1 | #========================================================================================\r |
| 0e077330 | 2 | # Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r |
| 1bc83266 | 3 | #\r |
| f4dfad05 | 4 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 1bc83266 HL |
5 | #\r |
| 6 | #=======================================================================================\r | |
| 7 | \r | |
| 8 | #include <AsmMacroIoLibV8.h>\r | |
| 9 | #include <Chipset/AArch64.h>\r | |
| 10 | \r | |
| 1bc83266 | 11 | // Setup EL1 while in EL1\r |
| 13dc7fa5 | 12 | ASM_FUNC(SetupExceptionLevel1)\r |
| 1bc83266 HL |
13 | mov x5, x30 // Save LR\r |
| 14 | \r | |
| 15 | mov x0, #CPACR_CP_FULL_ACCESS\r | |
| 16 | bl ASM_PFX(ArmWriteCpacr) // Disable copro traps to EL1\r | |
| 17 | \r | |
| 18 | ret x5\r | |
| 19 | \r | |
| 20 | // Setup EL2 while in EL2\r | |
| 13dc7fa5 | 21 | ASM_FUNC(SetupExceptionLevel2)\r |
| 1bc83266 HL |
22 | msr sctlr_el2, xzr\r |
| 23 | mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register\r | |
| 24 | \r | |
| 25 | // Send all interrupts to their respective Exception levels for EL2\r | |
| 26 | orr x0, x0, #(1 << 3) // Enable EL2 FIQ\r | |
| 27 | orr x0, x0, #(1 << 4) // Enable EL2 IRQ\r | |
| 28 | orr x0, x0, #(1 << 5) // Enable EL2 SError and Abort\r | |
| 29 | msr hcr_el2, x0 // Write back our settings\r | |
| 30 | \r | |
| 31 | msr cptr_el2, xzr // Disable copro traps to EL2\r | |
| 32 | \r | |
| 0e077330 SM |
33 | // Enable Timer access for non-secure EL1 and EL0\r |
| 34 | // The cnthctl_el2 register bits are architecturally\r | |
| 35 | // UNKNOWN on reset.\r | |
| 36 | // Disable event stream as it is not in use at this stage\r | |
| 37 | mov x0, #(CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN)\r | |
| 38 | msr cnthctl_el2, x0\r | |
| 39 | \r | |
| 1bc83266 HL |
40 | ret\r |
| 41 | \r | |
| 1bc83266 | 42 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |