]>
Commit | Line | Data |
---|---|---|
1bc83266 | 1 | //\r |
eaa84fd5 | 2 | // Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
1bc83266 HL |
3 | //\r |
4 | // This program and the accompanying materials\r | |
5 | // are licensed and made available under the terms and conditions of the BSD License\r | |
6 | // which accompanies this distribution. The full text of the license may be found at\r | |
7 | // http://opensource.org/licenses/bsd-license.php\r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | //\r | |
12 | //\r | |
13 | \r | |
14 | #include <AsmMacroIoLibV8.h>\r | |
1bc83266 | 15 | \r |
13dc7fa5 | 16 | ASM_FUNC(_ModuleEntryPoint)\r |
1bc83266 HL |
17 | // Do early platform specific actions\r |
18 | bl ASM_PFX(ArmPlatformPeiBootAction)\r | |
19 | \r | |
20 | // NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect\r | |
21 | // and configure the system accordingly. EL2 is default if possible.\r | |
22 | // If we started in EL3 we need to switch and run at EL2.\r | |
23 | // If we are running at EL2 stay in EL2\r | |
24 | // If we are starting at EL1 stay in EL1.\r | |
25 | \r | |
26 | // If started at EL3 Sec is run and switches to EL2 before jumping to PEI.\r | |
27 | // If started at EL1 or EL2 Sec jumps directly to PEI without making any\r | |
28 | // changes.\r | |
29 | \r | |
30 | // Which EL are we running at? Every EL needs some level of setup...\r | |
eaa84fd5 OM |
31 | // We should not run this code in EL3\r |
32 | EL1_OR_EL2(x0)\r | |
1bc83266 HL |
33 | 1:bl ASM_PFX(SetupExceptionLevel1)\r |
34 | b ASM_PFX(MainEntryPoint)\r | |
35 | 2:bl ASM_PFX(SetupExceptionLevel2)\r | |
36 | b ASM_PFX(MainEntryPoint)\r | |
1bc83266 HL |
37 | \r |
38 | ASM_PFX(MainEntryPoint):\r | |
39 | // Identify CPU ID\r | |
40 | bl ASM_PFX(ArmReadMpidr)\r | |
41 | // Keep a copy of the MpId register value\r | |
42 | mov x5, x0\r | |
43 | \r | |
44 | // Is it the Primary Core ?\r | |
45 | bl ASM_PFX(ArmPlatformIsPrimaryCore)\r | |
46 | \r | |
47 | // Get the top of the primary stacks (and the base of the secondary stacks)\r | |
13dc7fa5 | 48 | MOV64 (x1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize))\r |
1bc83266 HL |
49 | \r |
50 | // x0 is equal to 1 if I am the primary core\r | |
51 | cmp x0, #1\r | |
52 | b.eq _SetupPrimaryCoreStack\r | |
53 | \r | |
54 | _SetupSecondaryCoreStack:\r | |
55 | // x1 contains the base of the secondary stacks\r | |
56 | \r | |
57 | // Get the Core Position\r | |
58 | mov x6, x1 // Save base of the secondary stacks\r | |
59 | mov x0, x5\r | |
60 | bl ASM_PFX(ArmPlatformGetCorePosition)\r | |
61 | // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r | |
62 | add x0, x0, #1\r | |
63 | \r | |
64 | // StackOffset = CorePos * StackSize\r | |
13dc7fa5 | 65 | MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecondaryStackSize))\r |
1bc83266 HL |
66 | mul x0, x0, x2\r |
67 | // SP = StackBase + StackOffset\r | |
68 | add sp, x6, x0\r | |
69 | \r | |
70 | _PrepareArguments:\r | |
71 | // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r | |
13dc7fa5 AB |
72 | MOV64 (x2, FixedPcdGet64(PcdFvBaseAddress))\r |
73 | ldr x1, [x2, #8]\r | |
1bc83266 HL |
74 | \r |
75 | // Move sec startup address into a data register\r | |
76 | // Ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
13dc7fa5 | 77 | ldr x3, =ASM_PFX(CEntryPoint)\r |
1bc83266 HL |
78 | \r |
79 | // Jump to PrePeiCore C code\r | |
80 | // x0 = mp_id\r | |
81 | // x1 = pei_core_address\r | |
82 | mov x0, x5\r | |
83 | blr x3\r | |
84 | \r | |
85 | _SetupPrimaryCoreStack:\r | |
3707dee3 | 86 | mov sp, x1\r |
1bc83266 | 87 | b _PrepareArguments\r |