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1d5d0ae9 | 1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | *\r | |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
55a0d64b | 15 | #include <Library/ArmGicLib.h>\r |
1d5d0ae9 | 16 | #include <Library/ArmMPCoreMailBoxLib.h>\r |
17 | #include <Chipset/ArmV7.h>\r | |
1d5d0ae9 | 18 | \r |
f598bf12 | 19 | #include "PrePeiCore.h"\r |
20 | \r | |
1d5d0ae9 | 21 | /*\r |
22 | * This is the main function for secondary cores. They loop around until a non Null value is written to\r | |
23 | * SYS_FLAGS register.The SYS_FLAGS register is platform specific.\r | |
24 | * Note:The secondary cores, while executing secondary_main, assumes that:\r | |
25 | * : SGI 0 is configured as Non-secure interrupt\r | |
26 | * : Priority Mask is configured to allow SGI 0\r | |
27 | * : Interrupt Distributor and CPU interfaces are enabled\r | |
28 | *\r | |
29 | */\r | |
30 | VOID\r | |
31 | EFIAPI\r | |
f598bf12 | 32 | SecondaryMain (\r |
0787bc61 | 33 | IN UINTN MpId\r |
f598bf12 | 34 | )\r |
1d5d0ae9 | 35 | {\r |
f598bf12 | 36 | // Function pointer to Secondary Core entry point\r |
37 | VOID (*secondary_start)(VOID);\r | |
38 | UINTN secondary_entry_addr=0;\r | |
1d5d0ae9 | 39 | \r |
f598bf12 | 40 | // Clear Secondary cores MailBox\r |
41 | ArmClearMPCoreMailbox();\r | |
1d5d0ae9 | 42 | \r |
f598bf12 | 43 | while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r |
44 | ArmCallWFI();\r | |
45 | // Acknowledge the interrupt and send End of Interrupt signal.\r | |
0787bc61 | 46 | ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r |
f598bf12 | 47 | }\r |
1d5d0ae9 | 48 | \r |
f598bf12 | 49 | secondary_start = (VOID (*)())secondary_entry_addr;\r |
1d5d0ae9 | 50 | \r |
f598bf12 | 51 | // Jump to secondary core entry point.\r |
52 | secondary_start();\r | |
1d5d0ae9 | 53 | \r |
f598bf12 | 54 | // The secondaries shouldn't reach here\r |
55 | ASSERT(FALSE);\r | |
1d5d0ae9 | 56 | }\r |
57 | \r | |
f598bf12 | 58 | VOID\r |
59 | EFIAPI\r | |
60 | PrimaryMain (\r | |
1d5d0ae9 | 61 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r |
62 | )\r | |
63 | {\r | |
f598bf12 | 64 | EFI_SEC_PEI_HAND_OFF SecCoreData;\r |
1d5d0ae9 | 65 | \r |
55a0d64b | 66 | // Enable the GIC Distributor\r |
67 | ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r | |
1d5d0ae9 | 68 | \r |
f598bf12 | 69 | // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r |
55a0d64b | 70 | if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {\r |
f598bf12 | 71 | // Sending SGI to all the Secondary CPU interfaces\r |
55a0d64b | 72 | ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r |
f598bf12 | 73 | }\r |
1d5d0ae9 | 74 | \r |
f598bf12 | 75 | //\r |
76 | // Bind this information into the SEC hand-off state\r | |
77 | // Note: this must be in sync with the stuff in the asm file\r | |
78 | // Note also: HOBs (pei temp ram) MUST be above stack\r | |
79 | //\r | |
80 | SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r | |
f92b93c9 | 81 | SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);\r |
82 | SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r | |
2dbcb8f0 | 83 | SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize); // We consider we run on the primary core (and so we use the first stack)\r |
84 | SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize);\r | |
f598bf12 | 85 | SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r |
86 | SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r | |
87 | SecCoreData.StackBase = SecCoreData.TemporaryRamBase;\r | |
88 | SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r | |
1d5d0ae9 | 89 | \r |
f598bf12 | 90 | // Jump to PEI core entry point\r |
91 | (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r | |
1d5d0ae9 | 92 | }\r |